drm/amd/display: clean up one inconsistent indenting

1. The indentation of statements in the same curly bracket should be
consistent.
2. Variable declarations in the same function should be aligned.

Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1887
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1888
Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=1889
Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 1b62be8..9f8976b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -2169,13 +2169,16 @@ void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_pa
 
                        if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
                                if (bb_info.dram_clock_change_latency_100ns > 0)
-                                       dcn3_2_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
+                                       dcn3_2_soc.dram_clock_change_latency_us =
+                                               bb_info.dram_clock_change_latency_100ns * 10;
 
-                       if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
-                               dcn3_2_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
+                               if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
+                                       dcn3_2_soc.sr_enter_plus_exit_time_us =
+                                               bb_info.dram_sr_enter_exit_latency_100ns * 10;
 
-                       if (bb_info.dram_sr_exit_latency_100ns > 0)
-                               dcn3_2_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
+                               if (bb_info.dram_sr_exit_latency_100ns > 0)
+                                       dcn3_2_soc.sr_exit_time_us =
+                                               bb_info.dram_sr_exit_latency_100ns * 10;
                        }
                }
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 3040428..d8014bf 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -677,9 +677,9 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
                                dml_ceil((double) v->WritebackDelay[mode_lib->vba.VoltageLevel][k]
                                / (mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]), 1));
 
-       // Clamp to max OTG vstartup register limit
-       if (v->MaxVStartupLines[k] > 1023)
-               v->MaxVStartupLines[k] = 1023;
+               // Clamp to max OTG vstartup register limit
+               if (v->MaxVStartupLines[k] > 1023)
+                       v->MaxVStartupLines[k] = 1023;
 
 #ifdef __DML_VBA_DEBUG__
                dml_print("DML::%s: k=%d MaxVStartupLines = %d\n", __func__, k, v->MaxVStartupLines[k]);

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
index 6b3c4db..dc501ee 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c
@@ -4280,7 +4280,7 @@ void dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport(
        double ActiveClockChangeLatencyHidingY;
        double ActiveClockChangeLatencyHidingC;
        double ActiveClockChangeLatencyHiding;
-    double EffectiveDETBufferSizeY;
+       double EffectiveDETBufferSizeY;
        double     ActiveFCLKChangeLatencyMargin[DC__NUM_DPP__MAX];
        double     USRRetrainingLatencyMargin[DC__NUM_DPP__MAX];
        double TotalPixelBW = 0.0;