fimc-is-device-companion.o \
fimc-is-video-companion.o
+obj-$(CONFIG_VIDEO_EXYNOS_FIMC_IS) += setup-fimc-is.o
+obj-$(CONFIG_VIDEO_EXYNOS_FIMC_IS) += setup-fimc-is-sensor.o
+obj-$(CONFIG_VIDEO_EXYNOS_FIMC_IS) += setup-fimc-is-companion.o
+
obj-$(CONFIG_VIDEO_EXYNOS_FIMC_IS) += fimc-is.o
obj-$(CONFIG_OIS_USE) += fimc-is-device-ois.o
obj-$(CONFIG_AF_HOST_CONTROL) += fimc-is-device-af.o
--- /dev/null
+/*
+ * /include/media/exynos_fimc_is_sensor.h
+ *
+ * Copyright (C) 2012 Samsung Electronics, Co. Ltd
+ *
+ * Exynos series exynos_fimc_is_sensor device support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef MEDIA_EXYNOS_SENSOR_H
+#define MEDIA_EXYNOS_SENSOR_H
+
+#include "exynos-fimc-is.h"
+
+#define FIMC_IS_SENSOR_DEV_NAME "exynos-fimc-is-sensor"
+#define FIMC_IS_PINNAME_LEN 32
+#define FIMC_IS_MAX_NAME_LEN 32
+
+enum exynos_csi_id {
+ CSI_ID_A = 0,
+ CSI_ID_B = 1,
+ CSI_ID_C = 2,
+ CSI_ID_MAX
+};
+
+enum exynos_flite_id {
+ FLITE_ID_A = 0,
+ FLITE_ID_B = 1,
+ FLITE_ID_C = 2,
+ FLITE_ID_D = 3,
+ FLITE_ID_END,
+ FLITE_ID_NOTHING = 100,
+};
+
+enum exynos_sensor_channel {
+ SENSOR_CONTROL_I2C0 = 0,
+ SENSOR_CONTROL_I2C1 = 1,
+ SENSOR_CONTROL_I2C2 = 2
+};
+
+enum exynos_sensor_position {
+ SENSOR_POSITION_REAR = 0,
+ SENSOR_POSITION_FRONT
+};
+
+enum exynos_sensor_id {
+ SENSOR_NAME_NOTHING = 0,
+ SENSOR_NAME_S5K3H2 = 1,
+ SENSOR_NAME_S5K6A3 = 2,
+ SENSOR_NAME_S5K3H5 = 3,
+ SENSOR_NAME_S5K3H7 = 4,
+ SENSOR_NAME_S5K3H7_SUNNY = 5,
+ SENSOR_NAME_S5K3H7_SUNNY_2M = 6,
+ SENSOR_NAME_S5K6B2 = 7,
+ SENSOR_NAME_S5K3L2 = 8,
+ SENSOR_NAME_S5K4E5 = 9,
+ SENSOR_NAME_S5K2P2 = 10,
+ SENSOR_NAME_S5K8B1 = 11,
+ SENSOR_NAME_S5K1P2 = 12,
+ SENSOR_NAME_S5K4H5 = 13,
+ SENSOR_NAME_S5K2P2_12M = 15,
+ SENSOR_NAME_S5K6D1 = 16,
+ SENSOR_NAME_S5K2P3 = 19,
+ SENSOR_NAME_S5K4EC = 57,
+ SENSOR_NAME_SR352 = 57,
+ SENSOR_NAME_SR030 = 57,
+
+ SENSOR_NAME_IMX135 = 101, /* 101 ~ 200 Sony sensors */
+ SENSOR_NAME_IMX134 = 102,
+ SENSOR_NAME_IMX175 = 103,
+ SENSOR_NAME_IMX240 = 104,
+ SENSOR_NAME_IMX219 = 107,
+
+ SENSOR_NAME_SR261 = 201, /* 201 ~ 300 Other vendor sensors */
+
+ SENSOR_NAME_END,
+ SENSOR_NAME_CUSTOM = 301,
+};
+
+enum actuator_name {
+ ACTUATOR_NAME_AD5823 = 1,
+ ACTUATOR_NAME_DWXXXX = 2,
+ ACTUATOR_NAME_AK7343 = 3,
+ ACTUATOR_NAME_HYBRIDVCA = 4,
+ ACTUATOR_NAME_LC898212 = 5,
+ ACTUATOR_NAME_WV560 = 6,
+ ACTUATOR_NAME_AK7345 = 7,
+ ACTUATOR_NAME_DW9804 = 8,
+ ACTUATOR_NAME_AK7348 = 9,
+ ACTUATOR_NAME_END,
+ ACTUATOR_NAME_NOTHING = 100,
+};
+
+enum flash_drv_name {
+ FLADRV_NAME_KTD267 = 1, /* Gpio type(Flash mode, Movie/torch mode) */
+ FLADRV_NAME_AAT1290A = 2,
+ FLADRV_NAME_MAX77693 = 3,
+ FLADRV_NAME_AS3643 = 4,
+ FLADRV_NAME_KTD2692 = 5,
+ FLADRV_NAME_LM3560 = 6,
+ FLADRV_NAME_SKY81296 = 7,
+ FLADRV_NAME_RT5033 = 8,
+ FLADRV_NAME_END,
+ FLADRV_NAME_NOTHING = 100,
+};
+
+enum from_name {
+ FROMDRV_NAME_W25Q80BW = 1, /* Spi type */
+ FROMDRV_NAME_FM25M16A = 2, /* Spi type */
+ FROMDRV_NAME_FM25M32A = 3,
+ FROMDRV_NAME_NOTHING = 100,
+};
+
+enum companion_name {
+ COMPANION_NAME_73C1 = 1, /* SPI, I2C, FIMC Lite */
+ COMPANION_NAME_END,
+ COMPANION_NAME_NOTHING = 100,
+};
+
+enum ois_name {
+ OIS_NAME_IDG2030 = 1,
+ OIS_NAME_END,
+ OIS_NAME_NOTHING = 100,
+};
+
+enum sensor_peri_type {
+ SE_NULL = 0,
+ SE_I2C = 1,
+ SE_SPI = 2,
+ SE_GPIO = 3,
+ SE_MPWM = 4,
+ SE_ADC = 5,
+ SE_FIMC_LITE = 6,
+};
+
+struct i2c_type {
+ u32 channel;
+ u32 slave_address;
+ u32 speed;
+};
+
+struct spi_type {
+ u32 channel;
+};
+
+struct gpio_type {
+ u32 first_gpio_port_no;
+ u32 second_gpio_port_no;
+};
+
+struct fimc_lite_type {
+ u32 channel;
+};
+
+union sensor_peri_format {
+ struct i2c_type i2c;
+ struct spi_type spi;
+ struct gpio_type gpio;
+ struct fimc_lite_type fimc_lite;
+};
+
+struct sensor_protocol {
+ u32 product_name;
+ enum sensor_peri_type peri_type;
+ union sensor_peri_format peri_setting;
+ u32 csi_ch;
+ u32 cal_address;
+ u32 reserved[2];
+};
+
+struct sensor_peri_info {
+ bool valid;
+ enum sensor_peri_type peri_type;
+ union sensor_peri_format peri_setting;
+};
+
+struct sensor_companion {
+ u32 product_name; /* enum companion_name */
+ struct sensor_peri_info peri_info0;
+ struct sensor_peri_info peri_info1;
+ struct sensor_peri_info peri_info2;
+ struct sensor_peri_info reserved[2];
+};
+
+struct sensor_open_extended {
+ struct sensor_protocol sensor_con;
+ struct sensor_protocol actuator_con;
+ struct sensor_protocol flash_con;
+ struct sensor_protocol from_con;
+ struct sensor_companion companion_con;
+ struct sensor_protocol ois_con;
+
+ u32 mclk;
+ u32 mipi_lane_num;
+ u32 mipi_settle_line;
+ u32 mipi_speed;
+ /* Skip setfile loading when fast_open_sensor is not 0 */
+ u32 fast_open_sensor;
+ /* Activatiing sensor self calibration mode (6A3) */
+ u32 self_calibration_mode;
+ /* This field is to adjust I2c clock based on ACLK200 */
+ /* This value is varied in case of rev 0.2 */
+ u32 I2CSclk;
+};
+
+#define GPIO_SCENARIO_ON 0
+#define GPIO_SCENARIO_OFF 1
+#define GPIO_SCENARIO_MAX 2
+#define GPIO_CTRL_MAX 32
+
+#define SENSOR_SCENARIO_NORMAL 0
+#define SENSOR_SCENARIO_VISION 1
+#define SENSOR_SCENARIO_EXTERNAL 2
+#define SENSOR_SCENARIO_OIS_FACTORY 3
+#define SENSOR_SCENARIO_MAX 10
+
+enum pin_act {
+ PIN_PULL_NONE = 0,
+ PIN_OUTPUT_HIGH,
+ PIN_OUTPUT_LOW,
+ PIN_OUTPUT,
+ PIN_INPUT,
+ PIN_RESET,
+ PIN_FUNCTION,
+ PIN_REGULATOR_ON,
+ PIN_REGULATOR_OFF,
+ PIN_REGULATOR,
+ PIN_DELAY,
+ PIN_END
+};
+
+struct exynos_sensor_pin {
+ unsigned long pin;
+ int delay;
+ u32 value;
+ char *name;
+ enum pin_act act;
+ int voltage;
+};
+
+#ifdef CONFIG_USE_VENDER_FEATURE
+#define SET_PIN(p, id1, id2, n, _pin, _value, _name, _time, _act) \
+ (p)->pin_ctrls[id1][id2][n].pin = _pin; \
+ (p)->pin_ctrls[id1][id2][n].delay = _time; \
+ (p)->pin_ctrls[id1][id2][n].value = _value; \
+ (p)->pin_ctrls[id1][id2][n].name = _name; \
+ (p)->pin_ctrls[id1][id2][n].act = _act; \
+ (p)->pin_ctrls[id1][id2][n].voltage = 0;
+#else
+#define SET_PIN(d, s, c, i, p , v, n, a) \
+ (d)->pin_ctrls[s][c][i].pin = p; \
+ (d)->pin_ctrls[s][c][i].value = v; \
+ (d)->pin_ctrls[s][c][i].name = n; \
+ (d)->pin_ctrls[s][c][i].act = a;
+#endif
+
+/*
+ * struct exynos_platform_fimc_is_sensor - platform data for exynos_sensor driver
+ */
+struct exynos_platform_fimc_is_sensor {
+ int (*gpio_cfg)(struct platform_device *pdev, u32 scenario, u32 enable);
+ int (*iclk_cfg)(struct platform_device *pdev, u32 scenario, u32 channel);
+ int (*iclk_on)(struct platform_device *pdev,u32 scenario, u32 channel);
+ int (*iclk_off)(struct platform_device *pdev, u32 scenario, u32 channel);
+ int (*mclk_on)(struct platform_device *pdev, u32 scenario, u32 channel);
+ int (*mclk_off)(struct platform_device *pdev, u32 scenario, u32 channel);
+ struct exynos_sensor_pin pin_ctrls[SENSOR_SCENARIO_MAX][GPIO_SCENARIO_MAX][GPIO_CTRL_MAX];
+ char sensor_name[FIMC_IS_MAX_NAME_LEN];
+ u32 scenario;
+ u32 id;
+ u32 mclk_ch;
+ u32 csi_ch;
+ u32 flite_ch;
+ u32 i2c_ch;
+ u32 i2c_addr;
+ u32 is_bns;
+ u32 flash_first_gpio;
+ u32 flash_second_gpio;
+ u32 is_softlanding;
+ u32 sensor_id;
+ bool companion_use_pmic;
+#ifdef CONFIG_OIS_USE
+ int pin_ois_en;
+#endif
+ struct pinctrl *pinctrl;
+};
+
+extern int exynos_fimc_is_sensor_pins_cfg(struct platform_device *pdev,
+ u32 scenario,
+ u32 enable);
+extern int exynos_fimc_is_sensor_iclk_cfg(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel);
+extern int exynos_fimc_is_sensor_iclk_on(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel);
+extern int exynos_fimc_is_sensor_iclk_off(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel);
+extern int exynos_fimc_is_sensor_mclk_on(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel);
+extern int exynos_fimc_is_sensor_mclk_off(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel);
+
+extern int exynos_fimc_is_companion_iclk_cfg(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel);
+extern int exynos_fimc_is_companion_iclk_on(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel);
+extern int exynos_fimc_is_companion_iclk_off(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel);
+extern int exynos_fimc_is_companion_mclk_on(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel);
+extern int exynos_fimc_is_companion_mclk_off(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel);
+
+#endif /* MEDIA_EXYNOS_SENSOR_H */
--- /dev/null
+/* linux/arch/arm/plat-s5p/include/plat/fimc_is.h
+ *
+ * Copyright (C) 2011 Samsung Electronics, Co. Ltd
+ *
+ * Exynos 4 series FIMC-IS slave device support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef EXYNOS_FIMC_IS_H_
+#define EXYNOS_FIMC_IS_H_ __FILE__
+
+#define FIMC_IS_MAKE_QOS_IDX_NM(__LV) __LV ## _IDX
+#define FIMC_IS_DECLARE_QOS_ENUM(__TYPE) enum FIMC_IS_DVFS_ ## __TYPE ## _LV_IDX
+
+#include <linux/videodev2.h>
+#if defined(CONFIG_ARCH_EXYNOS4)
+#include <media/s5p_fimc.h>
+#endif
+
+#define FIMC_IS_DEV_NAME "exynos-fimc-is"
+#include <linux/platform_device.h>
+
+/* FIMC-IS DVFS LEVEL enum (INT, MIF, I2C) */
+enum FIMC_IS_INT_LV {
+ FIMC_IS_INT_L0,
+ FIMC_IS_INT_L1,
+ FIMC_IS_INT_L1_1,
+ FIMC_IS_INT_L1_2,
+ FIMC_IS_INT_L1_3,
+};
+
+enum FIMC_IS_MIF_LV {
+ FIMC_IS_MIF_L0,
+ FIMC_IS_MIF_L1,
+ FIMC_IS_MIF_L2,
+ FIMC_IS_MIF_L3,
+ FIMC_IS_MIF_L4,
+};
+
+/*
+ * On some soc, It needs to notify change of INT clock to F/W.
+ * Because I2C clock can be take affect from other clock change(like INT)
+ */
+enum FIMC_IS_I2C_LV {
+ FIMC_IS_I2C_L0,
+ FIMC_IS_I2C_L1,
+ FIMC_IS_I2C_L1_1,
+ FIMC_IS_I2C_L1_3,
+};
+
+/* FIMC-IS DVFS SCENARIO enum */
+enum FIMC_IS_SCENARIO_ID {
+ FIMC_IS_SN_DEFAULT,
+ FIMC_IS_SN_FRONT_PREVIEW,
+ FIMC_IS_SN_FRONT_CAPTURE,
+ FIMC_IS_SN_FRONT_CAMCORDING,
+ FIMC_IS_SN_FRONT_VT1,
+ FIMC_IS_SN_FRONT_VT2,
+ FIMC_IS_SN_REAR_PREVIEW_FHD,
+ FIMC_IS_SN_REAR_PREVIEW_FHD_BNS_OFF,
+ FIMC_IS_SN_REAR_PREVIEW_WHD,
+ FIMC_IS_SN_REAR_PREVIEW_UHD,
+ FIMC_IS_SN_REAR_CAPTURE,
+ FIMC_IS_SN_REAR_CAMCORDING_FHD,
+ FIMC_IS_SN_REAR_CAMCORDING_FHD_BNS_OFF,
+ FIMC_IS_SN_REAR_CAMCORDING_WHD,
+ FIMC_IS_SN_REAR_CAMCORDING_UHD,
+ FIMC_IS_SN_DUAL_PREVIEW,
+ FIMC_IS_SN_DUAL_CAPTURE,
+ FIMC_IS_SN_DUAL_CAMCORDING,
+ FIMC_IS_SN_HIGH_SPEED_FPS,
+ FIMC_IS_SN_DIS_ENABLE,
+ FIMC_IS_SN_MAX,
+ FIMC_IS_SN_END,
+};
+
+enum FIMC_IS_DVFS_QOS_TYPE {
+ FIMC_IS_DVFS_CPU_MIN,
+ FIMC_IS_DVFS_CPU_MAX,
+ FIMC_IS_DVFS_INT,
+ FIMC_IS_DVFS_MIF,
+ FIMC_IS_DVFS_I2C,
+ FIMC_IS_DVFS_CAM,
+ FIMC_IS_DVFS_DISP,
+ FIMC_IS_DVFS_PWM,
+ FIMC_IS_DVFS_END,
+};
+
+#define SET_QOS_WITH_CPU(t, s, i, m, _i, c, d, p, cmin, cmax) \
+ (t)[s][FIMC_IS_DVFS_INT] = i; \
+ (t)[s][FIMC_IS_DVFS_MIF] = m; \
+ (t)[s][FIMC_IS_DVFS_I2C] = _i; \
+ (t)[s][FIMC_IS_DVFS_CAM] = c; \
+ (t)[s][FIMC_IS_DVFS_DISP] = d; \
+ (t)[s][FIMC_IS_DVFS_PWM] = p; \
+ (t)[s][FIMC_IS_DVFS_CPU_MIN] = cmin; \
+ (t)[s][FIMC_IS_DVFS_CPU_MAX] = cmax;
+
+#define SET_QOS(t, s, i, m, _i, c, d, p) \
+ (t)[s][FIMC_IS_DVFS_INT] = i; \
+ (t)[s][FIMC_IS_DVFS_MIF] = m; \
+ (t)[s][FIMC_IS_DVFS_I2C] = _i; \
+ (t)[s][FIMC_IS_DVFS_CAM] = c; \
+ (t)[s][FIMC_IS_DVFS_DISP] = d; \
+ (t)[s][FIMC_IS_DVFS_PWM] = p; \
+ (t)[s][FIMC_IS_DVFS_CPU_MIN] = 0; \
+ (t)[s][FIMC_IS_DVFS_CPU_MAX] = 0;
+
+enum FIMC_IS_CLK_GATE {
+ FIMC_IS_GATE_3AA1_IP,
+ FIMC_IS_GATE_ISP_IP,
+ FIMC_IS_GATE_DRC_IP,
+ FIMC_IS_GATE_SCC_IP,
+ FIMC_IS_GATE_ODC_IP,
+ FIMC_IS_GATE_DIS_IP,
+ FIMC_IS_GATE_3DNR_IP,
+ FIMC_IS_GATE_SCP_IP,
+ FIMC_IS_GATE_FD_IP,
+ FIMC_IS_GATE_3AA0_IP,
+ FIMC_IS_CLK_GATE_MAX,
+};
+
+enum FIMC_IS_GRP {
+ FIMC_IS_GRP_3A0,
+ FIMC_IS_GRP_3A1,
+ FIMC_IS_GRP_ISP,
+ FIMC_IS_GRP_DIS,
+ FIMC_IS_GRP_MAX,
+};
+
+enum FIMC_IS_CLK_GATE_USR_SCENARIO {
+ CLK_GATE_NOT_FULL_BYPASS_SN = 1,
+ CLK_GATE_FULL_BYPASS_SN,
+ CLK_GATE_DIS_SN,
+};
+
+/*
+ * struct exynos_fimc_is_subip_info
+ * This info describes what and how many subip fimc-is has.
+ * In machine data, this info should be defined.
+ */
+struct exynos_fimc_is_subip_ext {
+ bool valid;
+ bool full_bypass;
+ u32 version;
+ u32 base_addr;
+};
+
+struct exynos_fimc_is_subip_info {
+ /* You can add more new subip */
+ struct exynos_fimc_is_subip_ext _mcuctl;
+ struct exynos_fimc_is_subip_ext _3a0;
+ struct exynos_fimc_is_subip_ext _3a1;
+ struct exynos_fimc_is_subip_ext _isp;
+ struct exynos_fimc_is_subip_ext _drc;
+ struct exynos_fimc_is_subip_ext _scc;
+ struct exynos_fimc_is_subip_ext _odc;
+ struct exynos_fimc_is_subip_ext _dis;
+ struct exynos_fimc_is_subip_ext _dnr;
+ struct exynos_fimc_is_subip_ext _scp;
+ struct exynos_fimc_is_subip_ext _fd;
+ struct exynos_fimc_is_subip_ext _pwm;
+};
+
+/*
+ * struct exynos_fimc_is_clk_gate_group
+ * This struct is for host clock gating.
+ * It decsribes register, masking bit info and other control for each group.
+ * If you uses host clock gating, You must define this struct in exynos_fimc_is_clk_gate_info.
+ */
+struct exynos_fimc_is_clk_gate_group {
+ u32 mask_clk_on_org; /* masking value in clk on */
+ u32 mask_clk_on_mod; /* masking value in clk on */
+ u32 mask_clk_off_self_org; /* masking value in clk off(not depend) original */
+ u32 mask_clk_off_self_mod; /* masking value in clk off(not depend) final */
+ u32 mask_clk_off_depend; /* masking value in clk off(depend on other grp) */
+ u32 mask_cond_for_depend; /* masking group having dependancy for other */
+};
+
+/*
+ * struct exynos_fimc_is_clk_gate_info
+ * This struct is for host clock gating.
+ * It has exynos_fimc_is_clk_gate_group to control each group's clk gating.
+ * And it has function pointer to include user scenario masking
+ */
+struct exynos_fimc_is_clk_gate_info {
+ const char *gate_str[FIMC_IS_CLK_GATE_MAX]; /* register adr for gating */
+ struct exynos_fimc_is_clk_gate_group groups[FIMC_IS_GRP_MAX];
+ /* You must set this function pointer (on/off) */
+ int (*clk_on_off)(u32 clk_gate_id, bool is_on);
+ /*
+ * if there are specific scenarios for clock gating,
+ * You can define user function.
+ * user_scenario_id will be in
+ */
+ int (*user_clk_gate)(u32 group_id,
+ bool is_on,
+ u32 user_scenario_id,
+ unsigned long msk_state,
+ struct exynos_fimc_is_clk_gate_info *gate_info);
+};
+
+/**
+* struct exynos_platform_fimc_is - camera host interface platform data
+*
+* @isp_info: properties of camera sensor required for host interface setup
+*/
+struct exynos_platform_fimc_is {
+ int hw_ver;
+ struct exynos_fimc_is_subip_info *subip_info;
+ int (*cfg_gpio)(struct platform_device *pdev, int channel, bool flag_on);
+ int (*clk_cfg)(struct platform_device *pdev);
+ int (*clk_on)(struct platform_device *pdev);
+ int (*clk_off)(struct platform_device *pdev);
+ int (*print_clk)(struct platform_device *pdev);
+ int (*print_cfg)(struct platform_device *pdev, u32 channel);
+ int (*print_pwr)(struct platform_device *pdev);
+
+ /* These fields are to return qos value for dvfs scenario */
+ u32 *int_qos_table;
+ u32 *mif_qos_table;
+ u32 *i2c_qos_table;
+ int (*get_int_qos)(int scenario_id);
+ int (*get_mif_qos)(int scenario_id);
+ int (*get_i2c_qos)(int scenario_id);
+ u32 dvfs_data[FIMC_IS_SN_END][FIMC_IS_DVFS_END];
+
+ /* For host clock gating */
+ struct exynos_fimc_is_clk_gate_info *gate_info;
+#ifdef CONFIG_COMPANION_USE
+ u32 companion_spi_channel;
+ bool use_two_spi_line;
+#endif
+ u32 use_sensor_dynamic_voltage_mode;
+#ifdef CONFIG_OIS_USE
+ bool use_ois;
+#endif /* CONFIG_OIS_USE */
+ bool use_ois_hsi2c;
+ bool use_module_check;
+};
+
+extern struct device *fimc_is_dev;
+
+extern void exynos_fimc_is_set_platdata(struct exynos_platform_fimc_is *pd);
+
+int fimc_is_set_parent_dt(struct platform_device *pdev,
+ const char *child, const char *parent);
+struct clk *fimc_is_get_parent_dt(struct platform_device *pdev,
+ const char *child);
+int fimc_is_set_rate_dt(struct platform_device *pdev,
+ const char *conid, unsigned int rate);
+unsigned int fimc_is_get_rate_dt(struct platform_device *pdev,
+ const char *conid);
+unsigned int fimc_is_enable_dt(struct platform_device *pdev,
+ const char *conid);
+void fimc_is_disable_dt(struct platform_device *pdev,
+ const char *conid);
+
+/* platform specific clock functions */
+#if defined(CONFIG_ARCH_EXYNOS4)
+/* exynos 4 */
+extern int exynos4_fimc_is_cfg_clk(struct platform_device *pdev);
+extern int exynos4_fimc_is_clk_on(struct platform_device *pdev);
+extern int exynos4_fimc_is_clk_off(struct platform_device *pdev);
+extern int exynos4_fimc_is_sensor_clock_on(struct platform_device *pdev, u32 source);
+extern int exynos4_fimc_is_sensor_clock_off(struct platform_device *pdev, u32 source);
+extern int exynos4_fimc_is_sensor_power_on(struct platform_device *pdev, int sensor_id);
+extern int exynos4_fimc_is_sensor_power_off(struct platform_device *pdev, int sensor_id);
+extern int exynos4_fimc_is_print_cfg(struct platform_device *pdev, u32 channel);
+extern int exynos4_fimc_is_cfg_gpio(struct platform_device *pdev, int channel, bool flag_on);
+#else /* exynos 4 */
+/* exynos 5 */
+extern int exynos_fimc_is_cfg_clk(struct platform_device *pdev);
+extern int exynos_fimc_is_cfg_cam_clk(struct platform_device *pdev);
+extern int exynos_fimc_is_clk_on(struct platform_device *pdev);
+extern int exynos_fimc_is_clk_off(struct platform_device *pdev);
+extern int exynos_fimc_is_print_clk(struct platform_device *pdev);
+extern int exynos_fimc_is_set_user_clk_gate(u32 group_id, bool is_on, u32 user_scenario_id,
+ unsigned long msk_state,
+ struct exynos_fimc_is_clk_gate_info *gate_info);
+extern int exynos_fimc_is_clk_gate(u32 clk_gate_id, bool is_on);
+
+extern int exynos_fimc_is_sensor_power_on(struct platform_device *pdev, int sensor_id);
+extern int exynos_fimc_is_sensor_power_off(struct platform_device *pdev, int sensor_id);
+extern int exynos_fimc_is_print_cfg(struct platform_device *pdev, u32 channel);
+extern int exynos_fimc_is_print_pwr(struct platform_device *pdev);
+#endif /* exynos 5*/
+#endif /* EXYNOS_FIMC_IS_H_ */
*/
#include <linux/sched.h>
-#include <mach/exynos-fimc-is-sensor.h>
-#include <mach/exynos-fimc-is.h>
-#include <media/exynos_mc.h>
+#include "exynos-fimc-is-sensor.h"
+#include "exynos-fimc-is.h"
+#include "media/exynos_mc.h"
#ifdef CONFIG_OF
#include <linux/of_gpio.h>
#endif
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/pm_runtime.h>
-#include <mach/exynos-fimc-is.h>
+#include "exynos-fimc-is.h"
#include <media/v4l2-device.h>
#include <media/v4l2-mediabus.h>
#include <media/v4l2-ioctl.h>
#ifndef fimc_is_device_companion_H
#define fimc_is_device_companion_H
-#include <mach/exynos-fimc-is-sensor.h>
+#include "exynos-fimc-is-sensor.h"
#include <linux/interrupt.h>
#include "fimc-is-video.h"
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
#include <linux/delay.h>
-#include <mach/exynos-fimc-is-sensor.h>
+#include "exynos-fimc-is-sensor.h"
#include <mach/pinctrl-samsung.h>
#ifdef CONFIG_OIS_FW_UPDATE_THREAD_USE
#include <linux/kthread.h>
#ifndef fimc_is_device_sensor_H
#define fimc_is_device_sensor_H
-#include <mach/exynos-fimc-is-sensor.h>
+#include "exynos-fimc-is-sensor.h"
#include "fimc-is-mem.h"
#include "fimc-is-video.h"
#include "fimc-is-resourcemgr.h"
*/
#include <linux/sched.h>
-#include <mach/exynos-fimc-is-sensor.h>
-#include <mach/exynos-fimc-is.h>
+#include "exynos-fimc-is-sensor.h"
+#include "exynos-fimc-is.h"
#include <media/exynos_mc.h>
#ifdef CONFIG_OF
#include <linux/of.h>
* published by the Free Software Foundation.
*/
-#include <mach/exynos-fimc-is-sensor.h>
+#include "exynos-fimc-is-sensor.h"
#ifndef FIMC_IS_DT_H
#define FIMC_IS_DT_H
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-subdev.h>
-#include <mach/exynos-fimc-is-sensor.h>
+#include "../exynos-fimc-is-sensor.h"
#include "../fimc-is-core.h"
#include "../fimc-is-device-sensor.h"
#include <media/v4l2-ctrls.h>
#include <media/v4l2-device.h>
#include <media/v4l2-subdev.h>
-#include <mach/exynos-fimc-is-sensor.h>
+#include "../exynos-fimc-is-sensor.h"
#include "../fimc-is-core.h"
#include "../fimc-is-device-sensor.h"
--- /dev/null
+/* linux/arch/arm/mach-exynos/setup-fimc-sensor.c
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * FIMC-IS-COMPANION gpio and clock configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/regulator/consumer.h>
+#include <linux/delay.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <mach/regs-gpio.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <plat/gpio-cfg.h>
+#include <plat/map-s5p.h>
+#include <plat/cpu.h>
+#ifdef CONFIG_OF
+#include <linux/of_gpio.h>
+#endif
+#if defined(CONFIG_SOC_EXYNOS5422)
+#include <mach/regs-clock-exynos5422.h>
+#elif defined(CONFIG_SOC_EXYNOS5430)
+#include <mach/regs-clock-exynos5430.h>
+#elif defined(CONFIG_SOC_EXYNOS5433)
+#include <mach/regs-clock-exynos5433.h>
+#endif
+
+#include "exynos-fimc-is.h"
+#include "exynos-fimc-is-sensor.h"
+
+#if defined(CONFIG_SOC_EXYNOS5422)
+int exynos5422_fimc_is_companion_iclk_cfg(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+ int ret = 0;
+
+ pr_info("clk_cfg:(ch%d),scenario(%d)\n", channel, scenario);
+
+ /* SCLK_SPI0_ISP */
+ fimc_is_set_parent_dt(pdev, "mout_spi0_isp", "mout_spll_ctrl");
+ fimc_is_set_rate_dt(pdev, "dout_spi0_isp", 200 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_spi0_isp_pre", 100 * 1000000);
+ /* SCLK_SPI1_ISP */
+ fimc_is_set_parent_dt(pdev, "mout_spi1_isp", "mout_spll_ctrl");
+ fimc_is_set_rate_dt(pdev, "dout_spi1_isp", 200 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_spi1_isp_pre", 100 * 1000000);
+
+ /* I2C */
+ /* CMU TOP */
+ /* 333_432_ISP */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_333_432_isp", "mout_ipll_ctrl");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_333_432_isp", (432 * 1000000));
+ fimc_is_set_parent_dt(pdev, "mout_aclk_333_432_isp_sw", "dout_aclk_333_432_isp");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_333_432_isp_user", "mout_aclk_333_432_isp_sw");
+
+ /* CMU ISP */
+ /* ACLK_DIV0 */
+ fimc_is_set_rate_dt(pdev, "dout_ispdiv0", (216 * 1000000));
+ /* ACLK_DIV1 */
+ fimc_is_set_rate_dt(pdev, "dout_ispdiv1", (108 * 1000000));
+ /* ACLK_DIV2 */
+ fimc_is_set_rate_dt(pdev, "dout_ispdiv2", (54 * 1000000));
+
+ return ret;
+}
+
+int exynos5422_fimc_is_companion_iclk_on(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+ return 0;
+}
+
+int exynos5422_fimc_is_companion_iclk_off(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+ return 0;
+}
+
+int exynos5422_fimc_is_companion_mclk_on(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+ u32 frequency;
+ char div_name[30];
+ char sclk_name[30];
+
+ pr_info("%s:ch(%d)\n", __func__, channel);
+
+ snprintf(div_name, sizeof(div_name), "dout_isp_sensor%d", channel);
+ snprintf(sclk_name, sizeof(sclk_name), "sclk_isp_sensor%d", channel);
+
+ fimc_is_set_parent_dt(pdev, "mout_isp_sensor", "fin_pll");
+ fimc_is_set_rate_dt(pdev, div_name, (24 * 1000000));
+ fimc_is_enable_dt(pdev, sclk_name);
+ frequency = fimc_is_get_rate_dt(pdev, div_name);
+
+ pr_info("%s(%d, mclk : %d)\n", __func__, channel, frequency);
+
+ return 0;
+}
+
+int exynos5422_fimc_is_companion_mclk_off(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+ pr_debug("%s\n", __func__);
+
+ fimc_is_disable_dt(pdev, "sclk_isp_sensor0");
+
+ return 0;
+}
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+int exynos5430_fimc_is_companion_iclk_div_max(struct platform_device *pdev)
+{
+ /* SCLK */
+ /* SCLK_SPI0 */
+ fimc_is_set_parent_dt(pdev, "mout_sclk_isp_spi0", "oscclk");
+ fimc_is_set_rate_dt(pdev, "dout_sclk_isp_spi0_a", 1);
+ fimc_is_set_rate_dt(pdev, "dout_sclk_isp_spi0_b", 1);
+ fimc_is_set_parent_dt(pdev, "mout_sclk_isp_spi0_user", "oscclk");
+
+ return 0;
+}
+
+int exynos5430_fimc_is_companion_iclk_cfg(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+ int ret = 0;
+
+ pr_info("clk_cfg:(ch%d),scenario(%d)\n", channel, scenario);
+
+ /* SCLK_SPI0_ISP */
+ fimc_is_set_parent_dt(pdev, "mout_sclk_isp_spi0", "mout_bus_pll_user");
+ fimc_is_set_rate_dt(pdev, "dout_sclk_isp_spi0_a", 200 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_sclk_isp_spi0_b", 100 * 1000000);
+ fimc_is_set_parent_dt(pdev, "mout_sclk_isp_spi0_user", "sclk_isp_spi0_top");
+#if 0
+ /* SCLK_SPI1_ISP */
+ fimc_is_set_parent_dt(pdev, "mout_sclk_isp_spi1", "mout_bus_pll_user");
+ fimc_is_set_rate_dt(pdev, "dout_sclk_isp_spi1_a", 275 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_sclk_isp_spi1_b", 46 * 1000000);
+ fimc_is_set_parent_dt(pdev, "mout_sclk_isp_spi1_user", "sclk_isp_spi1_top");
+#endif
+
+ /* I2C */
+ /* CMU TOP */
+ fimc_is_set_rate_dt(pdev, "dout_aclk_cam1_333", 333 * 1000000);
+
+ /* USER_MUX_SEL */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam1_333_user", "aclk_cam1_333");
+ /* MPWM */
+ fimc_is_set_rate_dt(pdev, "dout_pclk_cam1_166", 167 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_cam1_83", 84 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_sclk_isp_mpwm", 84 * 1000000);
+
+ return ret;
+}
+
+int exynos5430_fimc_is_companion_iclk_on(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+ /* SCLK clock enable */
+ fimc_is_enable_dt(pdev, "gate_isp_spi0");
+
+ return 0;
+}
+
+int exynos5430_fimc_is_companion_iclk_off(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+ exynos5430_fimc_is_companion_iclk_div_max(pdev);
+
+ /* SCLK clock disable */
+ fimc_is_disable_dt(pdev, "gate_isp_spi0");
+
+ return 0;
+}
+
+int exynos5430_fimc_is_companion_mclk_on(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+ u32 frequency;
+ char mux_name[30];
+ char div_a_name[30];
+ char div_b_name[30];
+ char sclk_name[30];
+
+ pr_debug("%s\n", __func__);
+
+ snprintf(mux_name, sizeof(mux_name), "mout_sclk_isp_sensor%d", channel);
+ snprintf(div_a_name, sizeof(div_a_name), "dout_sclk_isp_sensor%d_a", channel);
+ snprintf(div_b_name, sizeof(div_b_name), "dout_sclk_isp_sensor%d_b", channel);
+ snprintf(sclk_name, sizeof(sclk_name), "sclk_isp_sensor%d", channel);
+
+ fimc_is_set_parent_dt(pdev, mux_name, "oscclk");
+ fimc_is_set_rate_dt(pdev, div_a_name, 24 * 1000000);
+ fimc_is_set_rate_dt(pdev, div_b_name, 24 * 1000000);
+ frequency = fimc_is_get_rate_dt(pdev, sclk_name);
+
+ pr_info("%s(%d, mclk : %d)\n", __func__, channel, frequency);
+
+ return 0;
+}
+
+int exynos5430_fimc_is_companion_mclk_off(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+ pr_debug("%s\n", __func__);
+
+ return 0;
+}
+#endif
+
+/* Wrapper functions */
+int exynos_fimc_is_companion_iclk_cfg(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+#if defined(CONFIG_SOC_EXYNOS5422)
+ exynos5422_fimc_is_companion_iclk_cfg(pdev, scenario, channel);
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+ exynos5430_fimc_is_companion_iclk_cfg(pdev, scenario, channel);
+#endif
+ return 0;
+}
+
+int exynos_fimc_is_companion_iclk_on(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+#if defined(CONFIG_SOC_EXYNOS5422)
+ exynos5422_fimc_is_companion_iclk_on(pdev, scenario, channel);
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+ exynos5430_fimc_is_companion_iclk_on(pdev, scenario, channel);
+#endif
+ return 0;
+}
+
+int exynos_fimc_is_companion_iclk_off(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+#if defined(CONFIG_SOC_EXYNOS5422)
+ exynos5422_fimc_is_companion_iclk_off(pdev, scenario, channel);
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+ exynos5430_fimc_is_companion_iclk_off(pdev, scenario, channel);
+#endif
+ return 0;
+}
+
+int exynos_fimc_is_companion_mclk_on(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+#if defined(CONFIG_SOC_EXYNOS5422)
+ exynos5422_fimc_is_companion_mclk_on(pdev, scenario, channel);
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+ exynos5430_fimc_is_companion_mclk_on(pdev, scenario, channel);
+#endif
+ return 0;
+}
+
+int exynos_fimc_is_companion_mclk_off(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+#if defined(CONFIG_SOC_EXYNOS5422)
+ exynos5422_fimc_is_companion_mclk_off(pdev, scenario, channel);
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+ exynos5430_fimc_is_companion_mclk_off(pdev, scenario, channel);
+#endif
+ return 0;
+}
--- /dev/null
+/* linux/arch/arm/mach-exynos/setup-fimc-sensor.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * FIMC-IS gpio and clock configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/regulator/consumer.h>
+#include <linux/delay.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <mach/regs-gpio.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <plat/gpio-cfg.h>
+#include <plat/map-s5p.h>
+#include <plat/cpu.h>
+#ifdef CONFIG_OF
+#include <linux/of_gpio.h>
+#endif
+#if defined(CONFIG_SOC_EXYNOS5422)
+#include <mach/regs-clock-exynos5422.h>
+#elif defined(CONFIG_SOC_EXYNOS5430)
+#include <mach/regs-clock-exynos5430.h>
+#elif defined(CONFIG_SOC_EXYNOS5433)
+#include <mach/regs-clock-exynos5433.h>
+#endif
+
+#include "exynos-fimc-is.h"
+#include "exynos-fimc-is-sensor.h"
+
+static int exynos_fimc_is_sensor_pin_control(struct platform_device *pdev,
+ struct pinctrl *pinctrl, struct exynos_sensor_pin *pin_ctrls, int channel)
+{
+ int ret = 0;
+ char ch_name[30];
+
+ int pin = pin_ctrls->pin;
+ int delay = pin_ctrls->delay;
+ char* name = pin_ctrls->name;
+ enum pin_act act = pin_ctrls->act;
+ int voltage = pin_ctrls->voltage;
+ struct pinctrl_state *s;
+
+ snprintf(ch_name, sizeof(ch_name), "%s%d", name, channel);
+ pr_info("%s(pin(%d), act(%d), ch(%s), delay(%d), voltage(%d))\n", __func__, pin, act, ch_name, delay, voltage);
+
+ switch (act) {
+ case PIN_PULL_NONE:
+ break;
+ case PIN_OUTPUT_HIGH:
+ if (gpio_is_valid(pin)) {
+ gpio_request_one(pin, GPIOF_OUT_INIT_HIGH, "CAM_GPIO_OUTPUT_HIGH");
+ usleep_range(delay, delay);
+ gpio_free(pin);
+ }
+ break;
+ case PIN_OUTPUT_LOW:
+ if (gpio_is_valid(pin)) {
+ gpio_request_one(pin, GPIOF_OUT_INIT_LOW, "CAM_GPIO_OUTPUT_LOW");
+ usleep_range(delay, delay);
+ gpio_free(pin);
+ }
+ break;
+ case PIN_INPUT:
+ if (gpio_is_valid(pin)) {
+ gpio_request_one(pin, GPIOF_IN, "CAM_GPIO_INPUT");
+ gpio_free(pin);
+ }
+ break;
+ case PIN_RESET:
+ if (gpio_is_valid(pin)) {
+ gpio_request_one(pin, GPIOF_OUT_INIT_HIGH, "CAM_GPIO_RESET");
+ usleep_range(1000, 1000);
+ __gpio_set_value(pin, 0);
+ usleep_range(1000, 1000);
+ __gpio_set_value(pin, 1);
+ usleep_range(1000, 1000);
+ gpio_free(pin);
+ }
+ break;
+ case PIN_FUNCTION:
+ s = (struct pinctrl_state *)pin_ctrls->pin;
+ ret = pinctrl_select_state(pinctrl, s);
+ if (ret < 0) {
+ pr_err("%s: cam %s, state %p pinctrl_select_statee is failed\n", __func__, ch_name, s);
+ return ret;
+ }
+
+ usleep_range(1000, 1000);
+ break;
+ case PIN_REGULATOR_ON:
+ {
+ struct regulator *regulator = NULL;
+
+ regulator = regulator_get(&pdev->dev, name);
+ if (IS_ERR_OR_NULL(regulator)) {
+ pr_err("%s : regulator_get(%s) fail\n", __func__, name);
+ return PTR_ERR(regulator);
+ }
+
+ if(voltage > 0) {
+ pr_info("%s : regulator_set_voltage(%d)\n",__func__, voltage);
+ ret = regulator_set_voltage(regulator, voltage, voltage);
+ if(ret) {
+ pr_err("%s : regulator_set_voltage(%d) fail\n", __func__, ret);
+ }
+ }
+
+ if (regulator_is_enabled(regulator)) {
+ pr_warning("%s regulator is already enabled\n", name);
+ regulator_put(regulator);
+ return 0;
+ }
+
+ ret = regulator_enable(regulator);
+ if (ret) {
+ pr_err("%s : regulator_enable(%s) fail\n", __func__, name);
+ regulator_put(regulator);
+ return ret;
+ }
+ usleep_range(delay, delay);
+ regulator_put(regulator);
+ }
+ break;
+ case PIN_REGULATOR_OFF:
+ {
+ struct regulator *regulator = NULL;
+
+ regulator = regulator_get(&pdev->dev, name);
+ if (IS_ERR_OR_NULL(regulator)) {
+ pr_err("%s : regulator_get(%s) fail\n", __func__, name);
+ return PTR_ERR(regulator);
+ }
+
+ if (!regulator_is_enabled(regulator)) {
+ pr_warning("%s regulator is already disabled\n", name);
+ regulator_put(regulator);
+ return 0;
+ }
+
+ ret = regulator_disable(regulator);
+ if (ret) {
+ pr_err("%s : regulator_disable(%s) fail\n", __func__, name);
+ regulator_put(regulator);
+ return ret;
+ }
+ usleep_range(delay, delay);
+ regulator_put(regulator);
+ }
+ break;
+ default:
+ pr_err("unknown act for pin\n");
+ break;
+ }
+
+ return ret;
+}
+
+int exynos_fimc_is_sensor_pins_cfg(struct platform_device *pdev,
+ u32 scenario,
+ u32 enable)
+{
+ int ret = 0;
+ u32 i = 0;
+ struct exynos_sensor_pin (*pin_ctrls)[2][GPIO_CTRL_MAX];
+ struct exynos_platform_fimc_is_sensor *pdata;
+
+ BUG_ON(!pdev);
+ BUG_ON(!pdev->dev.platform_data);
+ BUG_ON(enable > 1);
+ BUG_ON(scenario > SENSOR_SCENARIO_MAX);
+
+ pdata = pdev->dev.platform_data;
+ pin_ctrls = pdata->pin_ctrls;
+
+ for (i = 0; i < GPIO_CTRL_MAX; ++i) {
+ if (pin_ctrls[scenario][enable][i].act == PIN_END) {
+ pr_info("gpio cfg is end(%d)\n", i);
+ break;
+ }
+
+ ret = exynos_fimc_is_sensor_pin_control(pdev,
+ pdata->pinctrl,
+ &pin_ctrls[scenario][enable][i],
+ pdata->csi_ch);
+ if (ret) {
+ pr_err("exynos5_fimc_is_sensor_gpio(%lu, %s, %d, %d) is fail(%d)",
+ pin_ctrls[scenario][enable][i].pin,
+ pin_ctrls[scenario][enable][i].name,
+ pin_ctrls[scenario][enable][i].act,
+ pdata->csi_ch,
+ ret);
+ goto p_err;
+ }
+ }
+
+p_err:
+ return ret;
+
+}
+
+#if defined(CONFIG_SOC_EXYNOS5422)
+int exynos5422_fimc_is_sensor_iclk_cfg(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+ int ret = 0;
+
+ pr_info("clk_cfg:(ch%d),scenario(%d)\n", channel, scenario);
+
+ switch (channel) {
+ case 0:
+ /* MIPI-CSIS0 */
+ fimc_is_set_parent_dt(pdev, "mout_gscl_wrap_a", "mout_mpll_ctrl");
+ fimc_is_set_rate_dt(pdev, "dout_gscl_wrap_a", (532 * 1000000));
+ fimc_is_get_rate_dt(pdev, "dout_gscl_wrap_a");
+ break;
+ case 1:
+ /* FL1_550_CAM */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_fl1_550_cam", "mout_mpll_ctrl");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_fl1_550_cam", (76 * 1000000));
+ fimc_is_set_parent_dt(pdev, "mout_aclk_fl1_550_cam_sw", "dout_aclk_fl1_550_cam");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_fl1_550_cam_user", "mout_aclk_fl1_550_cam_sw");
+ fimc_is_set_rate_dt(pdev, "dout2_cam_blk_550", (38 * 1000000));
+
+ /* MIPI-CSIS1 */
+ fimc_is_set_parent_dt(pdev, "mout_gscl_wrap_b", "mout_mpll_ctrl");
+ fimc_is_set_rate_dt(pdev, "dout_gscl_wrap_b", (76 * 1000000));
+ fimc_is_get_rate_dt(pdev, "dout_gscl_wrap_b");
+ break;
+ default:
+ pr_err("channel is invalid(%d)\n", channel);
+ break;
+ }
+
+ return ret;
+}
+
+int exynos5422_fimc_is_sensor_iclk_on(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+ return 0;
+}
+
+int exynos5422_fimc_is_sensor_iclk_off(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+ return 0;
+}
+
+int exynos5422_fimc_is_sensor_mclk_on(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+ u32 frequency;
+ char div_name[30];
+ char sclk_name[30];
+
+ pr_info("%s:ch(%d)\n", __func__, channel);
+
+ snprintf(div_name, sizeof(div_name), "dout_isp_sensor%d", channel);
+ snprintf(sclk_name, sizeof(sclk_name), "sclk_isp_sensor%d", channel);
+
+ fimc_is_set_parent_dt(pdev, "mout_isp_sensor", "fin_pll");
+ fimc_is_set_rate_dt(pdev, div_name, (24 * 1000000));
+ fimc_is_enable_dt(pdev, sclk_name);
+ frequency = fimc_is_get_rate_dt(pdev, div_name);
+
+ switch (channel) {
+ case SENSOR_CONTROL_I2C0:
+ fimc_is_enable_dt(pdev, "sclk_gscl_wrap_a");
+ fimc_is_enable_dt(pdev, "clk_camif_top_fimcl0");
+ fimc_is_enable_dt(pdev, "clk_camif_top_fimcl3");
+ fimc_is_enable_dt(pdev, "gscl_fimc_lite0");
+ fimc_is_enable_dt(pdev, "gscl_fimc_lite3");
+ fimc_is_enable_dt(pdev, "clk_gscl_wrap_a");
+ break;
+ case SENSOR_CONTROL_I2C1:
+ case SENSOR_CONTROL_I2C2:
+ fimc_is_enable_dt(pdev, "sclk_gscl_wrap_b");
+ fimc_is_enable_dt(pdev, "clk_camif_top_fimcl1");
+ fimc_is_enable_dt(pdev, "gscl_fimc_lite1");
+ fimc_is_enable_dt(pdev, "clk_gscl_wrap_b");
+ break;
+ default:
+ pr_err("channel is invalid(%d)\n", channel);
+ break;
+ }
+
+ fimc_is_enable_dt(pdev, "clk_camif_top_csis0");
+ fimc_is_enable_dt(pdev, "clk_xiu_si_gscl_cam");
+ fimc_is_enable_dt(pdev, "clk_noc_p_rstop_fimcl");
+
+ pr_info("%s(%d, mclk : %d)\n", __func__, channel, frequency);
+
+ return 0;
+}
+
+int exynos5422_fimc_is_sensor_mclk_off(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+ char sclk_name[30];
+
+ pr_debug("%s\n", __func__);
+
+ snprintf(sclk_name, sizeof(sclk_name), "sclk_isp_sensor%d", channel);
+
+ fimc_is_disable_dt(pdev, sclk_name);
+
+ switch (channel) {
+ case SENSOR_CONTROL_I2C0:
+ fimc_is_disable_dt(pdev, "sclk_gscl_wrap_a");
+ fimc_is_disable_dt(pdev, "clk_camif_top_fimcl0");
+ fimc_is_disable_dt(pdev, "clk_camif_top_fimcl3");
+ fimc_is_disable_dt(pdev, "gscl_fimc_lite0");
+ fimc_is_disable_dt(pdev, "gscl_fimc_lite3");
+ fimc_is_disable_dt(pdev, "clk_gscl_wrap_a");
+ break;
+ case SENSOR_CONTROL_I2C2:
+ fimc_is_disable_dt(pdev, "sclk_gscl_wrap_b");
+ fimc_is_disable_dt(pdev, "clk_camif_top_fimcl1");
+ fimc_is_disable_dt(pdev, "gscl_fimc_lite1");
+ fimc_is_disable_dt(pdev, "clk_gscl_wrap_b");
+ break;
+ default:
+ pr_err("channel is invalid(%d)\n", channel);
+ break;
+ }
+
+ return 0;
+}
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+int exynos5430_fimc_is_sensor_iclk_cfg(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+ int ret = 0;
+
+ if (scenario != SENSOR_SCENARIO_VISION)
+ return ret;
+
+ pr_info("clk_cfg(ch%d)\n", channel);
+
+ switch (channel) {
+ case 0:
+ /* USER_MUX_SEL */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam0_552_user", "oscclk");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam0_400_user", "oscclk");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam0_333_user", "oscclk");
+
+ /* MIPI-CSIS PHY */
+ fimc_is_set_parent_dt(pdev, "mout_phyclk_rxbyteclkhs0_s4", "oscclk");
+
+ /* MIPI-CSIS0 */
+ fimc_is_set_rate_dt(pdev, "dout_aclk_csis0", 1);
+
+ /* FIMC-LITE0 */
+ fimc_is_set_rate_dt(pdev, "dout_aclk_lite_a", 1);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_lite_a", 1);
+
+ /* FIMC-LITE3 */
+ fimc_is_set_rate_dt(pdev, "dout_aclk_lite_d", 1);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_lite_d", 1);
+
+ /* ASYNC, FLITE, 3AA, SMMU, QE ... */
+ fimc_is_set_rate_dt(pdev, "dout_aclk_cam0_400", 1);
+ fimc_is_set_rate_dt(pdev, "dout_aclk_cam0_200", 1);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_cam0_50", 1);
+
+ /* USER_MUX_SEL */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam0_552_user", "aclk_cam0_552");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam0_400_user", "aclk_cam0_400");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam0_333_user", "aclk_cam0_333");
+
+ /* MIPI-CSIS PHY */
+ fimc_is_set_parent_dt(pdev, "mout_phyclk_rxbyteclkhs0_s4", "phyclk_rxbyteclkhs0_s4");
+
+ /* MIPI-CSIS0 */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_csis0_a", "mout_aclk_cam0_552_user");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_csis0_b", "mout_aclk_csis0_a");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_csis0", 552 * 1000000);
+
+ /* FIMC-LITE0 */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_lite_a_a", "mout_aclk_cam0_552_user");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_lite_a_b", "mout_aclk_lite_a_a");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_lite_a", 552 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_lite_a", 276 * 1000000);
+
+ /* FIMC-LITE3 */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_lite_d_a", "mout_aclk_cam0_552_user");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_lite_d_b", "mout_aclk_lite_d_a");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_lite_d", 552 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_lite_d", 276 * 1000000);
+
+ /* ASYNC, FLITE, 3AA, SMMU, QE ... */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam0_400", "mout_aclk_cam0_400_user");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_cam0_400", 400 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_aclk_cam0_200", 200 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_cam0_50", 50 * 1000000);
+
+ /* FIMC-LITE2 PIXELASYNC */
+ fimc_is_set_rate_dt(pdev, "dout_sclk_pixelasync_lite_c_init", 1);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_pixelasync_lite_c", 1);
+ fimc_is_set_rate_dt(pdev, "dout_sclk_pixelasync_lite_c", 1);
+
+ /* FIMC-LITE2 PIXELASYNC */
+ fimc_is_set_parent_dt(pdev, "mout_sclk_pixelasync_lite_c_init_a", "mout_aclk_cam0_552_user");
+ fimc_is_set_parent_dt(pdev, "mout_sclk_pixelasync_lite_c_init_b", "mout_sclk_pixelasync_lite_c_init_a");
+ fimc_is_set_rate_dt(pdev, "dout_sclk_pixelasync_lite_c_init", 552 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_pixelasync_lite_c", 276 * 1000000);
+
+ fimc_is_set_parent_dt(pdev, "mout_sclk_pixelasync_lite_c_a", "mout_aclk_cam0_552_user");
+ fimc_is_set_parent_dt(pdev, "mout_sclk_pixelasync_lite_c_b", "mout_aclk_cam0_333_user");
+ fimc_is_set_rate_dt(pdev, "dout_sclk_pixelasync_lite_c", 333 * 1000000);
+
+ break;
+ case 1:
+ /* USER_MUX_SEL */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam0_552_user", "oscclk");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam0_400_user", "oscclk");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam0_333_user", "oscclk");
+
+ /* MIPI-CSIS PHY */
+ fimc_is_set_parent_dt(pdev, "mout_phyclk_rxbyteclkhs0_s2a", "oscclk");
+
+ /* MIPI-CSIS1 */
+ fimc_is_set_rate_dt(pdev, "dout_aclk_csis1", 1);
+
+ /* FIMC-LITE1 */
+ fimc_is_set_rate_dt(pdev, "dout_aclk_lite_b", 1);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_lite_b", 1);
+
+ /* USER_MUX_SEL */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam0_552_user", "aclk_cam0_552");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam0_400_user", "aclk_cam0_400");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam0_333_user", "aclk_cam0_333");
+
+ /* MIPI-CSIS PHY */
+ fimc_is_set_parent_dt(pdev, "mout_phyclk_rxbyteclkhs0_s2a", "phyclk_rxbyteclkhs0_s2a");
+
+ /* MIPI-CSIS1 */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_csis1_a", "mout_aclk_cam0_400_user");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_csis1_b", "mout_aclk_csis1_a");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_csis1", 552 * 1000000);
+
+ /* FIMC-LITE1 */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_lite_b_a", "mout_aclk_cam0_400_user");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_lite_b_b", "mout_aclk_lite_b_a");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_lite_b", 552 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_lite_b", 276 * 1000000);
+ break;
+ case 2:
+ /* USER_MUX_SEL */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam1_552_user", "oscclk");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam1_400_user", "oscclk");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam1_333_user", "oscclk");
+
+ /* MIPI-CSIS PHY */
+ fimc_is_set_parent_dt(pdev, "mout_phyclk_rxbyteclkhs0_s2b", "oscclk");
+
+ /* MIPI-CSIS2 */
+ fimc_is_set_rate_dt(pdev, "dout_aclk_csis2_a", 1);
+
+ /* FIMC-LITE2 */
+ fimc_is_set_rate_dt(pdev, "dout_aclk_lite_c", 1);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_lite_c", 1);
+
+ /* USER_MUX_SEL */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam1_552_user", "aclk_cam1_552");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam1_400_user", "aclk_cam1_400");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam1_333_user", "aclk_cam1_333");
+
+ /* MIPI-CSIS PHY */
+ fimc_is_set_parent_dt(pdev, "mout_phyclk_rxbyteclkhs0_s2b", "phyclk_rxbyteclkhs0_s2b");
+
+ /* MIPI-CSIS2 */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_csis2_a", "mout_aclk_cam1_400_user");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_csis2_b", "mout_aclk_cam1_333_user");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_csis2_a", 333 * 1000000);
+ break;
+ default:
+ pr_err("channel is invalid(%d)\n", channel);
+ break;
+ }
+
+ return ret;
+}
+
+int exynos5430_fimc_is_sensor_iclk_on(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+ switch (channel) {
+ case 0:
+ fimc_is_enable_dt(pdev, "aclk_csis0");
+ fimc_is_enable_dt(pdev, "pclk_csis0");
+ fimc_is_enable_dt(pdev, "gate_lite_a");
+ fimc_is_enable_dt(pdev, "gate_lite_d");
+ break;
+ case 1:
+ fimc_is_enable_dt(pdev, "aclk_csis1");
+ fimc_is_enable_dt(pdev, "pclk_csis1");
+ fimc_is_enable_dt(pdev, "gate_lite_b");
+ break;
+ case 2:
+ fimc_is_enable_dt(pdev, "gate_csis2");
+ fimc_is_enable_dt(pdev, "gate_lite_c");
+ break;
+ default:
+ pr_err("channel is invalid(%d)\n", channel);
+ break;
+ }
+
+ return 0;
+}
+
+int exynos5430_fimc_is_sensor_iclk_off(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+ switch (channel) {
+ case 0:
+ fimc_is_disable_dt(pdev, "aclk_csis0");
+ fimc_is_disable_dt(pdev, "pclk_csis0");
+ fimc_is_disable_dt(pdev, "gate_lite_a");
+ fimc_is_disable_dt(pdev, "gate_lite_d");
+ break;
+ case 1:
+ fimc_is_disable_dt(pdev, "aclk_csis1");
+ fimc_is_disable_dt(pdev, "pclk_csis1");
+ fimc_is_disable_dt(pdev, "gate_lite_b");
+ break;
+ case 2:
+ fimc_is_disable_dt(pdev, "gate_csis2");
+ fimc_is_disable_dt(pdev, "gate_lite_c");
+ break;
+ default:
+ pr_err("channel is invalid(%d)\n", channel);
+ break;
+ }
+
+ return 0;
+}
+
+int exynos5430_fimc_is_sensor_mclk_on(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+ u32 frequency;
+ char mux_name[30];
+ char div_a_name[30];
+ char div_b_name[30];
+ char sclk_name[30];
+
+ pr_debug("%s\n", __func__);
+
+ snprintf(mux_name, sizeof(mux_name), "mout_sclk_isp_sensor%d", channel);
+ snprintf(div_a_name, sizeof(div_a_name), "dout_sclk_isp_sensor%d_a", channel);
+ snprintf(div_b_name, sizeof(div_b_name), "dout_sclk_isp_sensor%d_b", channel);
+ snprintf(sclk_name, sizeof(sclk_name), "sclk_isp_sensor%d", channel);
+
+ fimc_is_set_parent_dt(pdev, mux_name, "oscclk");
+ fimc_is_set_rate_dt(pdev, div_a_name, 24 * 1000000);
+ fimc_is_set_rate_dt(pdev, div_b_name, 24 * 1000000);
+ frequency = fimc_is_get_rate_dt(pdev, sclk_name);
+
+ pr_info("%s(%d, mclk : %d)\n", __func__, channel, frequency);
+
+ return 0;
+}
+
+int exynos5430_fimc_is_sensor_mclk_off(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+ char mux_name[30];
+ char div_a_name[30];
+ char div_b_name[30];
+ char sclk_name[30];
+
+ pr_debug("%s\n", __func__);
+
+ snprintf(mux_name, sizeof(mux_name), "mout_sclk_isp_sensor%d", channel);
+ snprintf(div_a_name, sizeof(div_a_name), "dout_sclk_isp_sensor%d_a", channel);
+ snprintf(div_b_name, sizeof(div_b_name), "dout_sclk_isp_sensor%d_b", channel);
+ snprintf(sclk_name, sizeof(sclk_name), "sclk_isp_sensor%d", channel);
+
+ fimc_is_set_parent_dt(pdev, mux_name, "oscclk");
+ fimc_is_set_rate_dt(pdev, div_a_name, 24 * 1000000);
+ fimc_is_set_rate_dt(pdev, div_b_name, 24 * 1000000);
+ fimc_is_get_rate_dt(pdev, sclk_name);
+
+ return 0;
+}
+#endif
+
+/* Wrapper functions */
+int exynos_fimc_is_sensor_iclk_cfg(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+#if defined(CONFIG_SOC_EXYNOS5422)
+ exynos5422_fimc_is_sensor_iclk_cfg(pdev, scenario, channel);
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+ exynos5430_fimc_is_sensor_iclk_cfg(pdev, scenario, channel);
+#endif
+ return 0;
+}
+
+int exynos_fimc_is_sensor_iclk_on(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+#if defined(CONFIG_SOC_EXYNOS5422)
+ exynos5422_fimc_is_sensor_iclk_on(pdev, scenario, channel);
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+ exynos5430_fimc_is_sensor_iclk_on(pdev, scenario, channel);
+#endif
+ return 0;
+}
+
+int exynos_fimc_is_sensor_iclk_off(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+#if defined(CONFIG_SOC_EXYNOS5422)
+ exynos5422_fimc_is_sensor_iclk_off(pdev, scenario, channel);
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+ exynos5430_fimc_is_sensor_iclk_off(pdev, scenario, channel);
+#endif
+ return 0;
+}
+
+int exynos_fimc_is_sensor_mclk_on(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+#if defined(CONFIG_SOC_EXYNOS5422)
+ exynos5422_fimc_is_sensor_mclk_on(pdev, scenario, channel);
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+ exynos5430_fimc_is_sensor_mclk_on(pdev, scenario, channel);
+#endif
+ return 0;
+}
+
+int exynos_fimc_is_sensor_mclk_off(struct platform_device *pdev,
+ u32 scenario,
+ u32 channel)
+{
+#if defined(CONFIG_SOC_EXYNOS5422)
+ exynos5422_fimc_is_sensor_mclk_off(pdev, scenario, channel);
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+ exynos5430_fimc_is_sensor_mclk_off(pdev, scenario, channel);
+#endif
+ return 0;
+}
--- /dev/null
+/* linux/arch/arm/mach-exynos/setup-fimc-is.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * FIMC-IS gpio and clock configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/regulator/consumer.h>
+#include <linux/delay.h>
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <mach/regs-gpio.h>
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <plat/gpio-cfg.h>
+#include <plat/map-s5p.h>
+#include <plat/cpu.h>
+#include "exynos-fimc-is.h"
+#ifdef CONFIG_OF
+#include <linux/of_gpio.h>
+#endif
+#if defined(CONFIG_SOC_EXYNOS5422)
+#include <mach/regs-clock-exynos5422.h>
+#elif defined(CONFIG_SOC_EXYNOS5430)
+#include <mach/regs-clock-exynos5430.h>
+#elif defined(CONFIG_SOC_EXYNOS5433)
+#include <mach/regs-clock-exynos5433.h>
+#endif
+
+struct platform_device; /* don't need the contents */
+
+/*------------------------------------------------------*/
+/* Common control */
+/*------------------------------------------------------*/
+int exynos_fimc_is_print_cfg(struct platform_device *pdev, u32 channel)
+{
+ pr_debug("%s\n", __func__);
+
+ return 0;
+}
+
+/* utility function to set parent with DT */
+int fimc_is_set_parent_dt(struct platform_device *pdev,
+ const char *child, const char *parent)
+{
+ struct clk *p;
+ struct clk *c;
+
+ p = clk_get(&pdev->dev, parent);
+ if (IS_ERR(p)) {
+ pr_err("%s: could not lookup clock : %s\n", __func__, parent);
+ return -EINVAL;
+ }
+
+ c = clk_get(&pdev->dev, child);
+ if (IS_ERR(c)) {
+ pr_err("%s: could not lookup clock : %s\n", __func__, child);
+ return -EINVAL;
+ }
+
+ return clk_set_parent(c, p);
+}
+
+/* utility function to get parent with DT */
+struct clk *fimc_is_get_parent_dt(struct platform_device *pdev,
+ const char *child)
+{
+ struct clk *c;
+
+ c = clk_get(&pdev->dev, child);
+ if (IS_ERR(c)) {
+ pr_err("%s: could not lookup clock : %s\n", __func__, child);
+ return NULL;
+ }
+
+ return clk_get_parent(c);
+}
+
+/* utility function to set rate with DT */
+int fimc_is_set_rate_dt(struct platform_device *pdev,
+ const char *conid, unsigned int rate)
+{
+ struct clk *target;
+
+ target = clk_get(&pdev->dev, conid);
+ if (IS_ERR(target)) {
+ pr_err("%s: could not lookup clock : %s\n", __func__, conid);
+ return -EINVAL;
+ }
+
+ return clk_set_rate(target, rate);
+}
+
+/* utility function to get rate with DT */
+unsigned int fimc_is_get_rate_dt(struct platform_device *pdev,
+ const char *conid)
+{
+ struct clk *target;
+ unsigned int rate_target;
+
+ target = clk_get(&pdev->dev, conid);
+ if (IS_ERR(target)) {
+ pr_err("%s: could not lookup clock : %s\n", __func__, conid);
+ return -EINVAL;
+ }
+
+ rate_target = clk_get_rate(target);
+ pr_info("%s : %d\n", conid, rate_target);
+
+ return rate_target;
+}
+
+/* utility function to eable with DT */
+unsigned int fimc_is_enable_dt(struct platform_device *pdev,
+ const char *conid)
+{
+ struct clk *target;
+
+ target = clk_get(&pdev->dev, conid);
+ if (IS_ERR(target)) {
+ pr_err("%s: could not lookup clock : %s\n", __func__, conid);
+ return -EINVAL;
+ }
+
+ clk_prepare(target);
+
+ return clk_enable(target);
+}
+
+/* utility function to disable with DT */
+void fimc_is_disable_dt(struct platform_device *pdev,
+ const char *conid)
+{
+ struct clk *target;
+
+ target = clk_get(&pdev->dev, conid);
+ if (IS_ERR(target)) {
+ pr_err("%s: could not lookup clock : %s\n", __func__, conid);
+ }
+
+ clk_disable(target);
+ clk_unprepare(target);
+}
+
+#if defined(CONFIG_SOC_EXYNOS5422)
+int exynos5422_fimc_is_clk_gate(u32 clk_gate_id, bool is_on)
+{
+ int cfg = 0;
+ u32 value = 0;
+
+ if (clk_gate_id == 0)
+ return 0;
+
+ /* CAM block */
+ /* 3AA 0*/
+ if (clk_gate_id & (1 << FIMC_IS_GATE_3AA0_IP)) {
+ value |= ((1 << 31) | (1 << 27));
+ cfg = readl(EXYNOS5_CLK_GATE_IP_CAM);
+ if (is_on)
+ writel(cfg | value, EXYNOS5_CLK_GATE_IP_CAM);
+ else
+ writel(cfg & ~(value), EXYNOS5_CLK_GATE_IP_CAM);
+ pr_debug("%s :1 [%s] gate(%d) (0x%x) * (0x%x)\n", __func__,
+ is_on ? "ON" : "OFF",
+ clk_gate_id,
+ cfg,
+ value);
+ }
+
+ /* 3AA 1*/
+ value = 0;
+ if (clk_gate_id & (1 << FIMC_IS_GATE_3AA1_IP)) {
+ value |= ((1 << 9) | (1 << 4));
+ cfg = readl(EXYNOS5_CLK_GATE_IP_GSCL0);
+ if (is_on)
+ writel(cfg | value, EXYNOS5_CLK_GATE_IP_GSCL0);
+ else
+ writel(cfg & ~(value), EXYNOS5_CLK_GATE_IP_GSCL0);
+ pr_debug("%s :1 [%s] gate(%d) (0x%x) * (0x%x)\n", __func__,
+ is_on ? "ON" : "OFF",
+ clk_gate_id,
+ cfg,
+ value);
+ }
+
+ /* ISP block */
+ value = 0;
+ if (clk_gate_id & (1 << FIMC_IS_GATE_ISP_IP))
+ value |= (1 << 0);
+ if (clk_gate_id & (1 << FIMC_IS_GATE_DRC_IP))
+ value |= (1 << 1);
+ if (clk_gate_id & (1 << FIMC_IS_GATE_FD_IP))
+ value |= (1 << 2);
+ if (clk_gate_id & (1 << FIMC_IS_GATE_SCC_IP))
+ value |= (1 << 3);
+ if (clk_gate_id & (1 << FIMC_IS_GATE_SCP_IP))
+ value |= (1 << 4);
+ if (value > 0) {
+ cfg = readl(EXYNOS5_CLK_GATE_IP_ISP0);
+ if (is_on)
+ writel(cfg | value, EXYNOS5_CLK_GATE_IP_ISP0);
+ else
+ writel(cfg & ~(value), EXYNOS5_CLK_GATE_IP_ISP0);
+ pr_debug("%s :1 [%s] gate(%d) (0x%x) * (0x%x)\n", __func__,
+ is_on ? "ON" : "OFF",
+ clk_gate_id,
+ cfg,
+ value);
+ }
+
+ value = 0;
+ if (clk_gate_id & (1 << FIMC_IS_GATE_3DNR_IP))
+ value |= (1 << 2);
+ if (value > 0) {
+ cfg = readl(EXYNOS5_CLK_GATE_IP_ISP1);
+ if (is_on)
+ writel(cfg | value, EXYNOS5_CLK_GATE_IP_ISP1);
+ else
+ writel(cfg & ~(value), EXYNOS5_CLK_GATE_IP_ISP1);
+ pr_debug("%s :1 [%s] gate(%d) (0x%x) * (0x%x)\n", __func__,
+ is_on ? "ON" : "OFF",
+ clk_gate_id,
+ cfg,
+ value);
+ }
+
+/*
+ pr_info("%s : [%s] gate(%d) (0x%x)\n", __func__,
+ is_on ? "ON" : "OFF",
+ clk_gate_id,
+ cfg);
+*/
+ return 0;
+}
+
+int exynos5422_cfg_clk_div_max(struct platform_device *pdev)
+{
+ pr_info("%s\n", __func__);
+ /* CMU TOP */
+ /* 333_432_ISP0 */
+ fimc_is_set_rate_dt(pdev, "dout_aclk_333_432_isp0", 1);
+ /* 333_432_ISP */
+ fimc_is_set_rate_dt(pdev, "dout_aclk_333_432_isp", 1);
+ /* 400_ISP */
+ fimc_is_set_rate_dt(pdev, "dout_aclk_400_isp", 1);
+ /* 266_ISP */
+ fimc_is_set_rate_dt(pdev, "dout_aclk_266_isp", 1);
+
+ /* 333_432_GSCL */
+ fimc_is_set_rate_dt(pdev, "dout_aclk_333_432_gscl", 1);
+ /* 432_CAM */
+ fimc_is_set_rate_dt(pdev, "dout_aclk_432_cam", 1);
+ /* FL1_550_CAM */
+ fimc_is_set_rate_dt(pdev, "dout_aclk_fl1_550_cam", 1);
+ /* 550_CAM */
+ fimc_is_set_rate_dt(pdev, "dout_aclk_550_cam", 1);
+
+ return 0;
+}
+
+int exynos5422_cfg_clk_sclk(struct platform_device *pdev)
+{
+ pr_info("%s\n", __func__);
+#ifndef CONFIG_COMPANION_USE
+ /* SCLK_SPI0_ISP */
+ fimc_is_set_parent_dt(pdev, "mout_spi0_isp", "mout_spll_ctrl");
+ fimc_is_set_rate_dt(pdev, "dout_spi0_isp", 200 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_spi0_isp_pre", 100 * 1000000);
+ /* SCLK_SPI1_ISP */
+ fimc_is_set_parent_dt(pdev, "mout_spi1_isp", "mout_spll_ctrl");
+ fimc_is_set_rate_dt(pdev, "dout_spi1_isp", 200 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_spi1_isp_pre", 100 * 1000000);
+#endif
+ /* SCLK_UART_ISP */
+ fimc_is_set_parent_dt(pdev, "mout_uart_isp", "fin_pll");
+ fimc_is_set_rate_dt(pdev, "dout_uart_isp", (24* 1000000));
+ /* SCLK_PWM_ISP */
+ fimc_is_set_parent_dt(pdev, "mout_pwm_isp", "fin_pll");
+ fimc_is_set_rate_dt(pdev, "dout_pwm_isp", (2 * 1000000));
+
+ return 0;
+}
+
+int exynos5422_cfg_clk_cam(struct platform_device *pdev)
+{
+ pr_info("%s\n", __func__);
+ /* CMU TOP */
+ /* 333_432_GSCL */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_333_432_gscl", "mout_ipll_ctrl");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_333_432_gscl", (432 * 1000000));
+ fimc_is_set_parent_dt(pdev, "mout_aclk_333_432_gscl_sw", "dout_aclk_333_432_gscl");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_333_432_gscl_user", "mout_aclk_333_432_gscl_sw");
+ /* 432_CAM */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_432_cam", "mout_ipll_ctrl");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_432_cam", (432 * 1000000));
+ fimc_is_set_parent_dt(pdev, "mout_aclk_432_cam_sw", "dout_aclk_432_cam");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_432_cam_user", "mout_aclk_432_cam_sw");
+ /* 550_CAM */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_550_cam", "mout_mpll_ctrl");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_550_cam", (532 * 1000000));
+ fimc_is_set_parent_dt(pdev, "mout_aclk_550_cam_sw", "dout_aclk_550_cam");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_550_cam_user", "mout_aclk_550_cam_sw");
+
+ /* CMU CAM */
+ /* CLKDIV2_GSCL_BLK_333 */
+ fimc_is_set_rate_dt(pdev, "dout2_gscl_blk_333", (217 * 1000000));
+ /* CLKDIV2_CAM_BLK_432 */
+ fimc_is_set_rate_dt(pdev, "dout2_cam_blk_432", (217 * 1000000));
+
+ return 0;
+}
+
+int exynos5422_cfg_clk_isp(struct platform_device *pdev)
+{
+
+ /* CMU TOP */
+ /* 333_432_ISP0 */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_333_432_isp0", "mout_ipll_ctrl");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_333_432_isp0", (432 * 1000000));
+ fimc_is_set_parent_dt(pdev, "mout_aclk_333_432_isp0_sw", "dout_aclk_333_432_isp0");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_333_432_isp0_user", "mout_aclk_333_432_isp0_sw");
+ /* 333_432_ISP */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_333_432_isp", "mout_ipll_ctrl");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_333_432_isp", (432 * 1000000));
+ fimc_is_set_parent_dt(pdev, "mout_aclk_333_432_isp_sw", "dout_aclk_333_432_isp");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_333_432_isp_user", "mout_aclk_333_432_isp_sw");
+ /* 400_ISP */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_400_isp", "mout_mpll_ctrl");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_400_isp", (532 * 1000000));
+ fimc_is_set_parent_dt(pdev, "mout_aclk_400_isp_sw", "dout_aclk_400_isp");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_400_isp_user", "mout_aclk_400_isp_sw");
+ /* 266_ISP */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_266_isp", "mout_ipll_ctrl");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_266_isp", (432 * 1000000));
+ fimc_is_set_parent_dt(pdev, "mout_aclk_266_isp_sw", "dout_aclk_266_isp");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_266_isp_user", "mout_aclk_266_isp_sw");
+
+ /* CMU ISP */
+ /* ACLK_MCUISP_DIV0 */
+ fimc_is_set_rate_dt(pdev, "dout_mcuispdiv0", (267 * 1000000));
+ /* ACLK_MCUISP_DIV1 */
+ fimc_is_set_rate_dt(pdev, "dout_mcuispdiv1", (134 * 1000000));
+ /* ACLK_DIV0 */
+ fimc_is_set_rate_dt(pdev, "dout_ispdiv0", (216 * 1000000));
+ /* ACLK_DIV1 */
+ fimc_is_set_rate_dt(pdev, "dout_ispdiv1", (108 * 1000000));
+ /* ACLK_DIV2 */
+ fimc_is_set_rate_dt(pdev, "dout_ispdiv2", (54 * 1000000));
+
+ return 0;
+}
+
+int exynos5422_fimc_is_print_clk(struct platform_device *pdev)
+{
+ pr_debug("%s\n", __func__);
+
+ fimc_is_get_rate_dt(pdev, "mout_aclk_550_cam_user");
+ fimc_is_get_rate_dt(pdev, "mout_aclk_fl1_550_cam_user");
+ fimc_is_get_rate_dt(pdev, "mout_aclk_432_cam_user");
+ fimc_is_get_rate_dt(pdev, "mout_aclk_333_432_gscl_user");
+ fimc_is_get_rate_dt(pdev, "mout_aclk_333_432_isp0_user");
+ fimc_is_get_rate_dt(pdev, "mout_aclk_333_432_isp_user");
+ fimc_is_get_rate_dt(pdev, "mout_aclk_400_isp_user");
+ fimc_is_get_rate_dt(pdev, "mout_aclk_266_isp_user");
+
+ fimc_is_get_rate_dt(pdev, "dout_mcuispdiv0");
+ fimc_is_get_rate_dt(pdev, "dout_mcuispdiv1");
+ fimc_is_get_rate_dt(pdev, "dout_ispdiv0");
+ fimc_is_get_rate_dt(pdev, "dout_ispdiv1");
+ fimc_is_get_rate_dt(pdev, "dout_ispdiv2");
+
+ fimc_is_get_rate_dt(pdev, "dout2_gscl_blk_333");
+ fimc_is_get_rate_dt(pdev, "dout2_cam_blk_432");
+ fimc_is_get_rate_dt(pdev, "dout2_cam_blk_550");
+
+ fimc_is_get_rate_dt(pdev, "dout_pwm_isp");
+ fimc_is_get_rate_dt(pdev, "dout_uart_isp");
+ fimc_is_get_rate_dt(pdev, "dout_spi0_isp_pre");
+ fimc_is_get_rate_dt(pdev, "dout_spi1_isp_pre");
+
+ /* CMU_TOP_DUMP */
+ pr_info("EXYNOS5_CLK_SRC_TOP0(0x%08X)\n", readl(EXYNOS5_CLK_SRC_TOP0));
+ pr_info("EXYNOS5_CLK_SRC_TOP1(0x%08X)\n", readl(EXYNOS5_CLK_SRC_TOP1));
+ pr_info("EXYNOS5_CLK_SRC_TOP3(0x%08X)\n", readl(EXYNOS5_CLK_SRC_TOP3));
+ pr_info("EXYNOS5_CLK_SRC_TOP4(0x%08X)\n", readl(EXYNOS5_CLK_SRC_TOP4));
+ pr_info("EXYNOS5_CLK_SRC_TOP8(0x%08X)\n", readl(EXYNOS5_CLK_SRC_TOP8));
+ pr_info("EXYNOS5_CLK_SRC_TOP9(0x%08X)\n", readl(EXYNOS5_CLK_SRC_TOP9));
+ pr_info("EXYNOS5_CLK_SRC_TOP11(0x%08X)\n", readl(EXYNOS5_CLK_SRC_TOP11));
+ pr_info("EXYNOS5_CLK_SRC_TOP13(0x%08X)\n", readl(EXYNOS5_CLK_SRC_TOP13));
+
+ pr_info("EXYNOS5_CLK_DIV_TOP0(0x%08X)\n", readl(EXYNOS5_CLK_DIV_TOP0));
+ pr_info("EXYNOS5_CLK_DIV_TOP1(0x%08X)\n", readl(EXYNOS5_CLK_DIV_TOP1));
+ pr_info("EXYNOS5_CLK_DIV_TOP8(0x%08X)\n", readl(EXYNOS5_CLK_DIV_TOP8));
+
+ return 0;
+}
+
+int exynos5422_fimc_is_cfg_clk(struct platform_device *pdev)
+{
+ pr_info("%s\n", __func__);
+
+ /* initialize Clocks */
+ exynos5422_cfg_clk_sclk(pdev);
+ exynos5422_cfg_clk_cam(pdev);
+ exynos5422_cfg_clk_isp(pdev);
+
+ return 0;
+}
+
+int exynos5422_fimc_is_clk_on(struct platform_device *pdev)
+{
+ pr_debug("%s\n", __func__);
+
+ fimc_is_enable_dt(pdev, "sclk_uart_isp");
+ fimc_is_enable_dt(pdev, "sclk_pwm_isp");
+ fimc_is_enable_dt(pdev, "sclk_spi0_isp");
+
+ fimc_is_enable_dt(pdev, "clk_3aa");
+ fimc_is_enable_dt(pdev, "clk_camif_top_3aa");
+ fimc_is_enable_dt(pdev, "clk_3aa_2");
+ fimc_is_enable_dt(pdev, "clk_camif_top_3aa0");
+
+ return 0;
+}
+
+int exynos5422_fimc_is_clk_off(struct platform_device *pdev)
+{
+ pr_debug("%s\n", __func__);
+
+ exynos5422_cfg_clk_div_max(pdev);
+ fimc_is_disable_dt(pdev, "sclk_uart_isp");
+ fimc_is_disable_dt(pdev, "sclk_pwm_isp");
+ fimc_is_disable_dt(pdev, "sclk_spi0_isp");
+
+ fimc_is_disable_dt(pdev, "clk_3aa");
+ fimc_is_disable_dt(pdev, "clk_camif_top_3aa");
+ fimc_is_disable_dt(pdev, "clk_3aa_2");
+ fimc_is_disable_dt(pdev, "clk_camif_top_3aa0");
+
+ return 0;
+}
+
+/* sequence is important, don't change order */
+int exynos5422_fimc_is_sensor_power_on(struct platform_device *pdev, int sensor_id)
+{
+ pr_debug("%s\n", __func__);
+
+ return 0;
+}
+
+/* sequence is important, don't change order */
+int exynos5422_fimc_is_sensor_power_off(struct platform_device *pdev, int sensor_id)
+{
+ pr_debug("%s\n", __func__);
+
+ return 0;
+}
+
+int exynos5422_fimc_is_print_pwr(struct platform_device *pdev)
+{
+ pr_debug("%s\n", __func__);
+
+ pr_info("ISP power state(0x%08x)\n", readl(EXYNOS5422_ISP_STATUS));
+ pr_info("CAM power state(0x%08x)\n", readl(EXYNOS5422_CAM_STATUS));
+ pr_info("CA5 power state(0x%08x)\n", readl(EXYNOS5422_ISP_ARM_STATUS));
+
+ return 0;
+}
+
+int exynos5422_fimc_is_set_user_clk_gate(u32 group_id,
+ bool is_on,
+ u32 user_scenario_id,
+ unsigned long msk_state,
+ struct exynos_fimc_is_clk_gate_info *gate_info) {
+ /* if you want to skip clock on/off, let this func return -1 */
+ int ret = -1;
+
+ switch (user_scenario_id) {
+ case CLK_GATE_FULL_BYPASS_SN:
+ if (is_on == true)
+ gate_info->groups[group_id].mask_clk_on_mod &=
+ ~((1 << FIMC_IS_GATE_DIS_IP) |
+ (1 << FIMC_IS_GATE_3DNR_IP));
+ else
+ gate_info->groups[group_id].mask_clk_off_self_mod |=
+ ((1 << FIMC_IS_GATE_DIS_IP) |
+ (1 << FIMC_IS_GATE_3DNR_IP));
+ ret = 0;
+ break;
+ case CLK_GATE_DIS_SN:
+ if (is_on == true)
+ gate_info->groups[group_id].mask_clk_on_mod |=
+ ((1 << FIMC_IS_GATE_DIS_IP) |
+ (1 << FIMC_IS_GATE_3DNR_IP));
+ else
+ gate_info->groups[group_id].mask_clk_off_self_mod |=
+ ((1 << FIMC_IS_GATE_DIS_IP) |
+ (1 << FIMC_IS_GATE_3DNR_IP));
+ ret = 0;
+ break;
+ default:
+ ret = 0;
+ break;
+ }
+
+ return ret;
+}
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+int exynos5430_fimc_is_clk_gate(u32 clk_gate_id, bool is_on)
+{
+ int cfg = 0;
+ u32 value = 0;
+
+ if (clk_gate_id == 0)
+ return 0;
+
+ /* CAM00 */
+ if (clk_gate_id & (1 << FIMC_IS_GATE_3AA1_IP))
+ value |= (1 << 4);
+ if (clk_gate_id & (1 << FIMC_IS_GATE_3AA0_IP))
+ value |= (1 << 3);
+
+ if (value > 0) {
+ cfg = readl(EXYNOS5430_ENABLE_IP_CAM00);
+ if (is_on)
+ writel(cfg | value, EXYNOS5430_ENABLE_IP_CAM00);
+ else
+ writel(cfg & ~(value), EXYNOS5430_ENABLE_IP_CAM00);
+ pr_debug("%s :1 [%s] gate(%d) (0x%x) * (0x%x)\n", __func__,
+ is_on ? "ON" : "OFF",
+ clk_gate_id,
+ cfg,
+ value);
+ }
+
+
+ /* ISP 0 */
+ value = 0;
+ if (clk_gate_id & (1 << FIMC_IS_GATE_ISP_IP))
+ value |= (1 << 0);
+ if (clk_gate_id & (1 << FIMC_IS_GATE_DRC_IP))
+ value |= (1 << 1);
+ if (clk_gate_id & (1 << FIMC_IS_GATE_SCC_IP))
+ value |= (1 << 2);
+ if (clk_gate_id & (1 << FIMC_IS_GATE_DIS_IP))
+ value |= (1 << 3);
+ if (clk_gate_id & (1 << FIMC_IS_GATE_3DNR_IP))
+ value |= (1 << 4);
+ if (clk_gate_id & (1 << FIMC_IS_GATE_SCP_IP))
+ value |= (1 << 5);
+
+ if (value > 0) {
+ cfg = readl(EXYNOS5430_ENABLE_IP_ISP0);
+ if (is_on)
+ writel(cfg | value, EXYNOS5430_ENABLE_IP_ISP0);
+ else
+ writel(cfg & ~(value), EXYNOS5430_ENABLE_IP_ISP0);
+ pr_debug("%s :2 [%s] gate(%d) (0x%x) * (0x%x)\n", __func__,
+ is_on ? "ON" : "OFF",
+ clk_gate_id,
+ cfg,
+ value);
+ }
+
+ /* CAM 10 */
+ value = 0;
+ if (clk_gate_id & (1 << FIMC_IS_GATE_FD_IP))
+ value |= (1 << 3);
+
+ if (value > 0) {
+ cfg = readl(EXYNOS5430_ENABLE_IP_CAM10);
+ if (is_on)
+ writel(cfg | value, EXYNOS5430_ENABLE_IP_CAM10);
+ else
+ writel(cfg & ~(value), EXYNOS5430_ENABLE_IP_CAM10);
+ pr_debug("%s :3 [%s] gate(%d) (0x%x) * (0x%x)\n", __func__,
+ is_on ? "ON" : "OFF",
+ clk_gate_id,
+ cfg,
+ value);
+ }
+/*
+ pr_info("%s : [%s] gate(%d) (0x%x)\n", __func__,
+ is_on ? "ON" : "OFF",
+ clk_gate_id,
+ cfg);
+*/
+ return 0;
+}
+
+static int exynos5430_cfg_clk_isp_pll_on(struct platform_device *pdev)
+{
+ pr_info("%s\n", __func__);
+
+ fimc_is_enable_dt(pdev, "fout_isp_pll");
+ fimc_is_set_parent_dt(pdev, "mout_isp_pll", "fout_isp_pll");
+
+ return 0;
+}
+
+static int exynos5430_cfg_clk_isp_pll_off(struct platform_device *pdev)
+{
+ pr_info("%s\n", __func__);
+
+ fimc_is_set_parent_dt(pdev, "mout_isp_pll", "fin_pll");
+ fimc_is_disable_dt(pdev, "fout_isp_pll");
+
+ return 0;
+}
+
+int exynos5430_cfg_clk_div_max(struct platform_device *pdev)
+{
+ /* SCLK */
+#ifndef CONFIG_COMPANION_USE
+ /* SCLK_SPI0 */
+ fimc_is_set_parent_dt(pdev, "mout_sclk_isp_spi0", "oscclk");
+ fimc_is_set_rate_dt(pdev, "dout_sclk_isp_spi0_a", 1);
+ fimc_is_set_parent_dt(pdev, "mout_sclk_isp_spi0_user", "oscclk");
+
+ /* SCLK_SPI1 */
+ fimc_is_set_parent_dt(pdev, "mout_sclk_isp_spi1", "oscclk");
+ fimc_is_set_rate_dt(pdev, "dout_sclk_isp_spi1_a", 1);
+ fimc_is_set_parent_dt(pdev, "mout_sclk_isp_spi1_user", "oscclk");
+#endif
+
+ /* SCLK_UART */
+ fimc_is_set_parent_dt(pdev, "mout_sclk_isp_uart", "oscclk");
+ fimc_is_set_rate_dt(pdev, "dout_sclk_isp_uart", 1);
+ fimc_is_set_parent_dt(pdev, "mout_sclk_isp_uart_user", "oscclk");
+
+ /* CAM1 */
+ /* C-A5 */
+ fimc_is_set_rate_dt(pdev, "dout_atclk_cam1", 1);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_dbg_cam1", 1);
+
+ return 0;
+}
+
+int exynos5430_cfg_clk_sclk(struct platform_device *pdev)
+{
+#ifndef CONFIG_COMPANION_USE
+ /* SCLK_SPI0 */
+ fimc_is_set_parent_dt(pdev, "mout_sclk_isp_spi0", "mout_bus_pll_user");
+ fimc_is_set_rate_dt(pdev, "dout_sclk_isp_spi0_a", 275 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_sclk_isp_spi0_b", 46 * 1000000);
+ fimc_is_set_parent_dt(pdev, "mout_sclk_isp_spi0_user", "sclk_isp_spi0_top");
+
+#endif
+ /* SCLK_SPI1 */
+ fimc_is_set_parent_dt(pdev, "mout_sclk_isp_spi1", "mout_bus_pll_user");
+ fimc_is_set_rate_dt(pdev, "dout_sclk_isp_spi1_a", 275 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_sclk_isp_spi1_b", 46 * 1000000);
+ fimc_is_set_parent_dt(pdev, "mout_sclk_isp_spi1_user", "sclk_isp_spi1_top");
+
+ return 0;
+}
+
+int exynos5430_cfg_clk_cam0(struct platform_device *pdev)
+{
+ /* USER_MUX_SEL */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam0_552_user", "aclk_cam0_552");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam0_400_user", "aclk_cam0_400");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam0_333_user", "aclk_cam0_333");
+ fimc_is_set_parent_dt(pdev, "mout_phyclk_rxbyteclkhs0_s4", "phyclk_rxbyteclkhs0_s4");
+ fimc_is_set_parent_dt(pdev, "mout_phyclk_rxbyteclkhs0_s2a", "phyclk_rxbyteclkhs0_s2a");
+ fimc_is_set_parent_dt(pdev, "mout_phyclk_rxbyteclkhs0_s2b", "phyclk_rxbyteclkhs0_s2b");
+
+ /* LITE A */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_lite_a_a", "mout_aclk_cam0_552_user");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_lite_a_b", "mout_aclk_lite_a_a");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_lite_a", 552 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_lite_a", 276 * 1000000);
+
+ /* LITE B */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_lite_b_a", "mout_aclk_cam0_552_user");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_lite_b_b", "mout_aclk_lite_b_a");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_lite_b", 552 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_lite_b", 276 * 1000000);
+
+ /* LITE D */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_lite_d_a", "mout_aclk_cam0_552_user");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_lite_d_b", "mout_aclk_lite_d_a");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_lite_d", 552 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_lite_d", 276 * 1000000);
+
+ /* LITE C PIXELASYNC */
+ fimc_is_set_parent_dt(pdev, "mout_sclk_pixelasync_lite_c_init_a", "mout_aclk_cam0_552_user");
+ fimc_is_set_parent_dt(pdev, "mout_sclk_pixelasync_lite_c_init_b", "mout_sclk_pixelasync_lite_c_init_a");
+ fimc_is_set_rate_dt(pdev, "dout_sclk_pixelasync_lite_c_init", 552 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_pixelasync_lite_c", 276 * 1000000);
+
+ fimc_is_set_parent_dt(pdev, "mout_sclk_pixelasync_lite_c_a", "mout_aclk_cam0_552_user");
+ fimc_is_set_parent_dt(pdev, "mout_sclk_pixelasync_lite_c_b", "mout_aclk_cam0_333_user");
+ fimc_is_set_rate_dt(pdev, "dout_sclk_pixelasync_lite_c", 333 * 1000000);
+
+ /* 3AA 0 */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_3aa0_a", "mout_aclk_cam0_552_user");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_3aa0_b", "mout_aclk_3aa0_a");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_3aa0", 552 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_3aa0", 276 * 1000000);
+
+ /* 3AA 0 */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_3aa1_a", "mout_aclk_cam0_552_user");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_3aa1_b", "mout_aclk_3aa1_a");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_3aa1", 552 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_3aa1", 276 * 1000000);
+
+ /* CSI 0 */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_csis0_a", "mout_aclk_cam0_552_user");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_csis0_b", "mout_aclk_csis0_a");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_csis0", 552 * 1000000);
+
+ /* CSI 1 */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_csis1_a", "mout_aclk_cam0_552_user");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_csis1_b", "mout_aclk_csis1_a");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_csis1", 552 * 1000000);
+
+ /* CAM0 400 */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam0_400", "mout_aclk_cam0_400_user");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_cam0_400", 413 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_aclk_cam0_200", 207 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_cam0_50", 52 * 1000000);
+
+ return 0;
+}
+
+int exynos5430_cfg_clk_cam1(struct platform_device *pdev)
+{
+ /* USER_MUX_SEL */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam1_552_user", "aclk_cam1_552");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam1_400_user", "aclk_cam1_400");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam1_333_user", "aclk_cam1_333");
+
+ /* C-A5 */
+ fimc_is_set_rate_dt(pdev, "dout_atclk_cam1", 276 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_dbg_cam1", 138 * 1000000);
+
+ /* LITE A */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_lite_c_a", "mout_aclk_cam1_400_user");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_lite_c_b", "mout_aclk_cam1_333_user");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_lite_c", 333 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_lite_c", 166 * 1000000);
+
+ /* FD */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_fd_a", "mout_aclk_cam1_400_user");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_fd_b", "mout_aclk_fd_a");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_fd", 413 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_fd", 207 * 1000000);
+
+ /* CSI 2 */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_csis2_a", "mout_aclk_cam1_400_user");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_csis2_b", "mout_aclk_cam1_333_user");
+ fimc_is_set_rate_dt(pdev, "dout_aclk_csis2_a", 333 * 1000000);
+
+ /* MPWM */
+ fimc_is_set_rate_dt(pdev, "dout_pclk_cam1_166", 167 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_cam1_83", 84 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_sclk_isp_mpwm", 84 * 1000000);
+
+ /* CAM1 QE CLK GATE */
+ fimc_is_enable_dt(pdev, "gate_bts_fd");
+ fimc_is_disable_dt(pdev, "gate_bts_fd");
+
+ return 0;
+}
+
+int exynos5430_cfg_clk_cam1_spi(struct platform_device *pdev)
+{
+ /* USER_MUX_SEL */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_cam1_333_user", "aclk_cam1_333");
+
+ /* SPI */
+ fimc_is_set_rate_dt(pdev, "dout_pclk_cam1_83", 84 * 1000000);
+
+ return 0;
+}
+
+int exynos5430_cfg_clk_isp(struct platform_device *pdev)
+{
+ /* CMU_ISP */
+ /* USER_MUX_SEL */
+ fimc_is_set_parent_dt(pdev, "mout_aclk_isp_400_user", "aclk_isp_400");
+ fimc_is_set_parent_dt(pdev, "mout_aclk_isp_dis_400_user", "aclk_isp_dis_400");
+ /* ISP */
+ fimc_is_set_rate_dt(pdev, "dout_aclk_isp_c_200", 207 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_aclk_isp_d_200", 207 * 1000000);
+ fimc_is_set_rate_dt(pdev, "dout_pclk_isp", 83 * 1000000);
+ /* DIS */
+ fimc_is_set_rate_dt(pdev, "dout_pclk_isp_dis", 207 * 1000000);
+
+ /* ISP QE CLK GATE */
+ fimc_is_enable_dt(pdev, "gate_bts_3dnr");
+ fimc_is_enable_dt(pdev, "gate_bts_dis1");
+ fimc_is_enable_dt(pdev, "gate_bts_dis0");
+ fimc_is_enable_dt(pdev, "gate_bts_scalerc");
+ fimc_is_enable_dt(pdev, "gate_bts_drc");
+ fimc_is_disable_dt(pdev, "gate_bts_3dnr");
+ fimc_is_disable_dt(pdev, "gate_bts_dis1");
+ fimc_is_disable_dt(pdev, "gate_bts_dis0");
+ fimc_is_disable_dt(pdev, "gate_bts_scalerc");
+ fimc_is_disable_dt(pdev, "gate_bts_drc");
+
+ return 0;
+}
+
+int exynos5430_fimc_is_cfg_clk(struct platform_device *pdev)
+{
+ pr_debug("%s\n", __func__);
+
+ exynos5430_cfg_clk_isp_pll_on(pdev);
+ exynos5430_cfg_clk_div_max(pdev);
+
+ /* initialize Clocks */
+ exynos5430_cfg_clk_sclk(pdev);
+ exynos5430_cfg_clk_cam0(pdev);
+ exynos5430_cfg_clk_cam1(pdev);
+ exynos5430_cfg_clk_isp(pdev);
+
+ return 0;
+}
+
+static int exynos_fimc_is_sensor_iclk_init(struct platform_device *pdev)
+{
+ fimc_is_enable_dt(pdev, "aclk_csis0");
+ fimc_is_enable_dt(pdev, "pclk_csis0");
+ fimc_is_enable_dt(pdev, "aclk_csis1");
+ fimc_is_enable_dt(pdev, "pclk_csis1");
+ fimc_is_enable_dt(pdev, "gate_csis2");
+ fimc_is_enable_dt(pdev, "gate_lite_a");
+ fimc_is_enable_dt(pdev, "gate_lite_b");
+ fimc_is_enable_dt(pdev, "gate_lite_d");
+ fimc_is_enable_dt(pdev, "gate_lite_c");
+ fimc_is_enable_dt(pdev, "gate_lite_freecnt");
+
+ return 0;
+}
+
+static int exynos_fimc_is_sensor_iclk_deinit(struct platform_device *pdev)
+{
+ fimc_is_disable_dt(pdev, "aclk_csis0");
+ fimc_is_disable_dt(pdev, "pclk_csis0");
+ fimc_is_disable_dt(pdev, "aclk_csis1");
+ fimc_is_disable_dt(pdev, "pclk_csis1");
+ fimc_is_disable_dt(pdev, "gate_csis2");
+ fimc_is_disable_dt(pdev, "gate_lite_a");
+ fimc_is_disable_dt(pdev, "gate_lite_b");
+ fimc_is_disable_dt(pdev, "gate_lite_d");
+ fimc_is_disable_dt(pdev, "gate_lite_c");
+ fimc_is_disable_dt(pdev, "gate_lite_freecnt");
+
+ return 0;
+}
+
+int exynos5430_fimc_is_clk_on(struct platform_device *pdev)
+{
+ pr_debug("%s\n", __func__);
+
+ exynos_fimc_is_sensor_iclk_init(pdev);
+ exynos_fimc_is_sensor_iclk_deinit(pdev);
+
+ return 0;
+}
+
+int exynos5430_fimc_is_clk_off(struct platform_device *pdev)
+{
+ pr_debug("%s\n", __func__);
+
+ exynos5430_cfg_clk_div_max(pdev);
+ exynos5430_cfg_clk_isp_pll_off(pdev);
+
+ return 0;
+}
+
+int exynos5430_fimc_is_print_clk(struct platform_device *pdev)
+{
+ pr_debug("%s\n", __func__);
+
+ /* SCLK */
+ /* SCLK_SPI0 */
+ fimc_is_get_rate_dt(pdev, "sclk_isp_spi0_top");
+ fimc_is_get_rate_dt(pdev, "sclk_isp_spi0");
+ /* SCLK_SPI1 */
+ fimc_is_get_rate_dt(pdev, "sclk_isp_spi1_top");
+ fimc_is_get_rate_dt(pdev, "sclk_isp_spi1");
+ /* SCLK_UART */
+ fimc_is_get_rate_dt(pdev, "sclk_isp_uart_top");
+ fimc_is_get_rate_dt(pdev, "sclk_isp_uart");
+
+ /* CAM0 */
+ /* CMU_TOP */
+ fimc_is_get_rate_dt(pdev, "aclk_cam0_552");
+ fimc_is_get_rate_dt(pdev, "aclk_cam0_400");
+ fimc_is_get_rate_dt(pdev, "aclk_cam0_333");
+ /* LITE A */
+ fimc_is_get_rate_dt(pdev, "dout_aclk_lite_a");
+ fimc_is_get_rate_dt(pdev, "dout_pclk_lite_a");
+ /* LITE B */
+ fimc_is_get_rate_dt(pdev, "dout_aclk_lite_b");
+ fimc_is_get_rate_dt(pdev, "dout_pclk_lite_b");
+ /* LITE D */
+ fimc_is_get_rate_dt(pdev, "dout_aclk_lite_d");
+ fimc_is_get_rate_dt(pdev, "dout_pclk_lite_d");
+ /* LITE C PIXELASYNC */
+ fimc_is_get_rate_dt(pdev, "dout_sclk_pixelasync_lite_c_init");
+ fimc_is_get_rate_dt(pdev, "dout_pclk_pixelasync_lite_c");
+ fimc_is_get_rate_dt(pdev, "dout_sclk_pixelasync_lite_c");
+ /* 3AA 0 */
+ fimc_is_get_rate_dt(pdev, "dout_aclk_3aa0");
+ fimc_is_get_rate_dt(pdev, "dout_pclk_3aa0");
+ /* 3AA 0 */
+ fimc_is_get_rate_dt(pdev, "dout_aclk_3aa1");
+ fimc_is_get_rate_dt(pdev, "dout_pclk_3aa1");
+ /* CSI 0 */
+ fimc_is_get_rate_dt(pdev, "dout_aclk_csis0");
+ /* CSI 1 */
+ fimc_is_get_rate_dt(pdev, "dout_aclk_csis1");
+ /* CAM0 400 */
+ fimc_is_get_rate_dt(pdev, "dout_aclk_cam0_400");
+ fimc_is_get_rate_dt(pdev, "dout_aclk_cam0_200");
+ fimc_is_get_rate_dt(pdev, "dout_pclk_cam0_50");
+
+ /* CAM1 */
+ /* CMU_TOP */
+ fimc_is_get_rate_dt(pdev, "aclk_cam1_552");
+ fimc_is_get_rate_dt(pdev, "aclk_cam1_400");
+ fimc_is_get_rate_dt(pdev, "aclk_cam1_333");
+ /* C-A5 */
+ fimc_is_get_rate_dt(pdev, "dout_atclk_cam1");
+ fimc_is_get_rate_dt(pdev, "dout_pclk_dbg_cam1");
+ /* LITE A */
+ fimc_is_get_rate_dt(pdev, "dout_aclk_lite_c");
+ fimc_is_get_rate_dt(pdev, "dout_pclk_lite_c");
+ /* FD */
+ fimc_is_get_rate_dt(pdev, "dout_aclk_fd");
+ fimc_is_get_rate_dt(pdev, "dout_pclk_fd");
+ /* CSI 2 */
+ fimc_is_get_rate_dt(pdev, "dout_aclk_csis2_a");
+ /* MPWM */
+ fimc_is_get_rate_dt(pdev, "dout_pclk_cam1_166");
+ fimc_is_get_rate_dt(pdev, "dout_pclk_cam1_83");
+ fimc_is_get_rate_dt(pdev, "dout_sclk_isp_mpwm");
+
+ /* ISP */
+ /* CMU_TOP */
+ fimc_is_get_rate_dt(pdev, "aclk_isp_400");
+ fimc_is_get_rate_dt(pdev, "aclk_isp_dis_400");
+ /* ISP */
+ fimc_is_get_rate_dt(pdev, "dout_aclk_isp_c_200");
+ fimc_is_get_rate_dt(pdev, "dout_aclk_isp_d_200");
+ fimc_is_get_rate_dt(pdev, "dout_pclk_isp");
+ /* DIS */
+ fimc_is_get_rate_dt(pdev, "dout_pclk_isp_dis");
+
+ /* CMU_TOP_DUMP */
+ pr_info("EXYNOS5430_SRC_SEL_TOP1(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_TOP1));
+ pr_info("EXYNOS5430_SRC_SEL_TOP2(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_TOP2));
+ pr_info("EXYNOS5430_SRC_SEL_TOP_CAM1(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_TOP_CAM1));
+ pr_info("EXYNOS5430_SRC_ENABLE_TOP0(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_TOP0));
+ pr_info("EXYNOS5430_SRC_ENABLE_TOP1(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_TOP1));
+ pr_info("EXYNOS5430_SRC_ENABLE_TOP2(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_TOP2));
+ pr_info("EXYNOS5430_SRC_ENABLE_TOP3(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_TOP3));
+ pr_info("EXYNOS5430_SRC_ENABLE_TOP_CAM1(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_TOP_CAM1));
+ pr_info("EXYNOS5430_DIV_TOP0(0x%08X)\n", readl(EXYNOS5430_DIV_TOP0));
+ pr_info("EXYNOS5430_DIV_TOP_CAM10(0x%08X)\n", readl(EXYNOS5430_DIV_TOP_CAM10));
+ pr_info("EXYNOS5430_DIV_TOP_CAM11(0x%08X)\n", readl(EXYNOS5430_DIV_TOP_CAM11));
+ pr_info("EXYNOS5430_ENABLE_SCLK_TOP_CAM1(0x%08X)\n", readl(EXYNOS5430_ENABLE_SCLK_TOP_CAM1));
+ pr_info("EXYNOS5430_ENABLE_IP_TOP(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_TOP));
+ /* CMU_CAM0_DUMP */
+ pr_info("EXYNOS5430_SRC_SEL_CAM00(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_CAM00));
+ pr_info("EXYNOS5430_SRC_SEL_CAM01(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_CAM01));
+ pr_info("EXYNOS5430_SRC_SEL_CAM02(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_CAM02));
+ pr_info("EXYNOS5430_SRC_SEL_CAM03(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_CAM03));
+ pr_info("EXYNOS5430_SRC_SEL_CAM04(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_CAM04));
+ pr_info("EXYNOS5430_SRC_ENABLE_CAM00(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_CAM00));
+ pr_info("EXYNOS5430_SRC_ENABLE_CAM01(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_CAM01));
+ pr_info("EXYNOS5430_SRC_ENABLE_CAM02(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_CAM02));
+ pr_info("EXYNOS5430_SRC_ENABLE_CAM03(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_CAM03));
+ pr_info("EXYNOS5430_SRC_ENABLE_CAM04(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_CAM04));
+ pr_info("EXYNOS5430_SRC_STAT_CAM00(0x%08X)\n", readl(EXYNOS5430_SRC_STAT_CAM00));
+ pr_info("EXYNOS5430_SRC_STAT_CAM01(0x%08X)\n", readl(EXYNOS5430_SRC_STAT_CAM01));
+ pr_info("EXYNOS5430_SRC_STAT_CAM02(0x%08X)\n", readl(EXYNOS5430_SRC_STAT_CAM02));
+ pr_info("EXYNOS5430_SRC_STAT_CAM03(0x%08X)\n", readl(EXYNOS5430_SRC_STAT_CAM03));
+ pr_info("EXYNOS5430_SRC_STAT_CAM04(0x%08X)\n", readl(EXYNOS5430_SRC_STAT_CAM04));
+ pr_info("EXYNOS5430_SRC_IGNORE_CAM01(0x%08X)\n", readl(EXYNOS5430_SRC_IGNORE_CAM01));
+ pr_info("EXYNOS5430_DIV_CAM00(0x%08X)\n", readl(EXYNOS5430_DIV_CAM00));
+ pr_info("EXYNOS5430_DIV_CAM01(0x%08X)\n", readl(EXYNOS5430_DIV_CAM01));
+ pr_info("EXYNOS5430_DIV_CAM02(0x%08X)\n", readl(EXYNOS5430_DIV_CAM02));
+ pr_info("EXYNOS5430_DIV_CAM03(0x%08X)\n", readl(EXYNOS5430_DIV_CAM03));
+ pr_info("EXYNOS5430_DIV_STAT_CAM00(0x%08X)\n", readl(EXYNOS5430_DIV_STAT_CAM00));
+ pr_info("EXYNOS5430_DIV_STAT_CAM01(0x%08X)\n", readl(EXYNOS5430_DIV_STAT_CAM01));
+ pr_info("EXYNOS5430_DIV_STAT_CAM02(0x%08X)\n", readl(EXYNOS5430_DIV_STAT_CAM02));
+ pr_info("EXYNOS5430_DIV_STAT_CAM03(0x%08X)\n", readl(EXYNOS5430_DIV_STAT_CAM03));
+ pr_info("EXYNOS5430_ENABLE_IP_CAM00(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM00));
+ pr_info("EXYNOS5430_ENABLE_IP_CAM01(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM01));
+ pr_info("EXYNOS5430_ENABLE_IP_CAM02(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM02));
+ pr_info("EXYNOS5430_ENABLE_IP_CAM03(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM03));
+ /* CMU_CAM1_DUMP */
+ pr_info("EXYNOS5430_SRC_SEL_CAM10(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_CAM10));
+ pr_info("EXYNOS5430_SRC_SEL_CAM11(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_CAM11));
+ pr_info("EXYNOS5430_SRC_SEL_CAM12(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_CAM12));
+ pr_info("EXYNOS5430_SRC_ENABLE_CAM10(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_CAM10));
+ pr_info("EXYNOS5430_SRC_ENABLE_CAM11(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_CAM11));
+ pr_info("EXYNOS5430_SRC_ENABLE_CAM12(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_CAM12));
+ pr_info("EXYNOS5430_SRC_STAT_CAM10(0x%08X)\n", readl(EXYNOS5430_SRC_STAT_CAM10));
+ pr_info("EXYNOS5430_SRC_STAT_CAM11(0x%08X)\n", readl(EXYNOS5430_SRC_STAT_CAM11));
+ pr_info("EXYNOS5430_SRC_STAT_CAM12(0x%08X)\n", readl(EXYNOS5430_SRC_STAT_CAM12));
+ pr_info("EXYNOS5430_SRC_IGNORE_CAM11(0x%08X)\n", readl(EXYNOS5430_SRC_IGNORE_CAM11));
+ pr_info("EXYNOS5430_DIV_CAM10(0x%08X)\n", readl(EXYNOS5430_DIV_CAM10));
+ pr_info("EXYNOS5430_DIV_CAM11(0x%08X)\n", readl(EXYNOS5430_DIV_CAM11));
+ pr_info("EXYNOS5430_DIV_STAT_CAM10(0x%08X)\n", readl(EXYNOS5430_DIV_STAT_CAM10));
+ pr_info("EXYNOS5430_DIV_STAT_CAM11(0x%08X)\n", readl(EXYNOS5430_DIV_STAT_CAM11));
+ pr_info("EXYNOS5430_ENABLE_SCLK_CAM1(0x%08X)\n", readl(EXYNOS5430_ENABLE_SCLK_CAM1));
+ pr_info("EXYNOS5430_ENABLE_IP_CAM10(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM10));
+ pr_info("EXYNOS5430_ENABLE_IP_CAM11(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM11));
+ pr_info("EXYNOS5430_ENABLE_IP_CAM12(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM12));
+ /* CMU_ISP_DUMP */
+ pr_info("EXYNOS5430_SRC_SEL_ISP(0x%08X)\n", readl(EXYNOS5430_SRC_SEL_ISP));
+ pr_info("EXYNOS5430_SRC_ENABLE_ISP(0x%08X)\n", readl(EXYNOS5430_SRC_ENABLE_ISP));
+ pr_info("EXYNOS5430_SRC_STAT_ISP(0x%08X)\n", readl(EXYNOS5430_SRC_STAT_ISP));
+ pr_info("EXYNOS5430_DIV_ISP(0x%08X)\n", readl(EXYNOS5430_DIV_ISP));
+ pr_info("EXYNOS5430_DIV_STAT_ISP(0x%08X)\n", readl(EXYNOS5430_DIV_STAT_ISP));
+ pr_info("EXYNOS5430_ENABLE_ACLK_ISP0(0x%08X)\n", readl(EXYNOS5430_ENABLE_ACLK_ISP0));
+ pr_info("EXYNOS5430_ENABLE_ACLK_ISP1(0x%08X)\n", readl(EXYNOS5430_ENABLE_ACLK_ISP1));
+ pr_info("EXYNOS5430_ENABLE_ACLK_ISP2(0x%08X)\n", readl(EXYNOS5430_ENABLE_ACLK_ISP2));
+ pr_info("EXYNOS5430_ENABLE_PCLK_ISP(0x%08X)\n", readl(EXYNOS5430_ENABLE_PCLK_ISP));
+ pr_info("EXYNOS5430_ENABLE_SCLK_ISP(0x%08X)\n", readl(EXYNOS5430_ENABLE_SCLK_ISP));
+ pr_info("EXYNOS5430_ENABLE_IP_ISP0(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_ISP0));
+ pr_info("EXYNOS5430_ENABLE_IP_ISP1(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_ISP1));
+ pr_info("EXYNOS5430_ENABLE_IP_ISP2(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_ISP2));
+ pr_info("EXYNOS5430_ENABLE_IP_ISP3(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_ISP3));
+ /* CMU_ENABLE_DUMP */
+ pr_info("EXYNOS5430_ENABLE_SCLK_TOP_CAM1(0x%08X)\n", readl(EXYNOS5430_ENABLE_SCLK_TOP_CAM1));
+ pr_info("EXYNOS5430_ENABLE_IP_TOP(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_TOP));
+ pr_info("EXYNOS5430_ENABLE_IP_CAM00(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM00));
+ pr_info("EXYNOS5430_ENABLE_IP_CAM01(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM01));
+ pr_info("EXYNOS5430_ENABLE_IP_CAM02(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM02));
+ pr_info("EXYNOS5430_ENABLE_IP_CAM03(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM03));
+ pr_info("EXYNOS5430_ENABLE_IP_CAM10(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM10));
+ pr_info("EXYNOS5430_ENABLE_IP_CAM11(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM11));
+ pr_info("EXYNOS5430_ENABLE_IP_CAM12(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_CAM12));
+ pr_info("EXYNOS5430_ENABLE_IP_ISP0(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_ISP0));
+ pr_info("EXYNOS5430_ENABLE_IP_ISP1(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_ISP1));
+ pr_info("EXYNOS5430_ENABLE_IP_ISP2(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_ISP2));
+ pr_info("EXYNOS5430_ENABLE_IP_ISP3(0x%08X)\n", readl(EXYNOS5430_ENABLE_IP_ISP3));
+
+ return 0;
+}
+
+/* sequence is important, don't change order */
+int exynos5430_fimc_is_sensor_power_on(struct platform_device *pdev, int sensor_id)
+{
+ pr_debug("%s\n", __func__);
+
+ return 0;
+}
+
+/* sequence is important, don't change order */
+int exynos5430_fimc_is_sensor_power_off(struct platform_device *pdev, int sensor_id)
+{
+ pr_debug("%s\n", __func__);
+
+ return 0;
+}
+
+int exynos5430_fimc_is_print_pwr(struct platform_device *pdev)
+{
+ pr_debug("%s\n", __func__);
+
+ pr_info("ISP power state(0x%08x)\n", readl(EXYNOS5430_ISP_STATUS));
+ pr_info("CAM0 power state(0x%08x)\n", readl(EXYNOS5430_CAM0_STATUS));
+ pr_info("CAM1 power state(0x%08x)\n", readl(EXYNOS5430_CAM1_STATUS));
+ pr_info("CA5 power state(0x%08x)\n", readl(EXYNOS5430_A5IS_STATUS));
+
+ return 0;
+}
+
+int exynos5430_fimc_is_set_user_clk_gate(u32 group_id,
+ bool is_on,
+ u32 user_scenario_id,
+ unsigned long msk_state,
+ struct exynos_fimc_is_clk_gate_info *gate_info) {
+ /* if you want to skip clock on/off, let this func return -1 */
+ int ret = -1;
+
+ switch (user_scenario_id) {
+ case CLK_GATE_NOT_FULL_BYPASS_SN:
+ if (is_on == true)
+ gate_info->groups[group_id].mask_clk_on_mod &=
+ ~((1 << FIMC_IS_GATE_DIS_IP) |
+ (1 << FIMC_IS_GATE_3DNR_IP));
+ else
+ gate_info->groups[group_id].mask_clk_on_mod |=
+ ((1 << FIMC_IS_GATE_DIS_IP) |
+ (1 << FIMC_IS_GATE_3DNR_IP));
+ ret = 0;
+ break;
+ case CLK_GATE_DIS_SN:
+ if (is_on == true)
+ gate_info->groups[group_id].mask_clk_on_mod |=
+ ((1 << FIMC_IS_GATE_DIS_IP) |
+ (1 << FIMC_IS_GATE_3DNR_IP));
+ else
+ gate_info->groups[group_id].mask_clk_on_mod &=
+ ~((1 << FIMC_IS_GATE_DIS_IP) |
+ (1 << FIMC_IS_GATE_3DNR_IP));
+ ret = 0;
+ break;
+ default:
+ ret = 0;
+ break;
+ }
+
+ return ret;
+}
+#endif
+
+/* Wrapper functions */
+int exynos_fimc_is_cfg_clk(struct platform_device *pdev)
+{
+#if defined(CONFIG_SOC_EXYNOS5422)
+ exynos5422_fimc_is_cfg_clk(pdev);
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+ exynos5430_fimc_is_cfg_clk(pdev);
+#endif
+ return 0;
+}
+
+int exynos_fimc_is_cfg_cam_clk(struct platform_device *pdev)
+{
+#if defined(CONFIG_SOC_EXYNOS5422)
+ exynos5422_cfg_clk_sclk(pdev);
+ exynos5422_cfg_clk_cam(pdev);
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+ exynos5430_cfg_clk_sclk(pdev);
+ exynos5430_cfg_clk_cam1_spi(pdev);
+#endif
+ return 0;
+}
+
+int exynos_fimc_is_clk_on(struct platform_device *pdev)
+{
+#if defined(CONFIG_SOC_EXYNOS5422)
+ exynos5422_fimc_is_clk_on(pdev);
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+ exynos5430_fimc_is_clk_on(pdev);
+#endif
+ return 0;
+}
+
+int exynos_fimc_is_clk_off(struct platform_device *pdev)
+{
+#if defined(CONFIG_SOC_EXYNOS5422)
+ exynos5422_fimc_is_clk_off(pdev);
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+ exynos5430_fimc_is_clk_off(pdev);
+#endif
+ return 0;
+}
+
+int exynos_fimc_is_print_clk(struct platform_device *pdev)
+{
+#if defined(CONFIG_SOC_EXYNOS5422)
+ exynos5422_fimc_is_print_clk(pdev);
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+ exynos5430_fimc_is_print_clk(pdev);
+#endif
+ return 0;
+}
+
+int exynos_fimc_is_set_user_clk_gate(u32 group_id, bool is_on,
+ u32 user_scenario_id,
+ unsigned long msk_state,
+ struct exynos_fimc_is_clk_gate_info *gate_info)
+{
+#if defined(CONFIG_SOC_EXYNOS5422)
+ exynos5422_fimc_is_set_user_clk_gate(group_id, is_on, user_scenario_id, msk_state, gate_info);
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+ exynos5430_fimc_is_set_user_clk_gate(group_id, is_on, user_scenario_id, msk_state, gate_info);
+#endif
+ return 0;
+}
+
+int exynos_fimc_is_clk_gate(u32 clk_gate_id, bool is_on)
+{
+#if defined(CONFIG_SOC_EXYNOS5422)
+ exynos5422_fimc_is_clk_gate(clk_gate_id, is_on);
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+ exynos5430_fimc_is_clk_gate(clk_gate_id, is_on);
+#endif
+ return 0;
+}
+
+int exynos_fimc_is_sensor_power_on(struct platform_device *pdev, int sensor_id)
+{
+#if defined(CONFIG_SOC_EXYNOS5422)
+ exynos5422_fimc_is_sensor_power_on(pdev, sensor_id);
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+ exynos5430_fimc_is_sensor_power_on(pdev, sensor_id);
+#endif
+ return 0;
+}
+
+int exynos_fimc_is_sensor_power_off(struct platform_device *pdev, int sensor_id)
+{
+#if defined(CONFIG_SOC_EXYNOS5422)
+ exynos5422_fimc_is_sensor_power_off(pdev, sensor_id);
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+ exynos5430_fimc_is_sensor_power_off(pdev, sensor_id);
+#endif
+ return 0;
+}
+
+int exynos_fimc_is_print_pwr(struct platform_device *pdev)
+{
+#if defined(CONFIG_SOC_EXYNOS5422)
+ exynos5422_fimc_is_print_pwr(pdev);
+#elif defined(CONFIG_SOC_EXYNOS5430) || defined(CONFIG_SOC_EXYNOS5433)
+ exynos5430_fimc_is_print_pwr(pdev);
+#endif
+ return 0;
+}
--- /dev/null
+/*
+ * Copyright (c) 2012 Samsung Electronics.
+ *
+ * EXYNOS - SMC Call
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_EXYNOS_SMC_H
+#define __ASM_ARCH_EXYNOS_SMC_H
+
+#define SMC_CMD_INIT (-1)
+#define SMC_CMD_INFO (-2)
+/* For Power Management */
+#define SMC_CMD_SLEEP (-3)
+#define SMC_CMD_CPU1BOOT (-4)
+#define SMC_CMD_CPU0AFTR (-5)
+#define SMC_CMD_SAVE (-6)
+#define SMC_CMD_SHUTDOWN (-7)
+/* For CP15 Access */
+#define SMC_CMD_C15RESUME (-11)
+/* For L2 Cache Access */
+#define SMC_CMD_L2X0CTRL (-21)
+#define SMC_CMD_L2X0SETUP1 (-22)
+#define SMC_CMD_L2X0SETUP2 (-23)
+#define SMC_CMD_L2X0INVALL (-24)
+#define SMC_CMD_L2X0DEBUG (-25)
+
+/* For Accessing CP15/SFR (General) */
+#define SMC_CMD_REG (-101)
+
+/* For setting memory for debug */
+#define SMC_CMD_SET_DEBUG_MEM (-120)
+
+/* Command ID for smc */
+#define SMC_PROTECTION_SET 0x81000000
+#define SMC_DRM_FW_LOADING 0x81000001
+#define SMC_DCPP_SUPPORT 0x81000002
+#define SMC_DRM_MAKE_PGTABLE 0x81000003
+#define SMC_DRM_CLEAR_PGTABLE 0x81000004
+#define SMC_MEM_PROT_SET 0x81000005
+#define SMC_DRM_SECMEM_INFO 0x81000006
+#define SMC_DRM_VIDEO_PROC 0x81000007
+
+/* Parameter for smc */
+#define SMC_PROTECTION_ENABLE 1
+#define SMC_PROTECTION_DISABLE 0
+
+/* For FMP Ctrl */
+#define SMC_CMD_FMP 0x81000020
+
+/* For DTRNG Access */
+#ifdef CONFIG_EXYRNG_USE_CRYPTOMANAGER
+#define SMC_CMD_RANDOM 0x82001012
+#else
+#define SMC_CMD_RANDOM 0x81000030
+#endif
+
+/* MACRO for SMC_CMD_REG */
+#define SMC_REG_CLASS_CP15 (0x0 << 30)
+#define SMC_REG_CLASS_SFR_W (0x1 << 30)
+#define SMC_REG_CLASS_SFR_R (0x3 << 30)
+#define SMC_REG_CLASS_MASK (0x3 << 30)
+#define SMC_REG_ID_CP15(CRn, Op1, CRm, Op2) \
+ (SMC_REG_CLASS_CP15 | (CRn << 10) | (Op1 << 7) | (CRm << 3) | (Op2))
+#define SMC_REG_ID_SFR_W(addr) (SMC_REG_CLASS_SFR_W | ((addr) >> 2))
+#define SMC_REG_ID_SFR_R(addr) (SMC_REG_CLASS_SFR_R | ((addr) >> 2))
+
+/* op type for SMC_CMD_SAVE and SMC_CMD_SHUTDOWN */
+#define OP_TYPE_CORE 0x0
+#define OP_TYPE_CLUSTER 0x1
+
+/* Power State required for SMC_CMD_SAVE and SMC_CMD_SHUTDOWN */
+#define SMC_POWERSTATE_SLEEP 0x0
+#define SMC_POWERSTATE_IDLE 0x1
+#define SMC_POWERSTATE_SWITCH 0x2
+
+/* For DTRNG Access */
+#define HWRNG_INIT 0x0
+#define HWRNG_EXIT 0x1
+#define HWRNG_GET_DATA 0x2
+#define HWRNG_RESUME 0x3
+
+#ifndef __ASSEMBLY__
+extern int exynos_smc(unsigned long cmd, unsigned long arg1, unsigned long arg2,
+ unsigned long arg3);
+extern int exynos_smc_readsfr(unsigned long addr, unsigned long* val);
+#endif
+
+#endif
--- /dev/null
+/*
+ * Video for Linux Two header file for samsung
+ *
+ * Copyright (C) 2009, Dongsoo Nathaniel Kim<dongsoo45.kim@samsung.com>
+ *
+ * This header file contains several v4l2 APIs to be proposed to v4l2
+ * community and until bein accepted, will be used restrictly in Samsung's
+ * camera interface driver FIMC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __LINUX_VIDEODEV2_EXYNOS_CAMERA_H
+#define __LINUX_VIDEODEV2_EXYNOS_CAMERA_H
+
+/* Following CIDs are menu type */
+#define V4L2_CID_SCENEMODE (V4L2_CID_CAMERA_CLASS_BASE+23)
+#define V4L2_CID_CAM_STABILIZE (V4L2_CID_CAMERA_CLASS_BASE+24)
+#define V4L2_CID_CAM_MULTISHOT (V4L2_CID_CAMERA_CLASS_BASE+25)
+
+/* Control dynamic range */
+#define V4L2_CID_CAM_DR (V4L2_CID_CAMERA_CLASS_BASE+26)
+
+/* White balance preset control */
+#define V4L2_CID_WHITE_BALANCE_PRESET (V4L2_CID_CAMERA_CLASS_BASE+27)
+#define V4L2_CID_CAM_SENSOR_FW_VER (V4L2_CID_CAMERA_CLASS_BASE + 28)
+#define V4L2_CID_CAM_PHONE_FW_VER (V4L2_CID_CAMERA_CLASS_BASE + 29)
+
+#define V4L2_CID_FIMC_IS_BASE (V4L2_CTRL_CLASS_CAMERA | 0x1000)
+#define V4L2_CID_FIMC_IS_TUNE_BASE (V4L2_CTRL_CLASS_CAMERA | 0x2000)
+#define V4L2_CID_SENSOR_BASE (V4L2_CTRL_CLASS_CAMERA | 0x3000)
+
+#define V4L2_CID_IS_S_STREAM (V4L2_CID_FIMC_IS_BASE + 14)
+enum is_set_stream {
+ IS_DISABLE_STREAM,
+ IS_ENABLE_STREAM
+};
+
+#define V4L2_CID_IS_G_STREAM (V4L2_CID_FIMC_IS_BASE + 15)
+#define V4L2_CID_IS_G_CAPABILITY (V4L2_CID_FIMC_IS_BASE + 17)
+#define V4L2_CID_IS_G_COMPLETES (V4L2_CID_FIMC_IS_BASE + 18)
+#define V4L2_CID_IS_BDS_WIDTH (V4L2_CID_FIMC_IS_BASE + 19)
+#define V4L2_CID_IS_BDS_HEIGHT (V4L2_CID_FIMC_IS_BASE + 20)
+#define V4L2_CID_IS_DVFS_LOCK (V4L2_CID_FIMC_IS_BASE + 21)
+#define V4L2_CID_IS_DVFS_UNLOCK (V4L2_CID_FIMC_IS_BASE + 22)
+#define V4L2_CID_IS_FORCE_DONE (V4L2_CID_FIMC_IS_BASE + 50)
+#define V4L2_CID_IS_SET_SETFILE (V4L2_CID_FIMC_IS_BASE + 51)
+#define V4L2_CID_IS_S_BNS (V4L2_CID_FIMC_IS_BASE + 52)
+#define V4L2_CID_IS_G_BNS_SIZE (V4L2_CID_FIMC_IS_BASE + 53)
+#define V4L2_CID_IS_COLOR_RANGE (V4L2_CID_FIMC_IS_BASE + 54)
+#define V4L2_CID_IS_MIN_TARGET_FPS (V4L2_CID_FIMC_IS_BASE + 55)
+#define V4L2_CID_IS_MAX_TARGET_FPS (V4L2_CID_FIMC_IS_BASE + 56)
+#define V4L2_CID_IS_G_DTPSTATUS (V4L2_CID_FIMC_IS_BASE + 57)
+#define V4L2_CID_IS_END_OF_STREAM (V4L2_CID_FIMC_IS_BASE + 58)
+#define V4L2_CID_IS_MAP_BUFFER (V4L2_CID_FIMC_IS_BASE + 59)
+#define V4L2_CID_IS_INTENT (V4L2_CID_FIMC_IS_BASE + 60)
+
+#define V4L2_CID_SENSOR_SET_AE_TARGET (V4L2_CID_SENSOR_BASE + 1)
+#define V4L2_CID_SENSOR_SET_AE_WEIGHT_1x1_2 (V4L2_CID_SENSOR_BASE + 2)
+#define V4L2_CID_SENSOR_SET_AE_WEIGHT_1x3_4 (V4L2_CID_SENSOR_BASE + 3)
+#define V4L2_CID_SENSOR_SET_AE_WEIGHT_2x1_2 (V4L2_CID_SENSOR_BASE + 4)
+#define V4L2_CID_SENSOR_SET_AE_WEIGHT_2x3_4 (V4L2_CID_SENSOR_BASE + 5)
+#define V4L2_CID_SENSOR_SET_AE_WEIGHT_3x1_2 (V4L2_CID_SENSOR_BASE + 6)
+#define V4L2_CID_SENSOR_SET_AE_WEIGHT_3x3_4 (V4L2_CID_SENSOR_BASE + 7)
+#define V4L2_CID_SENSOR_SET_AE_WEIGHT_4x1_2 (V4L2_CID_SENSOR_BASE + 8)
+#define V4L2_CID_SENSOR_SET_AE_WEIGHT_4x3_4 (V4L2_CID_SENSOR_BASE + 9)
+#define V4L2_CID_SENSOR_SET_RG_WEIGHT (V4L2_CID_SENSOR_BASE + 10)
+#define V4L2_CID_SENSOR_SET_AE_SPEED (V4L2_CID_SENSOR_BASE + 11)
+#define V4L2_CID_SENSOR_SET_SHUTTER (V4L2_CID_SENSOR_BASE + 12)
+#define V4L2_CID_SENSOR_SET_GAIN (V4L2_CID_SENSOR_BASE + 13)
+#define V4L2_CID_SENSOR_SET_BIT_CONVERTING (V4L2_CID_SENSOR_BASE + 14)
+#define V4L2_CID_SENSOR_SET_AUTO_EXPOSURE (V4L2_CID_SENSOR_BASE + 15)
+#define V4L2_CID_SENSOR_SET_FRAME_RATE (V4L2_CID_SENSOR_BASE + 16)
+
+#define V4L2_CID_CAMERA_OIS_SINE_MODE (V4L2_CID_PRIVATE_BASE+152)
+
+#endif /* __LINUX_VIDEODEV2_EXYNOS_CAMERA_H */
projects / platform / kernel / linux-exynos.git / commitdiff