Add support for the MIPS P5600 family of CPUs.
authorAndrew Bennett <andrew.bennett@imgtec.com>
Tue, 8 Apr 2014 13:50:42 +0000 (14:50 +0100)
committerAndrew Bennett <andrew.bennett@imgtec.com>
Thu, 10 Apr 2014 09:20:50 +0000 (10:20 +0100)
ChangeLog:

2014-04-10  Andrew Bennett  <andrew.bennett@imgtec.com>

* config/tc-mips.c (mips_cpu_info_table): Add P5600
configuation.
* doc/c-mips.texi: Document p5600.

gas/ChangeLog
gas/config/tc-mips.c
gas/doc/c-mips.texi

index 62f5138..326b47c 100644 (file)
@@ -1,3 +1,9 @@
+2014-04-10  Andrew Bennett  <andrew.bennett@imgtec.com>
+
+       * config/tc-mips.c (mips_cpu_info_table): Add P5600
+       configuation.
+       * doc/c-mips.texi: Document p5600.
+
 2014-04-09  Nick Clifton  <nickc@redhat.com>
 
        * config/tc-rl78.h (TC_CONS_FIX_NEW): Add RELOC parameter.
index 318b0b5..47de8d3 100644 (file)
@@ -17902,6 +17902,8 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
   { "1004kf2_1",      0, ASE_DSP | ASE_MT,     ISA_MIPS32R2, CPU_MIPS32R2 },
   { "1004kf",         0, ASE_DSP | ASE_MT,     ISA_MIPS32R2, CPU_MIPS32R2 },
   { "1004kf1_1",      0, ASE_DSP | ASE_MT,     ISA_MIPS32R2, CPU_MIPS32R2 },
+  /* P5600 with EVA and Virtualization ASEs, other ASEs are optional.  */
+  { "p5600",          0, ASE_VIRT | ASE_EVA,   ISA_MIPS32R2, CPU_MIPS32R2 },
 
   /* MIPS 64 */
   { "5kc",            0, 0,                    ISA_MIPS64,   CPU_MIPS64 },
index 184915e..3778ae2 100644 (file)
@@ -337,6 +337,7 @@ m14kec,
 1004kf2_1,
 1004kf,
 1004kf1_1,
+p5600,
 5kc,
 5kf,
 20kc,