clock_am43xx:Set the MAC clock to /5 for OPP100

When EMAC is in the boot order, the boot ROM sets OPP50 and the
MAC clock is set to /2. SPL needs to change it to /5 for Ethernet
to generate the correct txclk. This patch sets it correctly.

Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>

diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index 31188c8..529a119 100644 (file)
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -118,4 +118,7 @@ void enable_basic_clocks(void)
 
        /* Select the Master osc clk as Timer2 clock source */
        writel(0x1, &cmdpll->clktimer2clk);
+
+       /* For OPP100 the mac clock should be /5. */
+       writel(0x4, &cmdpll->clkselmacclk);
 }

diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index b94b56c..523d22e 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -400,6 +400,8 @@ struct prm_device_inst {
 struct cm_dpll {
        unsigned int resv1;
        unsigned int clktimer2clk;      /* offset 0x04 */
+       unsigned int resv2[11];
+       unsigned int clkselmacclk;      /* offset 0x34 */ 
 };
 #endif /* CONFIG_AM43XX */