arm: dts: mediatek: add PCIe node for MT7622

This patch adds PCIe node in dts for Mediatek MT7622 Soc.

Signed-off-by: Chuanjia Liu <Chuanjia.Liu@mediatek.com>
Signed-off-by: Henry Yen <henry.yen@mediatek.com>

diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts
index f05c3fe..317fc78 100644 (file)
--- a/arch/arm/dts/mt7622-rfb.dts
+++ b/arch/arm/dts/mt7622-rfb.dts
@@ -46,8 +46,39 @@
        };
 };
 
+&pcie {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
+       status = "okay";
+
+       pcie@0,0 {
+               status = "okay";
+       };
+
+       pcie@1,0 {
+               status = "okay";
+       };
+};
 
 &pinctrl {
+       pcie0_pins: pcie0-pins {
+               mux {
+                       function = "pcie";
+                       groups = "pcie0_pad_perst",
+                                "pcie0_1_waken",
+                                "pcie0_1_clkreq";
+               };
+       };
+
+       pcie1_pins: pcie1-pins {
+               mux {
+                       function = "pcie";
+                       groups = "pcie1_pad_perst",
+                                "pcie1_0_waken",
+                                "pcie1_0_clkreq";
+               };
+       };
+
        snfi_pins: snfi-pins {
                mux {
                        function = "flash";

diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
index f6919bb..d0783bc 100644 (file)
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -193,6 +193,78 @@
                #reset-cells = <1>;
        };
 
+       pcie: pcie@1a140000 {
+               compatible = "mediatek,mt7622-pcie";
+               device_type = "pci";
+               reg = <0x1a140000 0x1000>,
+                     <0x1a143000 0x1000>,
+                     <0x1a145000 0x1000>;
+               reg-names = "subsys", "port0", "port1";
+               #address-cells = <3>;
+               #size-cells = <2>;
+               interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
+                            <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+               clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
+                        <&pciesys CLK_PCIE_P1_MAC_EN>,
+                        <&pciesys CLK_PCIE_P0_AHB_EN>,
+                        <&pciesys CLK_PCIE_P0_AHB_EN>,
+                        <&pciesys CLK_PCIE_P0_AUX_EN>,
+                        <&pciesys CLK_PCIE_P1_AUX_EN>,
+                        <&pciesys CLK_PCIE_P0_AXI_EN>,
+                        <&pciesys CLK_PCIE_P1_AXI_EN>,
+                        <&pciesys CLK_PCIE_P0_OBFF_EN>,
+                        <&pciesys CLK_PCIE_P1_OBFF_EN>,
+                        <&pciesys CLK_PCIE_P0_PIPE_EN>,
+                        <&pciesys CLK_PCIE_P1_PIPE_EN>;
+               clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
+                             "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
+                             "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
+               power-domains = <&scpsys MT7629_POWER_DOMAIN_HIF0>;
+               bus-range = <0x00 0xff>;
+               ranges = <0x82000000 0 0x20000000 0x20000000 0 0x10000000>;
+               status = "disabled";
+
+               pcie0: pcie@0,0 {
+                       reg = <0x0000 0 0 0 0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       ranges;
+                       status = "disabled";
+
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+                                       <0 0 0 2 &pcie_intc0 1>,
+                                       <0 0 0 3 &pcie_intc0 2>,
+                                       <0 0 0 4 &pcie_intc0 3>;
+                       pcie_intc0: interrupt-controller {
+                               interrupt-controller;
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                       };
+               };
+
+               pcie1: pcie@1,0 {
+                       reg = <0x0800 0 0 0 0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       ranges;
+                       status = "disabled";
+
+                       interrupt-map-mask = <0 0 0 7>;
+                       interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+                                       <0 0 0 2 &pcie_intc1 1>,
+                                       <0 0 0 3 &pcie_intc1 2>,
+                                       <0 0 0 4 &pcie_intc1 3>;
+                       pcie_intc1: interrupt-controller {
+                               interrupt-controller;
+                               #address-cells = <0>;
+                               #interrupt-cells = <1>;
+                       };
+               };
+       };
+
        ethsys: syscon@1b000000 {
                compatible = "mediatek,mt7622-ethsys", "syscon";
                reg = <0x1b000000 0x1000>;