arm64: tegra: Add SPI device tree nodes for Tegra234

Create the device tree nodes for the SPI1, SPI2 and SPI3 controllers
found on Tegra234.

Signed-off-by: Gautham Srinivasan <gauthams@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index f067326739c64f8567047115c2d0d200ae76a181..95524e5bce8262e3b4681b824ad9cecffd335ba3 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -818,6 +818,44 @@
                        dma-names = "rx", "tx";
                };
 
+               spi@3210000 {
+                       compatible = "nvidia,tegra210-spi";
+                       reg = <0x0 0x03210000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&bpmp TEGRA234_CLK_SPI1>;
+                       assigned-clocks = <&bpmp TEGRA234_CLK_SPI1>;
+                       assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+                       clock-names = "spi";
+                       iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+                       resets = <&bpmp TEGRA234_RESET_SPI1>;
+                       reset-names = "spi";
+                       dmas = <&gpcdma 15>, <&gpcdma 15>;
+                       dma-names = "rx", "tx";
+                       dma-coherent;
+                       status = "disabled";
+               };
+
+               spi@3230000 {
+                       compatible = "nvidia,tegra210-spi";
+                       reg = <0x0 0x03230000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&bpmp TEGRA234_CLK_SPI3>;
+                       clock-names = "spi";
+                       iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+                       assigned-clocks = <&bpmp TEGRA234_CLK_SPI3>;
+                       assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+                       resets = <&bpmp TEGRA234_RESET_SPI3>;
+                       reset-names = "spi";
+                       dmas = <&gpcdma 17>, <&gpcdma 17>;
+                       dma-names = "rx", "tx";
+                       dma-coherent;
+                       status = "disabled";
+               };
+
                spi@3270000 {
                        compatible = "nvidia,tegra234-qspi";
                        reg = <0x0 0x3270000 0x0 0x1000>;
@@ -1743,6 +1781,25 @@
                        dma-names = "rx", "tx";
                };
 
+               spi@c260000 {
+                       compatible = "nvidia,tegra210-spi";
+                       reg = <0x0 0x0c260000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&bpmp TEGRA234_CLK_SPI2>;
+                       clock-names = "spi";
+                       iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
+                       assigned-clocks = <&bpmp TEGRA234_CLK_SPI2>;
+                       assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
+                       resets = <&bpmp TEGRA234_RESET_SPI2>;
+                       reset-names = "spi";
+                       dmas = <&gpcdma 19>, <&gpcdma 19>;
+                       dma-names = "rx", "tx";
+                       dma-coherent;
+                       status = "disabled";
+               };
+
                rtc@c2a0000 {
                        compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
                        reg = <0x0 0x0c2a0000 0x0 0x10000>;