(Also included in this patch is a minor typo fix in gold/ChangeLog.)
When linking the following tlsdesc access sequence into an executable with -pie,
adrp x0, :tlsdesc:tls_gd
ldr x1, [x0, #:tlsdesc_lo12:tls_gd]
add x0, x0, :tlsdesc_lo12:tls_gd
.tlsdesccall tls_gd
blr x1
mrs x1, tpidr_el0
add x0, x1, x0
ldr w0, [x0]
current gold-aarch64 backend does tls-desc-gd-to-ie relaxation, into
adrp x0, 1000 <__FRAME_END__+0x720>
ldr x1, [x0,#4064] ;; <=== the target register should be x0
nop
nop
mrs x1, tpidr_el0
add x0, x1, x0
ldr w0, [x0]
This code is wrong. The fix changes ldr target register into x0.
+2014-11-26 Jing Yu <jingyu@google.com>
+
+ * aarch64.cc (Relocate::tls_desc_gd_to_ie): Set ldr target
+ register to be x0 when to relax TLSDESC_LD64_LO12.
+
2014-11-26 Alan Modra <amodra@gmail.com>
* powerpc.cc (struct Stub_table_owner): New.
* aarch64.cc (AArch64_relocate_functions::maybe_apply_stub):
Add "typename" keyword.
-2014-09-22 Han Shen <shenhan@google.com>
+2014-10-15 Han Shen <shenhan@google.com>
Jing Yu <jingyu@google.com>
Patch for gold aarch64 backend to support relaxation.
case elfcpp::R_AARCH64_TLSDESC_LD64_LO12:
{
+ // Set ldr target register to be x0.
+ Insntype insn = elfcpp::Swap<32, big_endian>::readval(ip);
+ insn &= 0xffffffe0;
+ elfcpp::Swap<32, big_endian>::writeval(ip, insn);
+ // Do relocation.
const AArch64_reloc_property* reloc_property =
aarch64_reloc_property_table->get_reloc_property(
elfcpp::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC);