Merge branch 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarn...

* 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/drm-intel:
  drm/i915: do not enable RC6p on Sandy Bridge
  drm/i915: gen7: Disable the RHWO optimization as it can cause GPU hangs.
  drm/i915: gen7: work around a system hang on IVB
  drm/i915: gen7: Implement an L3 caching workaround.
  drm/i915: gen7: implement rczunit workaround

diff --combined drivers/gpu/drm/i915/intel_display.c
index 00fbff5,049804e..f425b23
--- 1/drivers/gpu/drm/i915/intel_display.c
--- 2/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@@ -1872,7 -1872,7 +1872,7 @@@ static void intel_update_fbc(struct drm
        if (enable_fbc < 0) {
                DRM_DEBUG_KMS("fbc set to per-chip default\n");
                enable_fbc = 1;
 -              if (INTEL_INFO(dev)->gen <= 5)
 +              if (INTEL_INFO(dev)->gen <= 6)
                        enable_fbc = 0;
        }
        if (!enable_fbc) {
@@@ -5307,7 -5307,6 +5307,7 @@@ static int i9xx_crtc_mode_set(struct dr
                }
        }
  
 +      pipeconf &= ~PIPECONF_INTERLACE_MASK;
        if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
                pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
                /* the chip adds 2 halflines automatically */
@@@ -5318,7 -5317,7 +5318,7 @@@
                adjusted_mode->crtc_vsync_end -= 1;
                adjusted_mode->crtc_vsync_start -= 1;
        } else
 -              pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */
 +              pipeconf |= PIPECONF_PROGRESSIVE;
  
        I915_WRITE(HTOTAL(pipe),
                   (adjusted_mode->crtc_hdisplay - 1) |
@@@ -5903,7 -5902,6 +5903,7 @@@ static int ironlake_crtc_mode_set(struc
                }
        }
  
 +      pipeconf &= ~PIPECONF_INTERLACE_MASK;
        if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
                pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
                /* the chip adds 2 halflines automatically */
@@@ -5914,7 -5912,7 +5914,7 @@@
                adjusted_mode->crtc_vsync_end -= 1;
                adjusted_mode->crtc_vsync_start -= 1;
        } else
 -              pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
 +              pipeconf |= PIPECONF_PROGRESSIVE;
  
        I915_WRITE(HTOTAL(pipe),
                   (adjusted_mode->crtc_hdisplay - 1) |
@@@ -8184,8 -8182,8 +8184,8 @@@ void gen6_enable_rps(struct drm_i915_pr
        I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
  
        if (intel_enable_rc6(dev_priv->dev))
-               rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
-                       GEN6_RC_CTL_RC6_ENABLE;
+               rc6_mask = GEN6_RC_CTL_RC6_ENABLE |
+                       (IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0;
  
        I915_WRITE(GEN6_RC_CONTROL,
                   rc6_mask |
@@@ -8463,12 -8461,32 +8463,32 @@@ static void ivybridge_init_clock_gating
        I915_WRITE(WM2_LP_ILK, 0);
        I915_WRITE(WM1_LP_ILK, 0);
  
+       /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
+        * This implements the WaDisableRCZUnitClockGating workaround.
+        */
+       I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
+ 
        I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
  
        I915_WRITE(IVB_CHICKEN3,
                   CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
                   CHICKEN3_DGMG_DONE_FIX_DISABLE);
  
+       /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
+       I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
+                  GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
+ 
+       /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
+       I915_WRITE(GEN7_L3CNTLREG1,
+                       GEN7_WA_FOR_GEN7_L3_CONTROL);
+       I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
+                       GEN7_WA_L3_CHICKEN_MODE);
+ 
+       /* This is required by WaCatErrorRejectionIssue */
+       I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
+                       I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
+                       GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
+ 
        for_each_pipe(pipe) {
                I915_WRITE(DSPCNTR(pipe),
                           I915_READ(DSPCNTR(pipe)) |