(define_expand "uminsi3"
[(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (const_int -2147483648)))
+ (match_dup 5)))
(set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
- (const_int -2147483648)))
+ (match_dup 5)))
(set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
(const_int 0)
(minus:SI (match_dup 4) (match_dup 3))))
(minus:SI (match_dup 2) (match_dup 3)))]
"TARGET_POWER"
"
-{ operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
+{
+ operands[3] = gen_reg_rtx (SImode);
+ operands[4] = gen_reg_rtx (SImode);
+ operands[5] = GEN_INT (-2147483647 - 1);
+}")
(define_expand "umaxsi3"
[(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
- (const_int -2147483648)))
+ (match_dup 5)))
(set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
- (const_int -2147483648)))
+ (match_dup 5)))
(set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
(const_int 0)
(minus:SI (match_dup 4) (match_dup 3))))
(plus:SI (match_dup 3) (match_dup 1)))]
"TARGET_POWER"
"
-{ operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
+{
+ operands[3] = gen_reg_rtx (SImode);
+ operands[4] = gen_reg_rtx (SImode);
+ operands[5] = GEN_INT (-2147483647 - 1);
+}")
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")