#define DSIM_STATE_CMD_LPM BIT(2)
#define DSIM_STATE_VIDOUT_AVAILABLE BIT(3)
+#define exynos_dsi_hw_is_exynos(hw) \
+ ((hw) >= DSIM_TYPE_EXYNOS3250 && (hw) <= DSIM_TYPE_EXYNOS5433)
+
enum exynos_dsi_type {
DSIM_TYPE_EXYNOS3250,
DSIM_TYPE_EXYNOS4210,
{
const struct exynos_dsi_driver_data *driver_data = dsi->driver_data;
+ if (dsi->state & DSIM_STATE_INITIALIZED)
+ return 0;
+
exynos_dsi_reset(dsi);
exynos_dsi_enable_irq(dsi);
exynos_dsi_set_phy_ctrl(dsi);
exynos_dsi_init_link(dsi);
+ dsi->state |= DSIM_STATE_INITIALIZED;
+
return 0;
}
}
dsi->state |= DSIM_STATE_ENABLED;
+
+ /*
+ * For Exynos-DSIM the downstream bridge, or panel are expecting
+ * the host initialization during DSI transfer.
+ */
+ if (!exynos_dsi_hw_is_exynos(dsi->plat_data->hw_type)) {
+ ret = exynos_dsi_init(dsi);
+ if (ret)
+ return;
+ }
}
static void exynos_dsi_atomic_enable(struct drm_bridge *bridge,
if (!(dsi->state & DSIM_STATE_ENABLED))
return -EINVAL;
- if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
- ret = exynos_dsi_init(dsi);
- if (ret)
- return ret;
- dsi->state |= DSIM_STATE_INITIALIZED;
- }
+ ret = exynos_dsi_init(dsi);
+ if (ret)
+ return ret;
ret = mipi_dsi_create_packet(&xfer.packet, msg);
if (ret < 0)