byte_xor_operation:
CC_STATUS_INIT;
- if (intval == 0xff)
+ if (intval == 0xff
+ && (!TARGET_PENTIUM || optimize_size
+ || (GET_CODE (operands[0]) == MEM
+ && memory_address_length (XEXP (operands[0], 0)) != 0)))
return AS1 (not%B0,%b0);
if (intval != INTVAL (operands[2]))
if (REG_P (operands[0]))
{
CC_STATUS_INIT;
- if (intval == 0xff)
+ if (intval == 0xff
+ && (!TARGET_PENTIUM || optimize_size
+ || (GET_CODE (operands[0]) == MEM
+ && memory_address_length (XEXP (operands[0], 0)) != 0)))
return AS1 (not%B0,%h0);
operands[2] = GEN_INT (intval);
if (INTVAL (operands[2]) & 0xffff0000)
operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
- if (INTVAL (operands[2]) == 0xff)
+ if (INTVAL (operands[2]) == 0xff
+ && (!TARGET_PENTIUM || optimize_size
+ || (GET_CODE (operands[0]) == MEM
+ && memory_address_length (XEXP (operands[0], 0)) != 0)))
return AS1 (not%B0,%b0);
return AS2 (xor%B0,%2,%b0);
CC_STATUS_INIT;
operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff);
- if (INTVAL (operands[2]) == 0xff)
+ if (INTVAL (operands[2]) == 0xff
+ && (!TARGET_PENTIUM || optimize_size
+ || (GET_CODE (operands[0]) == MEM
+ && memory_address_length (XEXP (operands[0], 0)) != 0)))
return AS1 (not%B0,%h0);
return AS2 (xor%B0,%2,%h0);
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(not:SI (match_operand:SI 1 "nonimmediate_operand" "0")))]
""
- "not%L0 %0")
+ "*
+/* A Pentium NOT is not pariable. Output it only in case of complex
+ memory address, because XOR will be inpariable anyway because
+ of immediate/displacement rule. */
+
+if (TARGET_PENTIUM && !optimize_size
+ && (GET_CODE (operands[0]) != MEM
+ || memory_address_length (XEXP (operands[0], 0)) == 0))
+ {
+ rtx xops[2];
+ xops[0] = operands[0];
+ xops[1] = GEN_INT (0xffffffff);
+ output_asm_insn (AS2 (xor%L0,%1,%0), xops);
+ RET;
+ }
+else
+ return AS1 (not%L0,%0);")
(define_insn "one_cmplhi2"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(not:HI (match_operand:HI 1 "nonimmediate_operand" "0")))]
""
- "not%W0 %0")
+ "*
+/* A Pentium NOT is not pariable. Output it only in case of complex
+ memory address, because XOR will be inpariable anyway because
+ of immediate/displacement rule. */
+
+if (TARGET_PENTIUM && !optimize_size
+ && (GET_CODE (operands[0]) != MEM
+ || memory_address_length (XEXP (operands[0], 0)) == 0))
+ {
+ rtx xops[2];
+ xops[0] = operands[0];
+ xops[1] = GEN_INT (0xffff);
+ if (REG_P (operands[0])
+ && i386_cc_probably_useless_p (insn))
+ {
+ CC_STATUS_INIT;
+ output_asm_insn (AS2 (xor%L0,%1,%k0), xops);
+ }
+ else
+ output_asm_insn (AS2 (xor%W0,%1,%0), xops);
+ RET;
+ }
+else
+ {
+ if (REG_P (operands[0])
+ && i386_cc_probably_useless_p (insn))
+ {
+ CC_STATUS_INIT;
+ return AS1 (not%L0,%k0);
+ }
+ return AS1 (not%W0,%0);
+ }")
(define_insn "one_cmplqi2"
[(set (match_operand:QI 0 "nonimmediate_operand" "=qm")
(not:QI (match_operand:QI 1 "nonimmediate_operand" "0")))]
""
- "not%B0 %0")
+ "*
+/* A Pentium NOT is not pariable. Output it only in case of complex
+ memory address, because XOR will be inpariable anyway because
+ of immediate/displacement rule. */
+
+if (TARGET_PENTIUM && !optimize_size
+ && (GET_CODE (operands[0]) != MEM
+ || memory_address_length (XEXP (operands[0], 0)) == 0))
+ {
+ rtx xops[2];
+ xops[0] = operands[0];
+ xops[1] = GEN_INT (0xff);
+ output_asm_insn (AS2 (xor%B0,%1,%0), xops);
+ RET;
+ }
+else
+ return AS1 (not%B0,%0);")
\f
;;- arithmetic shift instructions