drm/amdgpu: Adjust MES polling timeout for sriov

[why]
MES response time in sriov may be longer than default value
due to reset or init in other VF. A timeout value specific
to sriov is needed.

[how]
When in sriov, adjust the timeout value to calculated
worst case scenario.

Signed-off-by: Yiqing Yao <yiqing.yao@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
index fef7d02..f141fad 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
@@ -98,7 +98,14 @@ static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
        struct amdgpu_device *adev = mes->adev;
        struct amdgpu_ring *ring = &mes->ring;
        unsigned long flags;
+       signed long timeout = adev->usec_timeout;
 
+       if (amdgpu_emu_mode) {
+               timeout *= 100;
+       } else if (amdgpu_sriov_vf(adev)) {
+               /* Worst case in sriov where all other 15 VF timeout, each VF needs about 600ms */
+               timeout = 15 * 600 * 1000;
+       }
        BUG_ON(size % 4 != 0);
 
        spin_lock_irqsave(&mes->ring_lock, flags);
@@ -118,7 +125,7 @@ static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes,
        DRM_DEBUG("MES msg=%d was emitted\n", x_pkt->header.opcode);
 
        r = amdgpu_fence_wait_polling(ring, ring->fence_drv.sync_seq,
-                     adev->usec_timeout * (amdgpu_emu_mode ? 100 : 1));
+                     timeout);
        if (r < 1) {
                DRM_ERROR("MES failed to response msg=%d\n",
                          x_pkt->header.opcode);