else if (TARGET_POWERPC64)
{
- HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
+ HOST_WIDE_INT low = sext_hwi (value, 32);
HOST_WIDE_INT high = value >> 31;
if (high == 0 || high == -1)
}
/* We only care if the access(es) would cause a change to the high part. */
- offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
+ offset = sext_hwi (offset, 16);
return SIGNED_16BIT_OFFSET_EXTRA_P (offset, extra);
}
if (GET_CODE (addr) == LO_SUM)
/* For lo_sum addresses, we must allow any offset except one that
causes a wrap, so test only the low 16 bits. */
- offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
+ offset = sext_hwi (offset, 16);
return SIGNED_16BIT_OFFSET_EXTRA_P (offset, extra);
}
if (GET_CODE (addr) == LO_SUM)
/* For lo_sum addresses, we must allow any offset except one that
causes a wrap, so test only the low 16 bits. */
- offset = ((offset & 0xffff) ^ 0x8000) - 0x8000;
+ offset = sext_hwi (offset, 16);
return SIGNED_16BIT_OFFSET_EXTRA_P (offset, extra);
}
{
HOST_WIDE_INT high_int, low_int;
rtx sum;
- low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
+ low_int = sext_hwi (INTVAL (XEXP (x, 1)), 16);
if (low_int >= 0x8000 - extra)
low_int = 0;
high_int = INTVAL (XEXP (x, 1)) - low_int;
lo = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
DImode);
emit_move_insn (hi, GEN_INT (c >> 32));
- c = ((c & 0xffffffff) ^ 0x80000000) - 0x80000000;
+ c = sext_hwi (c, 32);
emit_move_insn (lo, GEN_INT (c));
}
else
if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
|| (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
- emit_move_insn (dest, GEN_INT ((ud1 ^ 0x8000) - 0x8000));
+ emit_move_insn (dest, GEN_INT (sext_hwi (ud1, 16)));
else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
|| (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
emit_move_insn (ud1 != 0 ? copy_rtx (temp) : dest,
- GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
+ GEN_INT (sext_hwi (ud2 << 16, 32)));
if (ud1 != 0)
emit_move_insn (dest,
gen_rtx_IOR (DImode, copy_rtx (temp),
temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
gcc_assert (ud2 & 0x8000);
- emit_move_insn (copy_rtx (temp),
- GEN_INT (((ud2 << 16) ^ 0x80000000) - 0x80000000));
+ emit_move_insn (copy_rtx (temp), GEN_INT (sext_hwi (ud2 << 16, 32)));
if (ud1 != 0)
emit_move_insn (copy_rtx (temp),
gen_rtx_IOR (DImode, copy_rtx (temp),
{
temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
HOST_WIDE_INT num = (ud2 << 16) | ud1;
- rs6000_emit_set_long_const (temp, (num ^ 0x80000000) - 0x80000000);
+ rs6000_emit_set_long_const (temp, sext_hwi (num, 32));
rtx one = gen_rtx_AND (DImode, temp, GEN_INT (0xffffffff));
rtx two = gen_rtx_ASHIFT (DImode, temp, GEN_INT (32));
emit_move_insn (dest, gen_rtx_IOR (DImode, one, two));
{
temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
- emit_move_insn (copy_rtx (temp),
- GEN_INT (((ud3 << 16) ^ 0x80000000) - 0x80000000));
+ emit_move_insn (copy_rtx (temp), GEN_INT (sext_hwi (ud3 << 16, 32)));
if (ud2 != 0)
emit_move_insn (copy_rtx (temp),
gen_rtx_IOR (DImode, copy_rtx (temp),
{
temp = !can_create_pseudo_p () ? dest : gen_reg_rtx (DImode);
- emit_move_insn (copy_rtx (temp),
- GEN_INT (((ud4 << 16) ^ 0x80000000) - 0x80000000));
+ emit_move_insn (copy_rtx (temp), GEN_INT (sext_hwi (ud4 << 16, 32)));
if (ud3 != 0)
emit_move_insn (copy_rtx (temp),
gen_rtx_IOR (DImode, copy_rtx (temp),
/* If constant, low-order 16 bits of constant, signed. Otherwise, write
normally. */
if (INT_P (x))
- fprintf (file, HOST_WIDE_INT_PRINT_DEC,
- ((INTVAL (x) & 0xffff) ^ 0x8000) - 0x8000);
+ fprintf (file, HOST_WIDE_INT_PRINT_DEC, sext_hwi (INTVAL (x), 16));
else
print_operand (file, x, 0);
return;
/* See if we can use VSPLTISH or VSPLTISW. */
if (vsx_const->all_half_words_same)
{
- unsigned short h_word = vsx_const->half_words[0];
- short sign_h_word = ((h_word & 0xffff) ^ 0x8000) - 0x8000;
+ short sign_h_word = vsx_const->half_words[0];
if (EASY_VECTOR_15 (sign_h_word))
return 0;
}
- unsigned int word = vsx_const->words[0];
- int sign_word = ((word & 0xffffffff) ^ 0x80000000) - 0x80000000;
+ int sign_word = vsx_const->words[0];
if (EASY_VECTOR_15 (sign_word))
return 0;
}
HOST_WIDE_INT val = INTVAL (operands[2]);
- HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
+ HOST_WIDE_INT low = sext_hwi (val, 16);
HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
(set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
{
HOST_WIDE_INT val = INTVAL (operands[2]);
- HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
+ HOST_WIDE_INT low = sext_hwi (val, 16);
HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
operands[4] = GEN_INT (low);
operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode);
operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode);
operands[4] = GEN_INT (value >> 32);
- operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
+ operands[1] = GEN_INT (sext_hwi (value, 32));
})
(define_split
operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
DImode);
operands[4] = GEN_INT (value >> 32);
- operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
+ operands[1] = GEN_INT (sext_hwi (value, 32));
})
(define_split
SImode,
operands[1], operands[2]);
HOST_WIDE_INT c = INTVAL (cnst);
- HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
+ HOST_WIDE_INT sextc = sext_hwi (c, 16);
HOST_WIDE_INT xorv = c ^ sextc;
operands[9] = GEN_INT (xorv);