ARM: tegra: Enable PCIe controller on Beaver

PCIe lane 0 is connected to an onboard Gigabit Ethernet (RTL8168evl) and
lane 4 is routed to the board's miniPCIe slot.

Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 1de4ff6..21660da 100644 (file)
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -10,6 +10,27 @@
                reg = <0x80000000 0x7ff00000>;
        };
 
+       pcie-controller {
+               status = "okay";
+               pex-clk-supply = <&sys_3v3_pexs_reg>;
+               vdd-supply = <&ldo1_reg>;
+               avdd-supply = <&ldo2_reg>;
+
+               pci@1,0 {
+                       status = "okay";
+                       nvidia,num-lanes = <4>;
+               };
+
+               pci@2,0 {
+                       status = "okay";
+                       nvidia,num-lanes = <1>;
+               };
+
+               pci@3,0 {
+                       nvidia,num-lanes = <1>;
+               };
+       };
+
        host1x {
                hdmi {
                        status = "okay";