gas/testsuite/:

	* gas/m68k/cpu32.[sd]: New test.
	* gas/m68k/all.exp: Run it.

opcodes/:
	* m68k-opc.c: Fix encoding of signed bit in the cpu32 tbls insns.

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 84859ba..40a5895 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2007-01-04  Andreas Schwab  <schwab@suse.de>
+
+       * gas/m68k/cpu32.[sd]: New test.
+       * gas/m68k/all.exp: Run it.
+
 2007-01-04  Julian Brown  <julian@codesourcery.com>
 
        * gas/arm/neon-omit.d: Fix expected encodings for vshl, vqshl.

diff --git a/gas/testsuite/gas/m68k/all.exp b/gas/testsuite/gas/m68k/all.exp
index 8b43ed4..88a3088 100644 (file)
--- a/gas/testsuite/gas/m68k/all.exp
+++ b/gas/testsuite/gas/m68k/all.exp
@@ -50,6 +50,7 @@ if { [istarget m68*-*-*] || [istarget fido*-*-*] } then {
     run_dump_test mcf-fpu
     run_dump_test mcf-trap
     run_dump_test arch-cpu-1
+    run_dump_test cpu32
 
     set testname "68000 operands"
     gas_run "operands.s" "-m68000" "2>err.out"

diff --git a/gas/testsuite/gas/m68k/cpu32.d b/gas/testsuite/gas/m68k/cpu32.d
new file mode 100644 (file)
index 0000000..84f1d67
--- /dev/null
+++ b/gas/testsuite/gas/m68k/cpu32.d
@@ -0,0 +1,34 @@
+#name: cpu32
+#objdump: -d
+#as: -mcpu32
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+0+ <.text>:
+[ 0-9a-f]+:    4afa            bgnd
+[ 0-9a-f]+:    f800 2001       tblub %d0,%d1,%d2
+[ 0-9a-f]+:    f800 2041       tbluw %d0,%d1,%d2
+[ 0-9a-f]+:    f800 2081       tblul %d0,%d1,%d2
+[ 0-9a-f]+:    f800 2401       tblunb %d0,%d1,%d2
+[ 0-9a-f]+:    f800 2441       tblunw %d0,%d1,%d2
+[ 0-9a-f]+:    f800 2481       tblunl %d0,%d1,%d2
+[ 0-9a-f]+:    f800 2801       tblsb %d0,%d1,%d2
+[ 0-9a-f]+:    f800 2841       tblsw %d0,%d1,%d2
+[ 0-9a-f]+:    f800 2881       tblsl %d0,%d1,%d2
+[ 0-9a-f]+:    f800 2c01       tblsnb %d0,%d1,%d2
+[ 0-9a-f]+:    f800 2c41       tblsnw %d0,%d1,%d2
+[ 0-9a-f]+:    f800 2c81       tblsnl %d0,%d1,%d2
+[ 0-9a-f]+:    f810 1100       tblub %a0@,%d1
+[ 0-9a-f]+:    f810 1140       tbluw %a0@,%d1
+[ 0-9a-f]+:    f810 1180       tblul %a0@,%d1
+[ 0-9a-f]+:    f810 1500       tblunb %a0@,%d1
+[ 0-9a-f]+:    f810 1540       tblunw %a0@,%d1
+[ 0-9a-f]+:    f810 1580       tblunl %a0@,%d1
+[ 0-9a-f]+:    f810 1900       tblsb %a0@,%d1
+[ 0-9a-f]+:    f810 1940       tblsw %a0@,%d1
+[ 0-9a-f]+:    f810 1980       tblsl %a0@,%d1
+[ 0-9a-f]+:    f810 1d00       tblsnb %a0@,%d1
+[ 0-9a-f]+:    f810 1d40       tblsnw %a0@,%d1
+[ 0-9a-f]+:    f810 1d80       tblsnl %a0@,%d1

diff --git a/gas/testsuite/gas/m68k/cpu32.s b/gas/testsuite/gas/m68k/cpu32.s
new file mode 100644 (file)
index 0000000..589e7e3
--- /dev/null
+++ b/gas/testsuite/gas/m68k/cpu32.s
@@ -0,0 +1,26 @@
+       # cpu32 specific insns
+       bgnd
+       tblub   %d0,%d1,%d2
+       tbluw   %d0,%d1,%d2
+       tblul   %d0,%d1,%d2
+       tblunb  %d0,%d1,%d2
+       tblunw  %d0,%d1,%d2
+       tblunl  %d0,%d1,%d2
+       tblsb   %d0,%d1,%d2
+       tblsw   %d0,%d1,%d2
+       tblsl   %d0,%d1,%d2
+       tblsnb  %d0,%d1,%d2
+       tblsnw  %d0,%d1,%d2
+       tblsnl  %d0,%d1,%d2
+       tblub   (%a0),%d1
+       tbluw   (%a0),%d1
+       tblul   (%a0),%d1
+       tblunb  (%a0),%d1
+       tblunw  (%a0),%d1
+       tblunl  (%a0),%d1
+       tblsb   (%a0),%d1
+       tblsw   (%a0),%d1
+       tblsl   (%a0),%d1
+       tblsnb  (%a0),%d1
+       tblsnw  (%a0),%d1
+       tblsnl  (%a0),%d1

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f5cb698..d398506 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2007-01-04  Andreas Schwab  <schwab@suse.de>
+
+       * m68k-opc.c: Fix encoding of signed bit in the cpu32 tbls insns.
+
 2007-01-04  Julian Brown  <julian@codesourcery.com>
 
        * arm-dis.c (neon_opcode): Fix disassembly for vshl, vqshl, vrshl,

diff --git a/opcodes/m68k-opc.c b/opcodes/m68k-opc.c
index 2feafc1..51b62d4 100644 (file)
--- a/opcodes/m68k-opc.c
+++ b/opcodes/m68k-opc.c
@@ -2151,8 +2151,8 @@ const struct m68k_opcode m68k_opcodes[] =
      two(0177770,0107770), "DsD3D1", cpu32 }
 #define TBL(name1, name2, name3, s, r) \
   TBL1(name1, 4, s, r, 0), TBL1(name2, 4, s, r, 1), TBL1(name3, 4, s, r, 2)
-TBL("tblsb", "tblsw", "tblsl", 2, 1),
-TBL("tblsnb", "tblsnw", "tblsnl", 2, 0),
+TBL("tblsb", "tblsw", "tblsl", 1, 1),
+TBL("tblsnb", "tblsnw", "tblsnl", 1, 0),
 TBL("tblub", "tbluw", "tblul", 0, 1),
 TBL("tblunb", "tblunw", "tblunl", 0, 0),