arm64: uniphier: dts: add more clocks to Denali NAND controller node
authorMasahiro Yamada <yamada.masahiro@socionext.com>
Fri, 20 Jul 2018 08:50:45 +0000 (17:50 +0900)
committerMasahiro Yamada <yamada.masahiro@socionext.com>
Tue, 28 Aug 2018 14:14:55 +0000 (23:14 +0900)
Catch up with the new binding of the Denali IP where three clocks,
"nand", "nand_x", "ecc" are required.

For UniPhier SoCs, the "nand_x" and "ecc" are tied up because they
are both 200MHz.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi

index d63b56e..5640dac 100644 (file)
                        interrupts = <0 65 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand>;
-                       clocks = <&sys_clk 2>;
+                       clock-names = "nand", "nand_x", "ecc";
+                       clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
                        resets = <&sys_rst 2>;
                };
        };
index caf1126..6932cef 100644 (file)
                        interrupts = <0 65 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand>;
-                       clocks = <&sys_clk 2>;
+                       clock-names = "nand", "nand_x", "ecc";
+                       clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
                        resets = <&sys_rst 2>;
                };
        };
index 2a4cf42..fd2bcd4 100644 (file)
                        interrupts = <0 65 4>;
                        pinctrl-names = "default";
                        pinctrl-0 = <&pinctrl_nand>;
-                       clocks = <&sys_clk 2>;
+                       clock-names = "nand", "nand_x", "ecc";
+                       clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
                        resets = <&sys_rst 2>;
                };
        };