};
vdac {
- compatible = "amlogic, vdac-tl1";
+ compatible = "amlogic, vdac-tm2";
status = "okay";
};
/* Audio Related end */
tvafe_avin_detect {
- compatible = "amlogic, tl1_tvafe_avin_detect";
+ compatible = "amlogic, tm2_tvafe_avin_detect";
status = "okay";
device_mask = <1>;/*bit0:ch1;bit1:ch2*/
interrupts = <0 12 1>,
tv_bit_mode = <0x15>;
};
+ tvafe {
+ compatible = "amlogic, tvafe-tm2";
+ /*memory-region = <&tvafe_cma_reserved>;*/
+ status = "okay";
+ flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
+ cma_size = <5>;/*MByte*/
+ reg = <0xff654000 0x2000>;/*tvafe reg base*/
+ reserve-iomap = "true";
+ tvafe_id = <0>;
+ //pinctrl-names = "default";
+ /*!!particular sequence, no more and no less!!!*/
+ tvafe_pin_mux = <
+ 3 /* TVAFE_CVBS_IN2, CVBS_IN0 = 0 */
+ 1 /* TVAFE_CVBS_IN0, CVBS_IN1 */
+ 2 /* TVAFE_CVBS_IN1, CVBS_IN2 */
+ 4 /* TVAFE_CVBS_IN3, CVBS_IN3 */
+ >;
+ clocks = <&clkc CLKID_DAC_CLK>;
+ clock-names = "vdac_clk_gate";
+ };
+
+ vbi {
+ compatible = "amlogic, vbi";
+ status = "okay";
+ interrupts = <0 83 1>;
+ };
+
+ cvbsout {
+ compatible = "amlogic, cvbsout-tm2";
+ status = "disabled";
+ clocks = <&clkc CLKID_VCLK2_ENCI
+ &clkc CLKID_VCLK2_VENCI0
+ &clkc CLKID_VCLK2_VENCI1
+ &clkc CLKID_DAC_CLK>;
+ clock-names = "venci_top_gate",
+ "venci_0_gate",
+ "venci_1_gate",
+ "vdac_clk_gate";
+ /* clk path */
+ /* 0:vid_pll vid2_clk */
+ /* 1:gp0_pll vid2_clk */
+ /* 2:vid_pll vid1_clk */
+ /* 3:gp0_pll vid1_clk */
+ clk_path = <0>;
+
+ /* performance: reg_address, reg_value */
+ /* tm2 */
+ performance = <0x1bf0 0x9
+ 0x1b56 0x333
+ 0x1b12 0x8080
+ 0x1b05 0xfd
+ 0x1c59 0xf850
+ 0xffff 0x0>; /* ending flag */
+ performance_sarft = <0x1bf0 0x9
+ 0x1b56 0x333
+ 0x1b12 0x0
+ 0x1b05 0x9
+ 0x1c59 0xfc48
+ 0xffff 0x0>; /* ending flag */
+ performance_revB_telecom = <0x1bf0 0x9
+ 0x1b56 0x546
+ 0x1b12 0x8080
+ 0x1b05 0x9
+ 0x1c59 0xf850
+ 0xffff 0x0>; /* ending flag */
+ };
+
hdmirx {
compatible = "amlogic, hdmirx_tl1";
#address-cells=<1>;
};
tvafe_avin_detect {
- compatible = "amlogic, tl1_tvafe_avin_detect";
+ compatible = "amlogic, tm2_tvafe_avin_detect";
status = "okay";
device_mask = <1>;/*bit0:ch1;bit1:ch2*/
interrupts = <0 12 1>,
};
tvafe {
- compatible = "amlogic, tvafe-tl1";
+ compatible = "amlogic, tvafe-tm2";
/*memory-region = <&tvafe_cma_reserved>;*/
status = "okay";
flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
};
cvbsout {
- compatible = "amlogic, cvbsout-tl1";
+ compatible = "amlogic, cvbsout-tm2";
status = "disabled";
clocks = <&clkc CLKID_VCLK2_ENCI
&clkc CLKID_VCLK2_VENCI0
clk_path = <0>;
/* performance: reg_address, reg_value */
- /* tl1 */
+ /* tm2 */
performance = <0x1bf0 0x9
0x1b56 0x333
0x1b12 0x8080
};
tvafe_avin_detect {
- compatible = "amlogic, tl1_tvafe_avin_detect";
+ compatible = "amlogic, tm2_tvafe_avin_detect";
status = "okay";
device_mask = <1>;/*bit0:ch1;bit1:ch2*/
interrupts = <0 12 1>,
};
tvafe {
- compatible = "amlogic, tvafe-tl1";
+ compatible = "amlogic, tvafe-tm2";
/*memory-region = <&tvafe_cma_reserved>;*/
status = "okay";
flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
};
cvbsout {
- compatible = "amlogic, cvbsout-tl1";
+ compatible = "amlogic, cvbsout-tm2";
status = "disabled";
clocks = <&clkc CLKID_VCLK2_ENCI
&clkc CLKID_VCLK2_VENCI0
clk_path = <0>;
/* performance: reg_address, reg_value */
- /* tl1 */
+ /* tm2 */
performance = <0x1bf0 0x9
0x1b56 0x333
0x1b12 0x8080
};
tvafe_avin_detect {
- compatible = "amlogic, tl1_tvafe_avin_detect";
+ compatible = "amlogic, tm2_tvafe_avin_detect";
status = "okay";
device_mask = <1>;/*bit0:ch1;bit1:ch2*/
interrupts = <0 12 1>,
};
tvafe {
- compatible = "amlogic, tvafe-tl1";
+ compatible = "amlogic, tvafe-tm2";
/*memory-region = <&tvafe_cma_reserved>;*/
status = "okay";
flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
};
cvbsout {
- compatible = "amlogic, cvbsout-tl1";
+ compatible = "amlogic, cvbsout-tm2";
status = "disabled";
clocks = <&clkc CLKID_VCLK2_ENCI
&clkc CLKID_VCLK2_VENCI0
clk_path = <0>;
/* performance: reg_address, reg_value */
- /* tl1 */
+ /* tm2 */
performance = <0x1bf0 0x9
0x1b56 0x333
0x1b12 0x8080
};
tvafe_avin_detect {
- compatible = "amlogic, tl1_tvafe_avin_detect";
+ compatible = "amlogic, tm2_tvafe_avin_detect";
status = "okay";
device_mask = <1>;/*bit0:ch1;bit1:ch2*/
interrupts = <0 12 1>,
};
tvafe {
- compatible = "amlogic, tvafe-tl1";
+ compatible = "amlogic, tvafe-tm2";
/*memory-region = <&tvafe_cma_reserved>;*/
status = "okay";
flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
};
cvbsout {
- compatible = "amlogic, cvbsout-tl1";
+ compatible = "amlogic, cvbsout-tm2";
status = "disabled";
clocks = <&clkc CLKID_VCLK2_ENCI
&clkc CLKID_VCLK2_VENCI0
clk_path = <0>;
/* performance: reg_address, reg_value */
- /* tl1 */
+ /* tm2 */
performance = <0x1bf0 0x9
0x1b56 0x333
0x1b12 0x8080
};
vdac {
- compatible = "amlogic, vdac-tl1";
+ compatible = "amlogic, vdac-tm2";
status = "okay";
};
/* Audio Related end */
tvafe_avin_detect {
- compatible = "amlogic, tl1_tvafe_avin_detect";
+ compatible = "amlogic, tm2_tvafe_avin_detect";
status = "okay";
device_mask = <1>;/*bit0:ch1;bit1:ch2*/
interrupts = <0 12 1>,
tv_bit_mode = <0x15>;
};
+ tvafe {
+ compatible = "amlogic, tvafe-tm2";
+ /*memory-region = <&tvafe_cma_reserved>;*/
+ status = "okay";
+ flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
+ cma_size = <5>;/*MByte*/
+ reg = <0xff654000 0x2000>;/*tvafe reg base*/
+ reserve-iomap = "true";
+ tvafe_id = <0>;
+ //pinctrl-names = "default";
+ /*!!particular sequence, no more and no less!!!*/
+ tvafe_pin_mux = <
+ 3 /* TVAFE_CVBS_IN2, CVBS_IN0 = 0 */
+ 1 /* TVAFE_CVBS_IN0, CVBS_IN1 */
+ 2 /* TVAFE_CVBS_IN1, CVBS_IN2 */
+ 4 /* TVAFE_CVBS_IN3, CVBS_IN3 */
+ >;
+ clocks = <&clkc CLKID_DAC_CLK>;
+ clock-names = "vdac_clk_gate";
+ };
+
+ vbi {
+ compatible = "amlogic, vbi";
+ status = "okay";
+ interrupts = <0 83 1>;
+ };
+
+ cvbsout {
+ compatible = "amlogic, cvbsout-tm2";
+ status = "disabled";
+ clocks = <&clkc CLKID_VCLK2_ENCI
+ &clkc CLKID_VCLK2_VENCI0
+ &clkc CLKID_VCLK2_VENCI1
+ &clkc CLKID_DAC_CLK>;
+ clock-names = "venci_top_gate",
+ "venci_0_gate",
+ "venci_1_gate",
+ "vdac_clk_gate";
+ /* clk path */
+ /* 0:vid_pll vid2_clk */
+ /* 1:gp0_pll vid2_clk */
+ /* 2:vid_pll vid1_clk */
+ /* 3:gp0_pll vid1_clk */
+ clk_path = <0>;
+
+ /* performance: reg_address, reg_value */
+ /* tm2 */
+ performance = <0x1bf0 0x9
+ 0x1b56 0x333
+ 0x1b12 0x8080
+ 0x1b05 0xfd
+ 0x1c59 0xf850
+ 0xffff 0x0>; /* ending flag */
+ performance_sarft = <0x1bf0 0x9
+ 0x1b56 0x333
+ 0x1b12 0x0
+ 0x1b05 0x9
+ 0x1c59 0xfc48
+ 0xffff 0x0>; /* ending flag */
+ performance_revB_telecom = <0x1bf0 0x9
+ 0x1b56 0x546
+ 0x1b12 0x8080
+ 0x1b05 0x9
+ 0x1c59 0xf850
+ 0xffff 0x0>; /* ending flag */
+ };
+
hdmirx {
compatible = "amlogic, hdmirx_tl1";
#address-cells=<1>;
};
tvafe_avin_detect {
- compatible = "amlogic, tl1_tvafe_avin_detect";
+ compatible = "amlogic, tm2_tvafe_avin_detect";
status = "okay";
device_mask = <1>;/*bit0:ch1;bit1:ch2*/
interrupts = <0 12 1>,
};
tvafe {
- compatible = "amlogic, tvafe-tl1";
+ compatible = "amlogic, tvafe-tm2";
/*memory-region = <&tvafe_cma_reserved>;*/
status = "okay";
flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
};
cvbsout {
- compatible = "amlogic, cvbsout-tl1";
+ compatible = "amlogic, cvbsout-tm2";
status = "disabled";
clocks = <&clkc CLKID_VCLK2_ENCI
&clkc CLKID_VCLK2_VENCI0
clk_path = <0>;
/* performance: reg_address, reg_value */
- /* tl1 */
+ /* tm2 */
performance = <0x1bf0 0x9
0x1b56 0x333
0x1b12 0x8080
};
tvafe_avin_detect {
- compatible = "amlogic, tl1_tvafe_avin_detect";
+ compatible = "amlogic, tm2_tvafe_avin_detect";
status = "okay";
device_mask = <1>;/*bit0:ch1;bit1:ch2*/
interrupts = <0 12 1>,
};
tvafe {
- compatible = "amlogic, tvafe-tl1";
+ compatible = "amlogic, tvafe-tm2";
/*memory-region = <&tvafe_cma_reserved>;*/
status = "okay";
flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
};
cvbsout {
- compatible = "amlogic, cvbsout-tl1";
+ compatible = "amlogic, cvbsout-tm2";
status = "disabled";
clocks = <&clkc CLKID_VCLK2_ENCI
&clkc CLKID_VCLK2_VENCI0
clk_path = <0>;
/* performance: reg_address, reg_value */
- /* tl1 */
+ /* tm2 */
performance = <0x1bf0 0x9
0x1b56 0x333
0x1b12 0x8080
};
tvafe_avin_detect {
- compatible = "amlogic, tl1_tvafe_avin_detect";
+ compatible = "amlogic, tm2_tvafe_avin_detect";
status = "okay";
device_mask = <1>;/*bit0:ch1;bit1:ch2*/
interrupts = <0 12 1>,
};
tvafe {
- compatible = "amlogic, tvafe-tl1";
+ compatible = "amlogic, tvafe-tm2";
/*memory-region = <&tvafe_cma_reserved>;*/
status = "okay";
flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
};
cvbsout {
- compatible = "amlogic, cvbsout-tl1";
+ compatible = "amlogic, cvbsout-tm2";
status = "disabled";
clocks = <&clkc CLKID_VCLK2_ENCI
&clkc CLKID_VCLK2_VENCI0
clk_path = <0>;
/* performance: reg_address, reg_value */
- /* tl1 */
+ /* tm2 */
performance = <0x1bf0 0x9
0x1b56 0x333
0x1b12 0x8080
};
tvafe_avin_detect {
- compatible = "amlogic, tl1_tvafe_avin_detect";
+ compatible = "amlogic, tm2_tvafe_avin_detect";
status = "okay";
device_mask = <1>;/*bit0:ch1;bit1:ch2*/
interrupts = <0 12 1>,
};
tvafe {
- compatible = "amlogic, tvafe-tl1";
+ compatible = "amlogic, tvafe-tm2";
/*memory-region = <&tvafe_cma_reserved>;*/
status = "okay";
flag_cma = <1>;/*1:share with codec_mm;0:cma alone*/
};
cvbsout {
- compatible = "amlogic, cvbsout-tl1";
+ compatible = "amlogic, cvbsout-tm2";
status = "disabled";
clocks = <&clkc CLKID_VCLK2_ENCI
&clkc CLKID_VCLK2_VENCI0
clk_path = <0>;
/* performance: reg_address, reg_value */
- /* tl1 */
+ /* tm2 */
performance = <0x1bf0 0x9
0x1b56 0x333
0x1b12 0x8080
#ifdef CONFIG_AMLOGIC_MEDIA_TVIN_AVDETECT
/*only txlx chip enabled*/
if (tvafe_cpu_type() == CPU_TYPE_TXLX ||
- tvafe_cpu_type() == CPU_TYPE_TL1) {
+ tvafe_cpu_type() == CPU_TYPE_TL1 ||
+ tvafe_cpu_type() == CPU_TYPE_TM2) {
/*synctip set to 0 when tvafe working&&av connected*/
/*enable clamp if av connected*/
if (port == TVIN_PORT_CVBS1) {
#ifdef CONFIG_AMLOGIC_MEDIA_TVIN_AVDETECT
if (tvafe_cpu_type() == CPU_TYPE_TXLX ||
- tvafe_cpu_type() == CPU_TYPE_TL1) {
+ tvafe_cpu_type() == CPU_TYPE_TL1 ||
+ tvafe_cpu_type() == CPU_TYPE_TM2) {
if (port == TVIN_PORT_CVBS1)
tvafe_avin_detect_ch1_anlog_enable(0);
else if (port == TVIN_PORT_CVBS2)
}
#ifdef CONFIG_AMLOGIC_MEDIA_TVIN_AVDETECT
if (tvafe_cpu_type() == CPU_TYPE_TXLX ||
- tvafe_cpu_type() == CPU_TYPE_TL1) {
+ tvafe_cpu_type() == CPU_TYPE_TL1 ||
+ tvafe_cpu_type() == CPU_TYPE_TM2) {
if (port == TVIN_PORT_CVBS1)
tvafe_avin_detect_ch1_anlog_enable(1);
else if (port == TVIN_PORT_CVBS2)
#endif
#ifdef CONFIG_AMLOGIC_MEDIA_TVIN_AVDETECT
if (tvafe_cpu_type() == CPU_TYPE_TXLX ||
- tvafe_cpu_type() == CPU_TYPE_TL1) {
+ tvafe_cpu_type() == CPU_TYPE_TL1 ||
+ tvafe_cpu_type() == CPU_TYPE_TM2) {
/*avsync tip set 1 to resume av detect*/
if (tvafe->parm.port == TVIN_PORT_CVBS1) {
avport_opened = 0;
.name = "meson-tl1-tvafe",
};
+struct meson_tvafe_data meson_tm2_tvafe_data = {
+ .cpu_id = CPU_TYPE_TM2,
+ .name = "meson-tm2-tvafe",
+};
+
static const struct of_device_id meson_tvafe_dt_match[] = {
{
.compatible = "amlogic, tvafe-gxtvbb",
}, {
.compatible = "amlogic, tvafe-tl1",
.data = &meson_tl1_tvafe_data,
+ }, {
+ .compatible = "amlogic, tvafe-tm2",
+ .data = &meson_tm2_tvafe_data,
},
{},
};
.name = "meson-tl1-avin-detect",
};
+struct meson_avin_data tm2_data = {
+ .cpu_id = AVIN_CPU_TYPE_TM2,
+ .name = "meson-tm2-avin-detect",
+};
+
static const struct of_device_id tvafe_avin_dt_match[] = {
{ .compatible = "amlogic, tvafe_avin_detect",
},
{ .compatible = "amlogic, tl1_tvafe_avin_detect",
.data = &tl1_data,
},
+ { .compatible = "amlogic, tm2_tvafe_avin_detect",
+ .data = &tm2_data,
+ },
{},
};
#else
AVIN_CPU_TYPE_TXLX = 1,
AVIN_CPU_TYPE_TXHD = 2,
AVIN_CPU_TYPE_TL1 = 3,
+ AVIN_CPU_TYPE_TM2 = 4,
AVIN_CPU_TYPE_MAX,
};
/*setting for txhd snow*/
if (tvafe_get_snow_cfg() &&
(tvafe_cpu_type() == CPU_TYPE_TXHD ||
- tvafe_cpu_type() == CPU_TYPE_TL1)) {
+ tvafe_cpu_type() == CPU_TYPE_TL1 ||
+ tvafe_cpu_type() == CPU_TYPE_TM2)) {
W_APB_BIT(CVD2_OUTPUT_CONTROL, 3, 5, 2);
W_APB_REG(ACD_REG_6C, 0x80500000);
}
{
if (tvafe_snow_function_flag == 0 ||
tvafe_cpu_type() == CPU_TYPE_TXHD ||
- tvafe_cpu_type() == CPU_TYPE_TL1)
+ tvafe_cpu_type() == CPU_TYPE_TL1 ||
+ tvafe_cpu_type() == CPU_TYPE_TM2)
return;
if (onoff)
W_APB_BIT(CVD2_OUTPUT_CONTROL, 3, BLUE_MODE_BIT, BLUE_MODE_WID);
void tvafe_snow_config_clamp(unsigned int onoff)
{
if (tvafe_cpu_type() == CPU_TYPE_TXHD ||
- tvafe_cpu_type() == CPU_TYPE_TL1) {
+ tvafe_cpu_type() == CPU_TYPE_TL1 ||
+ tvafe_cpu_type() == CPU_TYPE_TM2) {
if (onoff)
vdin_adjust_tvafesnow_brightness();
return;
if (tvafe_cpu_type() == CPU_TYPE_TXL ||
tvafe_cpu_type() == CPU_TYPE_TXLX ||
tvafe_cpu_type() == CPU_TYPE_TXHD ||
- tvafe_cpu_type() == CPU_TYPE_TL1) {
+ tvafe_cpu_type() >= CPU_TYPE_TL1) {
tvafe_pr_info("[tvafe]%s:pin:%d\n",
__func__, (unsigned int)pin);
if (pin == TVAFE_CVBS_IN0) {
W_APB_BIT(TVFE_VAFE_CTRL1, 1,
VAFE_IN_SEL_BIT, VAFE_IN_SEL_WID);
- if (tvafe_cpu_type() != CPU_TYPE_TL1)
+ if (tvafe_cpu_type() < CPU_TYPE_TL1)
W_APB_BIT(TVFE_VAFE_CTRL2, 3, 4, 3);
ret = TVAFE_ADC_CH_0;
W_APB_BIT(TVFE_VAFE_CTRL1, 2,
VAFE_IN_SEL_BIT, VAFE_IN_SEL_WID);
- if (tvafe_cpu_type() != CPU_TYPE_TL1)
+ if (tvafe_cpu_type() < CPU_TYPE_TL1)
W_APB_BIT(TVFE_VAFE_CTRL2, 5, 4, 3);
ret = TVAFE_ADC_CH_1;
unsigned int i = 0;
/**disable auto mode clock**/
- if (tvafe_cpu_type() != CPU_TYPE_TL1)
+ if (tvafe_cpu_type() < CPU_TYPE_TL1)
W_HIU_REG(HHI_TVFE_AUTOMODE_CLK_CNTL, 0);
/*config adc*/
W_HIU_REG(HHI_DADC_CNTL, 0x00102038);
W_HIU_REG(HHI_DADC_CNTL2, 0x00000401);
W_HIU_REG(HHI_DADC_CNTL3, 0x00082183);
- } else if (tvafe_cpu_type() == CPU_TYPE_TL1) {
+ } else if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
/** DADC CNTL for LIF signal input **/
W_HIU_REG(HHI_DADC_CNTL, 0x0030303c);
W_HIU_REG(HHI_DADC_CNTL2, 0x00003480);
W_HIU_REG(HHI_DADC_CNTL, 0x00102038);
W_HIU_REG(HHI_DADC_CNTL2, 0x00000400);
W_HIU_REG(HHI_DADC_CNTL3, 0x00082183);
- } else if (tvafe_cpu_type() == CPU_TYPE_TL1) {
+ } else if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
W_HIU_REG(HHI_DADC_CNTL, 0x0030303c);
W_HIU_REG(HHI_DADC_CNTL2, 0x00003400);
W_HIU_REG(HHI_DADC_CNTL3, 0x08300b83);
if (tvafe_cpu_type() == CPU_TYPE_TXL ||
tvafe_cpu_type() == CPU_TYPE_TXLX ||
tvafe_cpu_type() == CPU_TYPE_TXHD ||
- tvafe_cpu_type() == CPU_TYPE_TL1) {
- if (tvafe_cpu_type() == CPU_TYPE_TL1) {
+ tvafe_cpu_type() >= CPU_TYPE_TL1) {
+ if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
if (port == TVIN_PORT_CVBS3) {
W_APB_REG(TVFE_VAFE_CTRL0, 0x000d0710);
W_APB_REG(TVFE_VAFE_CTRL1, 0x00003000);
W_APB_REG(TVFE_VAFE_CTRL0, 0x000d0710);
W_APB_REG(TVFE_VAFE_CTRL1, 0x0);
W_APB_REG(TVFE_VAFE_CTRL2, 0x1010eeb0);
- } else if (tvafe_cpu_type() == CPU_TYPE_TL1) {
+ } else if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
W_APB_REG(TVFE_VAFE_CTRL0, 0x000d0710);
W_APB_REG(TVFE_VAFE_CTRL1, 0x3000);
W_APB_REG(TVFE_VAFE_CTRL2, 0x1fe09e31);
if (tvafe_cpu_type() == CPU_TYPE_TXL ||
tvafe_cpu_type() == CPU_TYPE_TXLX ||
tvafe_cpu_type() == CPU_TYPE_TXHD ||
- tvafe_cpu_type() == CPU_TYPE_TL1) {
+ tvafe_cpu_type() >= CPU_TYPE_TL1) {
if (enable) {
tvafe_clk_gate_ctrl(1);
if (port == TVIN_PORT_CVBS3) {
break;
}
mutex_lock(&pll_mutex);
- if (tvafe_cpu_type() == CPU_TYPE_TL1) {
+ if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
do {
W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x012004e0);
W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x312004e0);
break;
}
mutex_lock(&pll_mutex);
- if (tvafe_cpu_type() == CPU_TYPE_TL1) {
+ if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
do {
W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x012004e0);
W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x312004e0);
break;
}
mutex_lock(&pll_mutex);
- if (tvafe_cpu_type() == CPU_TYPE_TL1) {
+ if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
do {
W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x012004e0);
W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x312004e0);
W_HIU_REG(HHI_DEMOD_CLK_CNTL, 0x1000502);
adc_pll_lock_cnt = 1;
- } else if (tvafe_cpu_type() == CPU_TYPE_TL1) {
+ } else if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
do {//25M
W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x001104c8);
W_HIU_REG(HHI_ADC_PLL_CNTL0_TL1, 0x301104c8);
if ((port >= TVIN_PORT_CVBS0) && (port <= TVIN_PORT_CVBS3)) {
#ifdef CRYSTAL_25M
- if (tvafe_cpu_type() != CPU_TYPE_TL1)
+ if (tvafe_cpu_type() < CPU_TYPE_TL1)
W_HIU_REG(HHI_VAFE_CLKIN_CNTL, 0x703);/* can't write !!! */
#endif
/* enable */
/* main clk up */
- if (tvafe_cpu_type() == CPU_TYPE_TL1) {
+ if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
W_HIU_BIT(HHI_ATV_DMD_SYS_CLK_CNTL, 1,
VAFE_CLK_SELECT, VAFE_CLK_SELECT_WIDTH);
W_HIU_BIT(HHI_ATV_DMD_SYS_CLK_CNTL, 1,
TVFE_ADC_CLK_DIV_WID);
/* main clk down */
- if (tvafe_cpu_type() == CPU_TYPE_TL1) {
+ if (tvafe_cpu_type() >= CPU_TYPE_TL1) {
W_HIU_BIT(HHI_ATV_DMD_SYS_CLK_CNTL, 0,
VAFE_CLK_SELECT, VAFE_CLK_SELECT_WIDTH);
W_HIU_BIT(HHI_ATV_DMD_SYS_CLK_CNTL, 0,
CPU_TYPE_TXHD = 3,
CPU_TYPE_GXLX = 4,
CPU_TYPE_TL1 = 5,
+ CPU_TYPE_TM2 = 6,
};
struct meson_tvafe_data {
VDIN_MATRIX_COEF_INDEX_BIT, VDIN_MATRIX_COEF_INDEX_WID);
wr(offset,
- VDIN_MATRIX_PRE_OFFSET0_1, matrix_tbl->pre_offset0_1);
+ VDIN_HDR2_MATRIXI_PRE_OFFSET0_1,
+ matrix_tbl->pre_offset0_1);
wr(offset,
- VDIN_MATRIX_PRE_OFFSET2, matrix_tbl->pre_offset2);
+ VDIN_HDR2_MATRIXI_PRE_OFFSET2, matrix_tbl->pre_offset2);
wr(offset, VDIN_HDR2_MATRIXI_COEF00_01, matrix_tbl->coef00_01);
wr(offset, VDIN_HDR2_MATRIXI_COEF02_10, matrix_tbl->coef02_10);
wr(offset, VDIN_HDR2_MATRIXI_COEF11_12, matrix_tbl->coef11_12);
.name = "meson-sm1-cvbsout",
};
+struct meson_cvbsout_data meson_tm2_cvbsout_data = {
+ .cntl0_val = 0x906001,
+ .cpu_id = CVBS_CPU_TYPE_TM2,
+ .name = "meson-tm2-cvbsout",
+};
+
static const struct of_device_id meson_cvbsout_dt_match[] = {
{
.compatible = "amlogic, cvbsout-gxl",
}, {
.compatible = "amlogic, cvbsout-sm1",
.data = &meson_sm1_cvbsout_data,
+ }, {
+ .compatible = "amlogic, cvbsout-tm2",
+ .data = &meson_tm2_cvbsout_data,
},
{},
};
CVBS_CPU_TYPE_G12B = 5,
CVBS_CPU_TYPE_TL1 = 6,
CVBS_CPU_TYPE_SM1 = 7,
+ CVBS_CPU_TYPE_TM2 = 8,
};
struct meson_cvbsout_data {
}
if (ret)
pr_info("[error]:hdmi_pll lock failed\n");
- } else if (cvbs_cpu_type() == CVBS_CPU_TYPE_TL1) {
+ } else if (cvbs_cpu_type() == CVBS_CPU_TYPE_TL1 ||
+ cvbs_cpu_type() == CVBS_CPU_TYPE_TM2) {
cvbs_out_hiu_write(HHI_TCON_PLL_CNTL0, 0x202f04f7);
udelay(100);
cvbs_out_hiu_write(HHI_TCON_PLL_CNTL0, 0x302f04f7);
cvbs_set_vid1_clk(cvbs_clk_path & 0x1);
else
cvbs_set_vid2_clk(cvbs_clk_path & 0x1);
- } else if (cvbs_cpu_type() == CVBS_CPU_TYPE_TL1) {
+ } else if (cvbs_cpu_type() == CVBS_CPU_TYPE_TL1 ||
+ cvbs_cpu_type() == CVBS_CPU_TYPE_TM2) {
if (cvbs_clk_path & 0x2)
cvbs_set_vid1_clk(0);
else
break;
vdac_out_cntl1_bit3(0, VDAC_MODULE_TVAFE);
vdac_out_cntl0_bit10(1, VDAC_MODULE_TVAFE);
- if (s_vdac_data->cpu_id == VDAC_CPU_TL1) {
+ if (s_vdac_data->cpu_id == VDAC_CPU_TL1 ||
+ s_vdac_data->cpu_id == VDAC_CPU_TM2) {
/*[6][8]bypass buffer enable*/
vdac_hiu_reg_setb(HHI_VDAC_CNTL1_G12A, 1, 6, 1);
vdac_hiu_reg_setb(HHI_VDAC_CNTL1_G12A, 1, 8, 1);
}
} else {
ana_ref_cntl0_bit9(0, VDAC_MODULE_TVAFE);
- if (s_vdac_data->cpu_id == VDAC_CPU_TL1) {
+ if (s_vdac_data->cpu_id == VDAC_CPU_TL1 ||
+ s_vdac_data->cpu_id == VDAC_CPU_TM2) {
/*[6][8]bypass buffer disable*/
vdac_hiu_reg_setb(HHI_VDAC_CNTL1_G12A, 0, 6, 1);
vdac_hiu_reg_setb(HHI_VDAC_CNTL1_G12A, 0, 8, 1);
.name = "meson-sm1-vdac",
};
+struct meson_vdac_data meson_tm2_vdac_data = {
+ .cpu_id = VDAC_CPU_TM2,
+ .name = "meson-tm2-vdac",
+};
+
static const struct of_device_id meson_vdac_dt_match[] = {
{
.compatible = "amlogic, vdac-gxtvbb",
}, {
.compatible = "amlogic, vdac-sm1",
.data = &meson_sm1_vdac_data,
+ }, {
+ .compatible = "amlogic, vdac-tm2",
+ .data = &meson_tm2_vdac_data,
},
{},
};
if (s_vdac_data->cpu_id == VDAC_CPU_TXL ||
s_vdac_data->cpu_id == VDAC_CPU_TXLX)
vdac_hiu_reg_write(HHI_VDAC_CNTL0, 0);
- else if (s_vdac_data->cpu_id == VDAC_CPU_TL1)
+ else if (s_vdac_data->cpu_id == VDAC_CPU_TL1 ||
+ s_vdac_data->cpu_id == VDAC_CPU_TM2)
vdac_hiu_reg_setb(HHI_VDAC_CNTL1_G12A, 1, 7, 1);
pr_info("%s: suspend module\n", __func__);
return 0;
static int amvdac_drv_resume(struct platform_device *pdev)
{
/*0xbc[7] for bandgap enable: 0:enable,1:disable*/
- if (s_vdac_data->cpu_id == VDAC_CPU_TL1)
+ if (s_vdac_data->cpu_id == VDAC_CPU_TL1 ||
+ s_vdac_data->cpu_id == VDAC_CPU_TM2)
vdac_hiu_reg_setb(HHI_VDAC_CNTL1_G12A, 0, 7, 1);
pr_info("%s: resume module\n", __func__);
return 0;
VDAC_CPU_G12AB = 6,
VDAC_CPU_TL1 = 7,
VDAC_CPU_SM1 = 8,
+ VDAC_CPU_TM2 = 9,
VDAC_CPU_MAX,
};