enum pp_mp1_state mp1_state)
{
int ret = 0;
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
- if (is_support_sw_smu(adev)) {
- ret = smu_set_mp1_state(&adev->smu, mp1_state);
- } else if (adev->powerplay.pp_funcs &&
- adev->powerplay.pp_funcs->set_mp1_state) {
- ret = adev->powerplay.pp_funcs->set_mp1_state(
+ if (pp_funcs && pp_funcs->set_mp1_state) {
+ ret = pp_funcs->set_mp1_state(
adev->powerplay.pp_handle,
mp1_state);
}
{
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
void *pp_handle = adev->powerplay.pp_handle;
- struct smu_context *smu = &adev->smu;
- if (is_support_sw_smu(adev)) {
- return smu_mode2_reset(smu);
- } else {
- if (!pp_funcs || !pp_funcs->asic_reset_mode_2)
- return -ENOENT;
+ if (!pp_funcs || !pp_funcs->asic_reset_mode_2)
+ return -ENOENT;
- return pp_funcs->asic_reset_mode_2(pp_handle);
- }
+ return pp_funcs->asic_reset_mode_2(pp_handle);
}
int amdgpu_dpm_baco_reset(struct amdgpu_device *adev)
enum PP_SMC_POWER_PROFILE type,
bool en)
{
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
int ret = 0;
if (amdgpu_sriov_vf(adev))
return 0;
- if (is_support_sw_smu(adev))
- ret = smu_switch_power_profile(&adev->smu, type, en);
- else if (adev->powerplay.pp_funcs &&
- adev->powerplay.pp_funcs->switch_power_profile)
- ret = adev->powerplay.pp_funcs->switch_power_profile(
+ if (pp_funcs && pp_funcs->switch_power_profile)
+ ret = pp_funcs->switch_power_profile(
adev->powerplay.pp_handle, type, en);
return ret;
int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev,
uint32_t pstate)
{
+ const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
int ret = 0;
- if (is_support_sw_smu(adev))
- ret = smu_set_xgmi_pstate(&adev->smu, pstate);
- else if (adev->powerplay.pp_funcs &&
- adev->powerplay.pp_funcs->set_xgmi_pstate)
- ret = adev->powerplay.pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle,
+ if (pp_funcs && pp_funcs->set_xgmi_pstate)
+ ret = pp_funcs->set_xgmi_pstate(adev->powerplay.pp_handle,
pstate);
return ret;
int ret = 0;
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
void *pp_handle = adev->powerplay.pp_handle;
- struct smu_context *smu = &adev->smu;
- if (is_support_sw_smu(adev))
- ret = smu_set_df_cstate(smu, cstate);
- else if (pp_funcs &&
- pp_funcs->set_df_cstate)
+ if (pp_funcs && pp_funcs->set_df_cstate)
ret = pp_funcs->set_df_cstate(pp_handle, cstate);
return ret;
void *pp_handle = adev->powerplay.pp_handle;
const struct amd_pm_funcs *pp_funcs =
adev->powerplay.pp_funcs;
- struct smu_context *smu = &adev->smu;
int ret = 0;
- if (is_support_sw_smu(adev))
- ret = smu_enable_mgpu_fan_boost(smu);
- else if (pp_funcs && pp_funcs->enable_mgpu_fan_boost)
+ if (pp_funcs && pp_funcs->enable_mgpu_fan_boost)
ret = pp_funcs->enable_mgpu_fan_boost(pp_handle);
return ret;
struct pp_display_clock_request *clock_req);
int smu_display_disable_memory_clock_switch(struct smu_context *smu, bool disable_memory_clock_switch);
-int smu_set_xgmi_pstate(struct smu_context *smu,
+int smu_set_xgmi_pstate(void *handle,
uint32_t pstate);
int smu_set_azalia_d3_pme(struct smu_context *smu);
bool smu_mode1_reset_is_support(struct smu_context *smu);
int smu_mode1_reset(struct smu_context *smu);
-int smu_mode2_reset(struct smu_context *smu);
+int smu_mode2_reset(void *handle);
extern const struct amd_ip_funcs smu_ip_funcs;
enum amd_dpm_forced_level level,
enum amd_pp_task task_id,
bool lock_needed);
-int smu_switch_power_profile(struct smu_context *smu,
+int smu_switch_power_profile(void *handle,
enum PP_SMC_POWER_PROFILE type,
bool en);
int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
int smu_force_clk_levels(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t mask);
-int smu_set_mp1_state(struct smu_context *smu,
+int smu_set_mp1_state(void *handle,
enum pp_mp1_state mp1_state);
-int smu_set_df_cstate(struct smu_context *smu,
+int smu_set_df_cstate(void *handle,
enum pp_df_cstate state);
int smu_allow_xgmi_power_down(struct smu_context *smu, bool en);
ssize_t smu_sys_get_gpu_metrics(struct smu_context *smu, void **table);
-int smu_enable_mgpu_fan_boost(struct smu_context *smu);
+int smu_enable_mgpu_fan_boost(void *handle);
int smu_gfx_state_change_set(struct smu_context *smu, uint32_t state);
#endif
return ret;
}
-int smu_switch_power_profile(struct smu_context *smu,
+int smu_switch_power_profile(void *handle,
enum PP_SMC_POWER_PROFILE type,
bool en)
{
+ struct smu_context *smu = handle;
struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
long workload;
uint32_t index;
* However, the mp1 state setting should still be granted
* even if the dpm_enabled cleared.
*/
-int smu_set_mp1_state(struct smu_context *smu,
+int smu_set_mp1_state(void *handle,
enum pp_mp1_state mp1_state)
{
+ struct smu_context *smu = handle;
uint16_t msg;
int ret;
return ret;
}
-int smu_set_df_cstate(struct smu_context *smu,
+int smu_set_df_cstate(void *handle,
enum pp_df_cstate state)
{
+ struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return ret;
}
-int smu_set_xgmi_pstate(struct smu_context *smu,
+int smu_set_xgmi_pstate(void *handle,
uint32_t pstate)
{
+ struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
return ret;
}
-int smu_mode2_reset(struct smu_context *smu)
+int smu_mode2_reset(void *handle)
{
+ struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled)
return size;
}
-int smu_enable_mgpu_fan_boost(struct smu_context *smu)
+int smu_enable_mgpu_fan_boost(void *handle)
{
+ struct smu_context *smu = handle;
int ret = 0;
if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
}
static const struct amd_pm_funcs swsmu_pm_funcs = {
+ /* export for sysfs */
.get_performance_level = smu_get_performance_level,
+ .switch_power_profile = smu_switch_power_profile,
+ /* export to amdgpu */
+ .set_mp1_state = smu_set_mp1_state,
+ /* export to DC */
+ .enable_mgpu_fan_boost = smu_enable_mgpu_fan_boost,
+ .asic_reset_mode_2 = smu_mode2_reset,
+ .set_df_cstate = smu_set_df_cstate,
+ .set_xgmi_pstate = smu_set_xgmi_pstate,
};