if (ret == 0)
ret = drm_intel_bo_mrb_exec(batch->bo, batch_end,
NULL, 0, 0, 0);
- assert(ret == 0);
+ igt_assert(ret == 0);
}
static uint32_t
batch_offset(batch, ss) + 4,
buf->bo, 0,
read_domain, write_domain);
- assert(ret == 0);
+ igt_assert(ret == 0);
ss->ss2.height = igt_buf_height(buf) - 1;
ss->ss2.width = igt_buf_width(buf) - 1;
curbe_buffer = gen7_fill_curbe_buffer_data(batch, color);
interface_descriptor = gen7_fill_interface_descriptor(batch, dst);
- assert(batch->ptr < &batch->buffer[4095]);
+ igt_assert(batch->ptr < &batch->buffer[4095]);
/* media pipeline */
batch->ptr = batch->buffer;
OUT_BATCH(MI_BATCH_BUFFER_END);
batch_end = batch_align(batch, 8);
- assert(batch_end < BATCH_STATE_SPLIT);
+ igt_assert(batch_end < BATCH_STATE_SPLIT);
gen7_render_flush(batch, batch_end);
intel_batchbuffer_reset(batch);
if (ret == 0)
ret = drm_intel_bo_mrb_exec(batch->bo, batch_end,
NULL, 0, 0, 0);
- assert(ret == 0);
+ igt_assert(ret == 0);
}
static uint32_t
batch_offset(batch, ss) + 8 * 4,
buf->bo, 0,
read_domain, write_domain);
- assert(ret == 0);
+ igt_assert(ret == 0);
ss->ss2.height = igt_buf_height(buf) - 1;
ss->ss2.width = igt_buf_width(buf) - 1;
curbe_buffer = gen8_fill_curbe_buffer_data(batch, color);
interface_descriptor = gen8_fill_interface_descriptor(batch, dst);
- assert(batch->ptr < &batch->buffer[4095]);
+ igt_assert(batch->ptr < &batch->buffer[4095]);
/* media pipeline */
batch->ptr = batch->buffer;
OUT_BATCH(MI_BATCH_BUFFER_END);
batch_end = batch_align(batch, 8);
- assert(batch_end < BATCH_STATE_SPLIT);
+ igt_assert(batch_end < BATCH_STATE_SPLIT);
gen8_render_flush(batch, batch_end);
intel_batchbuffer_reset(batch);
if (ret == 0)
ret = drm_intel_bo_mrb_exec(batch->bo, batch_end,
NULL, 0, 0, 0);
- assert(ret == 0);
+ igt_assert(ret == 0);
}
static uint32_t
batch_offset(batch, ss) + 8 * 4,
buf->bo, 0,
read_domain, write_domain);
- assert(ret == 0);
+ igt_assert(ret == 0);
ss->ss2.height = igt_buf_height(buf) - 1;
ss->ss2.width = igt_buf_width(buf) - 1;
curbe_buffer = gen8_fill_curbe_buffer_data(batch, color);
interface_descriptor = gen8_fill_interface_descriptor(batch, dst);
- assert(batch->ptr < &batch->buffer[4095]);
+ igt_assert(batch->ptr < &batch->buffer[4095]);
/* media pipeline */
batch->ptr = batch->buffer;
OUT_BATCH(MI_BATCH_BUFFER_END);
batch_end = batch_align(batch, 8);
- assert(batch_end < BATCH_STATE_SPLIT);
+ igt_assert(batch_end < BATCH_STATE_SPLIT);
gen8_render_flush(batch, batch_end);
intel_batchbuffer_reset(batch);
if (ret == 0)
ret = drm_intel_gem_bo_context_exec(batch->bo, context,
batch_end, 0);
- assert(ret == 0);
+ igt_assert(ret == 0);
}
static uint32_t
batch_offset(batch, ss) + 4,
buf->bo, 0,
read_domain, write_domain);
- assert(ret == 0);
+ igt_assert(ret == 0);
ss->ss2.height = igt_buf_height(buf) - 1;
ss->ss2.width = igt_buf_width(buf) - 1;
if (ret == 0)
ret = drm_intel_gem_bo_context_exec(batch->bo, context,
batch_end, 0);
- assert(ret == 0);
+ igt_assert(ret == 0);
}
static uint32_t
gen7_tiling_bits(uint32_t tiling)
{
switch (tiling) {
- default: assert(0);
+ default: igt_assert(0);
case I915_TILING_NONE: return 0;
case I915_TILING_X: return GEN7_SURFACE_TILED;
case I915_TILING_Y: return GEN7_SURFACE_TILED | GEN7_SURFACE_TILED_Y;
batch_offset(batch, ss) + 4,
buf->bo, 0,
read_domain, write_domain);
- assert(ret == 0);
+ igt_assert(ret == 0);
return batch_offset(batch, ss);
}
batch_end = batch->ptr - batch->buffer;
batch_end = ALIGN(batch_end, 8);
- assert(batch_end < BATCH_STATE_SPLIT);
+ igt_assert(batch_end < BATCH_STATE_SPLIT);
gen7_render_flush(batch, context, batch_end);
intel_batchbuffer_reset(batch);
uint32_t start_offset,
size_t size)
{
- assert(ctx->index < MAX_ANNOTATIONS);
+ igt_assert(ctx->index < MAX_ANNOTATIONS);
add_annotation(&ctx->annotations[ctx->index++],
AUB_TRACE_TYPE_NOTYPE, 0,
if (ret == 0)
ret = drm_intel_gem_bo_context_exec(batch->bo, context,
batch_end, 0);
- assert(ret == 0);
+ igt_assert(ret == 0);
}
/* Mostly copy+paste from gen6, except height, width, pitch moved */
batch_offset(batch, ss) + 8 * 4,
buf->bo, 0,
read_domain, write_domain);
- assert(ret == 0);
+ igt_assert(ret == 0);
ss->ss2.height = igt_buf_height(buf) - 1;
ss->ss2.width = igt_buf_width(buf) - 1;
scissor_state = gen6_create_scissor_rect(batch);
/* TODO: theree is other state which isn't setup */
- assert(batch->ptr < &batch->buffer[4095]);
+ igt_assert(batch->ptr < &batch->buffer[4095]);
batch->ptr = batch->buffer;
OUT_BATCH(MI_BATCH_BUFFER_END);
batch_end = batch_align(batch, 8);
- assert(batch_end < BATCH_STATE_SPLIT);
+ igt_assert(batch_end < BATCH_STATE_SPLIT);
annotation_add_batch(&aub_annotations, batch_end);
dump_batch(batch);