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x86: cacheinfo: disable L3 ECC scrubbing when L3 cache index is disabled
author
Mark Langsdorf
<mark.langsdorf@amd.com>
Thu, 9 Apr 2009 13:24:06 +0000
(15:24 +0200)
committer
Ingo Molnar
<mingo@elte.hu>
Fri, 10 Apr 2009 12:22:34 +0000
(14:22 +0200)
(Use correct mask to zero out bits 24-28 by Andreas)
Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
LKML-Reference: <
20090409132406
.GK31527@alberich.amd.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/kernel/cpu/intel_cacheinfo.c
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diff --git
a/arch/x86/kernel/cpu/intel_cacheinfo.c
b/arch/x86/kernel/cpu/intel_cacheinfo.c
index
fc28291
..
d46a849
100644
(file)
--- a/
arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/
arch/x86/kernel/cpu/intel_cacheinfo.c
@@
-731,6
+731,7
@@
static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
int node = cpu_to_node(cpu);
struct pci_dev *dev = node_to_k8_nb_misc(node);
unsigned long val = 0;
+ unsigned int scrubber = 0;
if (!this_leaf->can_disable)
return -EINVAL;
@@
-745,6
+746,11
@@
static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
return -EINVAL;
val |= 0xc0000000;
+
+ pci_read_config_dword(dev, 0x58, &scrubber);
+ scrubber &= ~0x1f000000;
+ pci_write_config_dword(dev, 0x58, scrubber);
+
pci_write_config_dword(dev, 0x1BC + index * 4, val & ~0x40000000);
wbinvd();
pci_write_config_dword(dev, 0x1BC + index * 4, val);