arm64: dts: sparx5: Add spi-nor support

This add spi-nor device nodes to the Sparx5 reference boards.

Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20200824203010.2033-6-lars.povlsen@microchip.com

diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
index 573309f..c1eb1d6 100644 (file)
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
@@ -39,6 +39,22 @@
        microchip,clock-delay = <10>;
 };
 
+&spi0 {
+       status = "okay";
+       spi@0 {
+               compatible = "spi-mux";
+               mux-controls = <&mux>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0>;      /* CS0 */
+               spi-flash@9 {
+                       compatible = "jedec,spi-nor";
+                       spi-max-frequency = <8000000>;
+                       reg = <0x9>;    /* SPI */
+               };
+       };
+};
+
 &i2c1 {
        status = "okay";
 };

diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
index 18a535a..f37b478 100644 (file)
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
@@ -38,6 +38,38 @@
        };
 };
 
+&spi0 {
+       status = "okay";
+       spi@0 {
+               compatible = "spi-mux";
+               mux-controls = <&mux>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0>;      /* CS0 */
+               spi-flash@9 {
+                       compatible = "jedec,spi-nor";
+                       spi-max-frequency = <8000000>;
+                       reg = <0x9>;    /* SPI */
+               };
+       };
+};
+
+&spi0 {
+       status = "okay";
+       spi@0 {
+               compatible = "spi-mux";
+               mux-controls = <&mux>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0>;      /* CS0 */
+               spi-flash@9 {
+                       compatible = "jedec,spi-nor";
+                       spi-max-frequency = <8000000>;
+                       reg = <0x9>;    /* SPI */
+               };
+       };
+};
+
 &gpio {
        i2cmux_pins_i: i2cmux-pins-i {
               pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19",

diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
index d71f11a..b02b8c8 100644 (file)
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi
@@ -51,6 +51,38 @@
        };
 };
 
+&spi0 {
+       status = "okay";
+       spi@0 {
+               compatible = "spi-mux";
+               mux-controls = <&mux>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0>; /* CS0 */
+               spi-flash@9 {
+                       compatible = "jedec,spi-nor";
+                       spi-max-frequency = <8000000>;
+                       reg = <0x9>; /* SPI */
+               };
+       };
+};
+
+&spi0 {
+       status = "okay";
+       spi@0 {
+               compatible = "spi-mux";
+               mux-controls = <&mux>;
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0>; /* CS0 */
+               spi-flash@9 {
+                       compatible = "jedec,spi-nor";
+                       spi-max-frequency = <8000000>;
+                       reg = <0x9>; /* SPI */
+               };
+       };
+};
+
 &axi {
        i2c0_imux: i2c0-imux@0 {
                compatible = "i2c-mux-pinctrl";