drm/vc4: hvs: Align the HVS atomic hooks to the new API

Since the CRTC setup in vc4 is split between the PixelValves/TXP and the
HVS, only the PV/TXP atomic hooks were updated in the previous commits, but
it makes sense to update the HVS ones too.

Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://patchwork.freedesktop.org/patch/msgid/20201215154243.540115-2-maxime@cerno.tech

diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 321f47b..8db8c01 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -647,7 +647,7 @@ static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
        struct drm_encoder *encoder;
        int ret, i;
 
-       ret = vc4_hvs_atomic_check(crtc, crtc_state);
+       ret = vc4_hvs_atomic_check(crtc, state);
        if (ret)
                return ret;
 

diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h
index 9997d22..5aaf289 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_drv.h
+++ b/drivers/gpu/drm/vc4/vc4_drv.h
@@ -925,11 +925,10 @@ void vc4_irq_reset(struct drm_device *dev);
 extern struct platform_driver vc4_hvs_driver;
 void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int output);
 int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output);
-int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
+int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state);
 void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state);
 void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state);
-void vc4_hvs_atomic_flush(struct drm_crtc *crtc,
-                         struct drm_atomic_state *state);
+void vc4_hvs_atomic_flush(struct drm_crtc *crtc, struct drm_atomic_state *state);
 void vc4_hvs_dump_state(struct drm_device *dev);
 void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel);
 void vc4_hvs_mask_underrun(struct drm_device *dev, int channel);

diff --git a/drivers/gpu/drm/vc4/vc4_hvs.c b/drivers/gpu/drm/vc4/vc4_hvs.c
index 3ceda2f..6049923 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_hvs.c
+++ b/drivers/gpu/drm/vc4/vc4_hvs.c
@@ -365,10 +365,10 @@ void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int chan)
                     SCALER_DISPSTATX_EMPTY);
 }
 
-int vc4_hvs_atomic_check(struct drm_crtc *crtc,
-                        struct drm_crtc_state *state)
+int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state)
 {
-       struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
+       struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+       struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
        struct drm_device *dev = crtc->dev;
        struct vc4_dev *vc4 = to_vc4_dev(dev);
        struct drm_plane *plane;
@@ -380,10 +380,10 @@ int vc4_hvs_atomic_check(struct drm_crtc *crtc,
        /* The pixelvalve can only feed one encoder (and encoders are
         * 1:1 with connectors.)
         */
-       if (hweight32(state->connector_mask) > 1)
+       if (hweight32(crtc_state->connector_mask) > 1)
                return -EINVAL;
 
-       drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
+       drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state)
                dlist_count += vc4_plane_dlist_size(plane_state);
 
        dlist_count++; /* Account for SCALER_CTL0_END. */

diff --git a/drivers/gpu/drm/vc4/vc4_txp.c b/drivers/gpu/drm/vc4/vc4_txp.c
index 2243064..79ecaaa 100644 (file)
--- a/drivers/gpu/drm/vc4/vc4_txp.c
+++ b/drivers/gpu/drm/vc4/vc4_txp.c
@@ -393,7 +393,7 @@ static int vc4_txp_atomic_check(struct drm_crtc *crtc,
        struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
        int ret;
 
-       ret = vc4_hvs_atomic_check(crtc, crtc_state);
+       ret = vc4_hvs_atomic_check(crtc, state);
        if (ret)
                return ret;