arm64: dts: qcom: sm8250: sort nodes by physical address

Other dts have nodes sorted by physical address, be consistent with that.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20200523132223.31108-1-jonathan@marek.ca
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 8d7e89e..d53878f 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -377,13 +377,9 @@
                        };
                };
 
-               intc: interrupt-controller@17a00000 {
-                       compatible = "arm,gic-v3";
-                       #interrupt-cells = <3>;
-                       interrupt-controller;
-                       reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
-                             <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
-                       interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+               tcsr_mutex_regs: syscon@1f40000 {
+                       compatible = "syscon";
+                       reg = <0x0 0x01f40000 0x0 0x40000>;
                };
 
                pdc: interrupt-controller@b220000 {
@@ -414,6 +410,74 @@
                        #interrupt-cells = <4>;
                };
 
+               intc: interrupt-controller@17a00000 {
+                       compatible = "arm,gic-v3";
+                       #interrupt-cells = <3>;
+                       interrupt-controller;
+                       reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */
+                             <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */
+                       interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               timer@17c20000 {
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+                       compatible = "arm,armv7-timer-mem";
+                       reg = <0x0 0x17c20000 0x0 0x1000>;
+                       clock-frequency = <19200000>;
+
+                       frame@17c21000 {
+                               frame-number = <0>;
+                               interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                               reg = <0x0 0x17c21000 0x0 0x1000>,
+                                     <0x0 0x17c22000 0x0 0x1000>;
+                       };
+
+                       frame@17c23000 {
+                               frame-number = <1>;
+                               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+                               reg = <0x0 0x17c23000 0x0 0x1000>;
+                               status = "disabled";
+                       };
+
+                       frame@17c25000 {
+                               frame-number = <2>;
+                               interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+                               reg = <0x0 0x17c25000 0x0 0x1000>;
+                               status = "disabled";
+                       };
+
+                       frame@17c27000 {
+                               frame-number = <3>;
+                               interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                               reg = <0x0 0x17c27000 0x0 0x1000>;
+                               status = "disabled";
+                       };
+
+                       frame@17c29000 {
+                               frame-number = <4>;
+                               interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+                               reg = <0x0 0x17c29000 0x0 0x1000>;
+                               status = "disabled";
+                       };
+
+                       frame@17c2b000 {
+                               frame-number = <5>;
+                               interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                               reg = <0x0 0x17c2b000 0x0 0x1000>;
+                               status = "disabled";
+                       };
+
+                       frame@17c2d000 {
+                               frame-number = <6>;
+                               interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+                               reg = <0x0 0x17c2d000 0x0 0x1000>;
+                               status = "disabled";
+                       };
+               };
+
                apps_rsc: rsc@18200000 {
                        label = "apps_rsc";
                        compatible = "qcom,rpmh-rsc";
@@ -486,71 +550,6 @@
                                };
                        };
                };
-
-               tcsr_mutex_regs: syscon@1f40000 {
-                       compatible = "syscon";
-                       reg = <0x0 0x01f40000 0x0 0x40000>;
-               };
-
-               timer@17c20000 {
-                       #address-cells = <2>;
-                       #size-cells = <2>;
-                       ranges;
-                       compatible = "arm,armv7-timer-mem";
-                       reg = <0x0 0x17c20000 0x0 0x1000>;
-                       clock-frequency = <19200000>;
-
-                       frame@17c21000 {
-                               frame-number = <0>;
-                               interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
-                                            <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
-                               reg = <0x0 0x17c21000 0x0 0x1000>,
-                                     <0x0 0x17c22000 0x0 0x1000>;
-                       };
-
-                       frame@17c23000 {
-                               frame-number = <1>;
-                               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
-                               reg = <0x0 0x17c23000 0x0 0x1000>;
-                               status = "disabled";
-                       };
-
-                       frame@17c25000 {
-                               frame-number = <2>;
-                               interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-                               reg = <0x0 0x17c25000 0x0 0x1000>;
-                               status = "disabled";
-                       };
-
-                       frame@17c27000 {
-                               frame-number = <3>;
-                               interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
-                               reg = <0x0 0x17c27000 0x0 0x1000>;
-                               status = "disabled";
-                       };
-
-                       frame@17c29000 {
-                               frame-number = <4>;
-                               interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
-                               reg = <0x0 0x17c29000 0x0 0x1000>;
-                               status = "disabled";
-                       };
-
-                       frame@17c2b000 {
-                               frame-number = <5>;
-                               interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
-                               reg = <0x0 0x17c2b000 0x0 0x1000>;
-                               status = "disabled";
-                       };
-
-                       frame@17c2d000 {
-                               frame-number = <6>;
-                               interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
-                               reg = <0x0 0x17c2d000 0x0 0x1000>;
-                               status = "disabled";
-                       };
-               };
-
        };
 
        timer {