arm64: dts: qcom: sc7280: Add pinmux for I2S speaker and Headset

Add pinmux nodes for primary and secondary I2S for SC7280 based platforms.

Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1655108645-1517-2-git-send-email-quic_srivasam@quicinc.com

diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 5eb6689..acf407a 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -367,6 +367,20 @@
        bias-disable;
 };
 
+&mi2s1_data0 {
+       drive-strength = <6>;
+       bias-disable;
+};
+
+&mi2s1_sclk {
+       drive-strength = <6>;
+       bias-disable;
+};
+
+&mi2s1_ws {
+       drive-strength = <6>;
+};
+
 &pm7325_gpios {
        key_vol_up_default: key-vol-up-default {
                pins = "gpio6";

diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 41da63e..046aee0 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -3893,6 +3893,46 @@
                                function = "edp_hot";
                        };
 
+                       mi2s0_data0: mi2s0-data0 {
+                               pins = "gpio98";
+                               function = "mi2s0_data0";
+                       };
+
+                       mi2s0_data1: mi2s0-data1 {
+                               pins = "gpio99";
+                               function = "mi2s0_data1";
+                       };
+
+                       mi2s0_mclk: mi2s0-mclk {
+                               pins = "gpio96";
+                               function = "pri_mi2s";
+                       };
+
+                       mi2s0_sclk: mi2s0-sclk {
+                               pins = "gpio97";
+                               function = "mi2s0_sck";
+                       };
+
+                       mi2s0_ws: mi2s0-ws {
+                               pins = "gpio100";
+                               function = "mi2s0_ws";
+                       };
+
+                       mi2s1_data0: mi2s1-data0 {
+                               pins = "gpio107";
+                               function = "mi2s1_data0";
+                       };
+
+                       mi2s1_sclk: mi2s1-sclk {
+                               pins = "gpio106";
+                               function = "mi2s1_sck";
+                       };
+
+                       mi2s1_ws: mi2s1-ws {
+                               pins = "gpio108";
+                               function = "mi2s1_ws";
+                       };
+
                        pcie1_clkreq_n: pcie1-clkreq-n {
                                pins = "gpio79";
                                function = "pcie1_clkreqn";