padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
if (!padcfg0) {
- dev_warn(vg->dev,
- "Group %s, pin %i not muxed (no padcfg0)\n",
+ dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n",
group.grp.name, i);
continue;
}
padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
if (!padcfg0) {
- dev_warn(vg->dev,
- "Group %s, pin %i not muxed (no padcfg0)\n",
+ dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n",
group.grp.name, i);
continue;
}
value |= gpio_mux;
writel(value, reg);
- dev_warn(vg->dev, FW_BUG "pin %u forcibly re-configured as GPIO\n", offset);
+ dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset);
}
raw_spin_unlock_irqrestore(&byt_lock, flags);
* themselves in the foot.
*/
if (readl(conf_reg) & BYT_DIRECT_IRQ_EN)
- dev_info_once(vg->dev, "Potential Error: Setting GPIO with direct_irq_en to output");
+ dev_info_once(vg->dev,
+ "Potential Error: Pin %i: forcibly set GPIO with DIRECT_IRQ_EN to output\n",
+ offset);
}
static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
if (val & BYT_INPUT_EN) {
val &= ~BYT_INPUT_EN;
writel(val, val_reg);
- dev_warn(vg->dev,
- "pin %u forcibly set to input mode\n",
- offset);
+ dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
}
conf &= ~BYT_PULL_ASSIGN_MASK;
if (val & BYT_INPUT_EN) {
val &= ~BYT_INPUT_EN;
writel(val, val_reg);
- dev_warn(vg->dev,
- "pin %u forcibly set to input mode\n",
- offset);
+ dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
}
conf &= ~BYT_PULL_ASSIGN_MASK;
pin = vg->soc->pins[i].number;
reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
if (!reg) {
- seq_printf(s,
- "Could not retrieve pin %i conf0 reg\n",
- pin);
+ seq_printf(s, "Pin %i: can't retrieve CONF0\n", pin);
raw_spin_unlock_irqrestore(&byt_lock, flags);
continue;
}
reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
if (!reg) {
- seq_printf(s,
- "Could not retrieve pin %i val reg\n", pin);
+ seq_printf(s, "Pin %i: can't retrieve VAL\n", pin);
raw_spin_unlock_irqrestore(&byt_lock, flags);
continue;
}
comm = byt_get_community(vg, pin);
if (!comm) {
- seq_printf(s,
- "Could not get community for pin %i\n", pin);
+ seq_printf(s, "Pin %i: can't retrieve community\n", pin);
continue;
}
label = gpiochip_is_requested(chip, i);
value = readl(reg);
WARN(value & BYT_DIRECT_IRQ_EN,
- "Bad pad config for io mode, force direct_irq_en bit clearing");
+ "Bad pad config for IO mode, force DIRECT_IRQ_EN bit clearing");
/* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
* are used to indicate high and low level triggering
reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
if (!reg) {
- dev_warn(vg->dev,
- "Pin %i: could not retrieve interrupt status register\n",
- base);
+ dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base);
continue;
}
sizeof(direct_irq_mux));
match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux));
if (!match) {
- dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set but no IRQ assigned, clearing\n", pin);
+ dev_warn(vg->dev, FW_BUG "Pin %i: DIRECT_IRQ_EN set but no IRQ assigned, clearing\n", pin);
return false;
}
trig = conf0 & BYT_TRIG_MASK;
if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) &&
trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) {
- dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set without trigger (conf0: %xh), clearing\n",
+ dev_warn(vg->dev,
+ FW_BUG "Pin %i: DIRECT_IRQ_EN set without trigger (CONF0: %#08x), clearing\n",
pin, conf0);
return false;
}
reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
if (!reg) {
- dev_warn(vg->dev,
- "Pin %i: could not retrieve conf0 register\n",
- i);
+ dev_warn(vg->dev, "Pin %i: could not retrieve CONF0\n", i);
continue;
}
reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
if (!reg) {
- dev_warn(vg->dev,
- "Pin %i: could not retrieve irq status reg\n",
- base);
+ dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base);
continue;
}
value = readl(reg);
if (value)
dev_err(vg->dev,
- "GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",
+ "GPIO interrupt error, pins misconfigured. INT_STAT%u: %#08x\n",
base / 32, value);
}
reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
if (!reg) {
- dev_warn(vg->dev,
- "Pin %i: could not retrieve conf0 register\n",
- i);
+ dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i);
continue;
}
value = readl(reg) & BYT_CONF0_RESTORE_MASK;
reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
if (!reg) {
- dev_warn(vg->dev,
- "Pin %i: could not retrieve conf0 register\n",
- i);
+ dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i);
continue;
}
value = readl(reg);
value &= ~BYT_CONF0_RESTORE_MASK;
value |= vg->context.pads[i].conf0;
writel(value, reg);
- dev_info(dev, "restored pin %d conf0 %#08x", i, value);
+ dev_info(dev, "restored pin %d CONF0 %#08x", i, value);
}
reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
v |= vg->context.pads[i].val;
if (v != value) {
writel(v, reg);
- dev_dbg(dev, "restored pin %d val %#08x\n",
- i, v);
+ dev_dbg(dev, "restored pin %d VAL %#08x\n", i, v);
}
}
}