drm/amd/display: Disable Stutter for Stereo 3D

[WHY]
Bandwidth calculation formulas currently do not take Stereo 3D + Stutter
properly into account. Disable stutter feature when we detect a Stereo
3D mode as a temporary workaround.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Martin Leung <Martin.Leung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
index 5a4614c..e161ad8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c
@@ -88,11 +88,18 @@ void hubbub1_wm_read_state(struct hubbub *hubbub,
        s->dram_clk_chanage = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D);
 }
 
-void hubbub1_disable_allow_self_refresh(struct hubbub *hubbub)
+void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow)
 {
        struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
-       REG_UPDATE(DCHUBBUB_ARB_DRAM_STATE_CNTL,
-                       DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, 0);
+
+       /*
+        * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 1 means do not allow stutter
+        * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0 means allow stutter
+        */
+
+       REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
+                       DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0,
+                       DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, !allow);
 }
 
 bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubbub)
@@ -262,8 +269,6 @@ void hubbub1_program_watermarks(
                bool safe_to_lower)
 {
        struct dcn10_hubbub *hubbub1 = TO_DCN10_HUBBUB(hubbub);
-
-       uint32_t force_en = hubbub1->base.ctx->dc->debug.disable_stutter ? 1 : 0;
        /*
         * Need to clamp to max of the register values (i.e. no wrap)
         * for dcn1, all wm registers are 21-bit wide
@@ -537,9 +542,7 @@ void hubbub1_program_watermarks(
        REG_UPDATE(DCHUBBUB_ARB_DF_REQ_OUTSTAND,
                        DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 68);
 
-       REG_UPDATE_2(DCHUBBUB_ARB_DRAM_STATE_CNTL,
-                       DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_VALUE, 0,
-                       DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE, force_en);
+       hubbub1_allow_self_refresh_control(hubbub, !hubbub->ctx->dc->debug.disable_stutter);
 
 #if 0
        REG_UPDATE_2(DCHUBBUB_ARB_WATERMARK_CHANGE_CNTL,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
index c681e1c..9cd4a51 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h
@@ -204,7 +204,7 @@ void hubbub1_program_watermarks(
                unsigned int refclk_mhz,
                bool safe_to_lower);
 
-void hubbub1_disable_allow_self_refresh(struct hubbub *hubbub);
+void hubbub1_allow_self_refresh_control(struct hubbub *hubbub, bool allow);
 
 bool hububu1_is_allow_self_refresh_enabled(struct hubbub *hubub);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 9f23ea2..7cead03 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -1011,7 +1011,7 @@ static void dcn10_init_hw(struct dc *dc)
                         */
                        if (allow_self_fresh_force_enable == false &&
                                        hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub))
-                               hubbub1_disable_allow_self_refresh(dc->res_pool->hubbub);
+                               hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, true);
 
                        disable_vga(dc->hwseq);
                }
@@ -2384,6 +2384,22 @@ static void dcn10_apply_ctx_for_surface(
                hubbub1_wm_change_req_wa(dc->res_pool->hubbub);
 }
 
+static void dcn10_stereo_hw_frame_pack_wa(struct dc *dc, struct dc_state *context)
+{
+       uint8_t i;
+
+       for (i = 0; i < context->stream_count; i++) {
+               if (context->streams[i]->timing.timing_3d_format
+                               == TIMING_3D_FORMAT_HW_FRAME_PACKING) {
+                       /*
+                        * Disable stutter
+                        */
+                       hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, false);
+                       break;
+               }
+       }
+}
+
 static void dcn10_prepare_bandwidth(
                struct dc *dc,
                struct dc_state *context)
@@ -2405,6 +2421,7 @@ static void dcn10_prepare_bandwidth(
                        &context->bw.dcn.watermarks,
                        dc->res_pool->ref_clock_inKhz / 1000,
                        true);
+       dcn10_stereo_hw_frame_pack_wa(dc, context);
 
        if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
                dcn_bw_notify_pplib_of_wm_ranges(dc);
@@ -2434,6 +2451,7 @@ static void dcn10_optimize_bandwidth(
                        &context->bw.dcn.watermarks,
                        dc->res_pool->ref_clock_inKhz / 1000,
                        true);
+       dcn10_stereo_hw_frame_pack_wa(dc, context);
 
        if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
                dcn_bw_notify_pplib_of_wm_ranges(dc);