ARM: exynos: Register CPU IO area for Exynos3

This patch map CPU IO area for Exynos3.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>

diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 291a7a0..3362fdb 100644 (file)
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -68,6 +68,7 @@ static const char name_exynos4412[] = "EXYNOS4412";
 static const char name_exynos5250[] = "EXYNOS5250";
 static const char name_exynos5440[] = "EXYNOS5440";
 
+static void exynos3_map_io(void);
 static void exynos4_map_io(void);
 static void exynos5_map_io(void);
 static void exynos5440_map_io(void);
@@ -80,6 +81,7 @@ static struct cpu_table cpu_ids[] __initdata = {
        {
                .idcode         = EXYNOS3250_SOC_ID,
                .idmask         = EXYNOS3_SOC_MASK,
+               .map_io         = exynos3_map_io,
                .init           = exynos_init,
                .name           = name_exynos3250,
        }, {
@@ -129,6 +131,75 @@ static struct map_desc exynos_iodesc[] __initdata = {
        },
 };
 
+static struct map_desc exynos3_iodesc[] __initdata = {
+       {
+               .virtual        = (unsigned long)S3C_VA_TIMER,
+               .pfn            = __phys_to_pfn(EXYNOS3_PA_TIMER),
+               .length         = SZ_16K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_WATCHDOG,
+               .pfn            = __phys_to_pfn(S3C_PA_WDT),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_SYS,
+               .pfn            = __phys_to_pfn(EXYNOS3_PA_SYSCON),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_SYSTIMER,
+               .pfn            = __phys_to_pfn(EXYNOS3_PA_SYSTIMER),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_SYSRAM,
+               .pfn            = __phys_to_pfn(EXYNOS3_PA_SYSRAM),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
+               .pfn            = __phys_to_pfn(EXYNOS3_PA_SYSRAM_NS),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_CMU,
+               .pfn            = __phys_to_pfn(EXYNOS3_PA_CMU_BUS_TOP),
+               .length         = SZ_128K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_PMU,
+               .pfn            = __phys_to_pfn(EXYNOS3_PA_PMU),
+               .length         = SZ_64K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S3C_VA_UART,
+               .pfn            = __phys_to_pfn(EXYNOS3_PA_UART),
+               .length         = SZ_512K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GIC_CPU,
+               .pfn            = __phys_to_pfn(EXYNOS3_PA_GIC_CPU),
+               .length         = SZ_8K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GIC_DIST,
+               .pfn            = __phys_to_pfn(EXYNOS3_PA_GIC_DIST),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       }, {
+               .virtual        = (unsigned long)S5P_VA_GPIO2,
+               .pfn            = __phys_to_pfn(EXYNOS3_PA_GPIO2),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },{
+               .virtual        = (unsigned long)S3C_VA_USB_HSPHY,
+               .pfn            = __phys_to_pfn(EXYNOS4_PA_HSPHY),
+               .length         = SZ_4K,
+               .type           = MT_DEVICE,
+       },
+};
+
 static struct map_desc exynos4_iodesc[] __initdata = {
        {
                .virtual        = (unsigned long)S3C_VA_SYS,
@@ -421,6 +492,11 @@ void __init exynos_init_io(struct map_desc *mach_desc, int size)
        s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
 }
 
+static void __init exynos3_map_io(void)
+{
+       iotable_init(exynos3_iodesc, ARRAY_SIZE(exynos3_iodesc));
+}
+
 static void __init exynos4_map_io(void)
 {
        iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));

diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 9d8a9b7..3296281 100644 (file)
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -23,6 +23,54 @@
 
 #include <plat/map-s5p.h>
 
+#define EXYNOS3_PA_SYSRAM               0x02020000
+#define EXYNOS3_PA_SYSRAM_NS            0x0205F000
+#define EXYNOS3_PA_CHIPID               0x10000000
+#define EXYNOS3_PA_SYSCON               0x10010000
+#define EXYNOS3_PA_CMU_BUS_TOP          0x10030000
+#define EXYNOS3_PA_CMU_CPU_ISP          0x10040000
+#define EXYNOS3_PA_CMU_ACP              0x10450000
+#define EXYNOS3_PA_CMU_DMC              0x105C0000
+
+#define EXYNOS3_PA_TIMER                0x139D0000
+#define EXYNOS3_PA_RTC                  0x10070000
+
+#define EXYNOS3_SYSREG                  0x10010000
+
+#define EXYNOS3_PA_PMU                  0x10020000
+#define EXYNOS3_PA_TMU                  0x100C0000
+
+#define EXYNOS3_PA_SYSTIMER             0x10050000
+
+#define EXYNOS3_PA_GIC_CPU              0x10482000
+#define EXYNOS3_PA_GIC_DIST             0x10481000
+
+#define EXYNOS3_PA_UART                 0x13800000
+
+#define EXYNOS3_PA_UART0                0x13800000
+#define EXYNOS3_PA_UART1                0x13810000
+#define EXYNOS3_PA_UART2                0x13820000
+#define EXYNOS3_PA_UART3                0x13830000
+#define EXYNOS3_SZ_UART                        SZ_256
+
+#define EXYNOS3_PA_GPIO1                0x11400000
+#define EXYNOS3_PA_GPIO2                0x11000000
+
+#define EXYNOS3_PA_WATCHDOG            0x10060000
+
+#define EXYNOS3_PA_IIC(x)               (0x13860000 + ((x) * 0x10000))
+
+#define EXYNOS3_PA_FIMD0               0x11c00000
+#define EXYNOS3_PA_DSIM0               0x11c80000
+
+#define EXYNOS3_PA_PDMA0                0x12680000
+#define EXYNOS3_PA_PDMA1                0x12690000
+#define EXYNOS3_PA_MDMA                        0x12840000
+
+#define EXYNOS3_PA_ADC                  0x126c0000
+
+#define EXYNOS3_PA_KEYPAD               0x100a0000
+
 #define EXYNOS4_PA_SYSRAM0             0x02025000
 #define EXYNOS4_PA_SYSRAM1             0x02020000
 #define EXYNOS5_PA_SYSRAM              0x02020000