i965/gen11: Fix must-be-ones bit positions in 3D_MODE

Fixes: f0d29238df3 ("i965/gen11: Emit SLICE_HASH_TABLE when pipes are unbalanced.")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9505>

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 10f8885..1816c38 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -144,7 +144,7 @@ brw_upload_gen11_slice_hashing_state(struct brw_context *brw)
     */
    BEGIN_BATCH(2);
    OUT_BATCH(_3DSTATE_3D_MODE  << 16 | (2 - 2));
-   OUT_BATCH(0xffff | SLICE_HASHING_TABLE_ENABLE);
+   OUT_BATCH(0xffff0000 | SLICE_HASHING_TABLE_ENABLE);
    ADVANCE_BATCH();
 }