arm64: dts: renesas: r9a07g043: Split out RZ/G2UL SoC specific parts

Move RZ/G2UL SoC specific parts to r9a07g043u.dtsi so that
r9a07g043.dtsi can be shared with RZ/Five (RISC-V SoC).

Below are the changes due to which SoC specific parts are moved to
r9a07g043u.dtsi:
  - RZ/G2UL has Cortex-A55 (ARM64) whereas RZ/Five has AX45MP (RISC-V),
  - RZ/G2UL has GICv3 as interrupt controller whereas RZ/Five has PLIC,
  - RZ/G2UL has interrupts for SYSC block whereas interrupts are missing
    for SYSC block on RZ/Five,
  - RZ/G2UL has armv8-timer whereas RZ/Five has riscv-timer,
  - RZ/G2UL has PSCI whereas RZ/Five have OpenSBI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20221025220629.79321-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index a7248204d2ba4f82884410453acd1c79c27b5300..3f7d451b119953bbc7af8e3b08adf54a13ecc859 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 /*
- * Device Tree Source for the RZ/G2UL SoC
+ * Device Tree Source for the RZ/Five and RZ/G2UL SoCs
  *
  * Copyright (C) 2022 Renesas Electronics Corp.
  */
@@ -68,36 +68,8 @@
                };
        };
 
-       cpus {
-               #address-cells = <1>;
-               #size-cells = <0>;
-
-               cpu0: cpu@0 {
-                       compatible = "arm,cortex-a55";
-                       reg = <0>;
-                       device_type = "cpu";
-                       #cooling-cells = <2>;
-                       next-level-cache = <&L3_CA55>;
-                       enable-method = "psci";
-                       clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
-                       operating-points-v2 = <&cluster0_opp>;
-               };
-
-               L3_CA55: cache-controller-0 {
-                       compatible = "cache";
-                       cache-unified;
-                       cache-size = <0x40000>;
-               };
-       };
-
-       psci {
-               compatible = "arm,psci-1.0", "arm,psci-0.2";
-               method = "smc";
-       };
-
        soc: soc {
                compatible = "simple-bus";
-               interrupt-parent = <&gic>;
                #address-cells = <2>;
                #size-cells = <2>;
                ranges;
@@ -550,12 +522,6 @@
                sysc: system-controller@11020000 {
                        compatible = "renesas,r9a07g043-sysc";
                        reg = <0 0x11020000 0 0x10000>;
-                       interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>,
-                                    <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>,
-                                    <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>,
-                                    <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
-                       interrupt-names = "lpm_int", "ca55stbydone_int",
-                                         "cm33stbyr_int", "ca55_deny";
                        status = "disabled";
                };
 
@@ -608,16 +574,6 @@
                        dma-channels = <16>;
                };
 
-               gic: interrupt-controller@11900000 {
-                       compatible = "arm,gic-v3";
-                       #interrupt-cells = <3>;
-                       #address-cells = <0>;
-                       interrupt-controller;
-                       reg = <0x0 0x11900000 0 0x40000>,
-                             <0x0 0x11940000 0 0x60000>;
-                       interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
-               };
-
                sdhi0: mmc@11c00000 {
                        compatible = "renesas,sdhi-r9a07g043",
                                     "renesas,rcar-gen3-sdhi";
@@ -883,12 +839,4 @@
                        };
                };
        };
-
-       timer {
-               compatible = "arm,armv8-timer";
-               interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
-                                     <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
-       };
 };

diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
index 96f935bc2d4d1b5f4096724aac60935c9b4cc660..b8bf06b5123514eeb36ee776b1896aa20d316da7 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi
@@ -10,3 +10,63 @@
 #define SOC_PERIPHERAL_IRQ(nr)         GIC_SPI nr
 
 #include "r9a07g043.dtsi"
+
+/ {
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu0: cpu@0 {
+                       compatible = "arm,cortex-a55";
+                       reg = <0>;
+                       device_type = "cpu";
+                       #cooling-cells = <2>;
+                       next-level-cache = <&L3_CA55>;
+                       enable-method = "psci";
+                       clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
+                       operating-points-v2 = <&cluster0_opp>;
+               };
+
+               L3_CA55: cache-controller-0 {
+                       compatible = "cache";
+                       cache-unified;
+                       cache-size = <0x40000>;
+               };
+       };
+
+       psci {
+               compatible = "arm,psci-1.0", "arm,psci-0.2";
+               method = "smc";
+       };
+
+       timer {
+               compatible = "arm,armv8-timer";
+               interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                                     <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                                     <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                                     <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+       };
+};
+
+&soc {
+       interrupt-parent = <&gic>;
+
+       gic: interrupt-controller@11900000 {
+               compatible = "arm,gic-v3";
+               #interrupt-cells = <3>;
+               #address-cells = <0>;
+               interrupt-controller;
+               reg = <0x0 0x11900000 0 0x40000>,
+                     <0x0 0x11940000 0 0x60000>;
+               interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+       };
+};
+
+&sysc {
+       interrupts = <SOC_PERIPHERAL_IRQ(42) IRQ_TYPE_LEVEL_HIGH>,
+                    <SOC_PERIPHERAL_IRQ(43) IRQ_TYPE_LEVEL_HIGH>,
+                    <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>,
+                    <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>;
+       interrupt-names = "lpm_int", "ca55stbydone_int",
+                         "cm33stbyr_int", "ca55_deny";
+};