Add fp16 <-> fp64 conversion tests

Require support for VK_KHR_shader_float16_int8 extension.

Added tests:

dEQP-VK.spirv_assembly.instruction.*.16bit_storage*64*

VK-GL-CTS issue: 1116
Components: Vulkan, Framework

Fix 16-bit storage IO f64-to-f16 conversion tests

The tests were applying a rounding mode decoration
to OpFConvert that was used by OpReturnValue.
The extension doesn't allow this. The only allowed
successor for suc instruction is OpStore to specific
storage classes.

Components: Vulkan

VK-GL-CTS issue: 1424

Affects:
dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.*

Change-Id: Ia224e4c6d1e11e6bc1c250d68e5b24f90000d8e6
(cherry picked from commit 04ba8ac400a3a090cfdf68db9ff004cd142fa7ac)
(cherry picked from commit c74832c803b5df82482747fd4dd11fa1d7b6badc)

diff --git a/android/cts/master/vk-master.txt b/android/cts/master/vk-master.txt
index 6b9beea..75ec161 100755 (executable)
--- a/android/cts/master/vk-master.txt
+++ b/android/cts/master/vk-master.txt
@@ -212295,6 +212295,24 @@ dEQP-VK.spirv_assembly.instruction.compute.8bit_storage.uniform_8struct_to_32str
 dEQP-VK.spirv_assembly.instruction.compute.8bit_storage.storagebuffer_32struct_to_8struct.storage_buffer
 dEQP-VK.spirv_assembly.instruction.compute.8bit_storage.struct_mixed_types.storage_buffer
 dEQP-VK.spirv_assembly.instruction.compute.8bit_storage.struct_mixed_types.uniform
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_scalar_float_rtz
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_scalar_float_rte
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_scalar_float_unspecified_rnd_mode
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_vector_float_rtz
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_vector_float_rte
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_vector_float_unspecified_rnd_mode
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_matrix_float_rtz
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_matrix_float_rte
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_matrix_float_unspecified_rnd_mode
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_scalar_float_rtz
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_scalar_float_rte
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_scalar_float_unspecified_rnd_mode
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_vector_float_rtz
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_vector_float_rte
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_vector_float_unspecified_rnd_mode
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_matrix_float_rtz
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_matrix_float_rte
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_matrix_float_unspecified_rnd_mode
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_32_to_16.uniform_buffer_block_scalar_float_rtz
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_32_to_16.uniform_buffer_block_scalar_float_rte
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_32_to_16.uniform_buffer_block_scalar_float_unspecified_rnd_mode
@@ -212347,6 +212365,16 @@ dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_32.unifor
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_32.uniform_scalar_uint_const_idx_8
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_32.uniform_vector_sint
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_32.uniform_vector_uint
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_buffer_block_scalar_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_buffer_block_scalar_const_idx_5_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_buffer_block_scalar_const_idx_8_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_buffer_block_vector_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_buffer_block_matrix_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_scalar_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_scalar_const_idx_5_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_scalar_const_idx_8_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_vector_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_matrix_float
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_32.scalar_float
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_32.scalar_const_idx_5_float
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_32.scalar_const_idx_8_float
@@ -212360,6 +212388,9 @@ dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_32.
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_32.scalar_uint_const_idx_8
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_32.vector_sint
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_32.vector_uint
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_64.scalar_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_64.vector_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_64.matrix_float
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16struct_to_32struct.uniform_buffer_block
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16struct_to_32struct.uniform
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_32struct_to_16struct.uniform_buffer_block
@@ -214250,6 +214281,96 @@ dEQP-VK.spirv_assembly.instruction.graphics.8bit_storage.struct_mixed_types.unif
 dEQP-VK.spirv_assembly.instruction.graphics.8bit_storage.struct_mixed_types.uniform_tesse
 dEQP-VK.spirv_assembly.instruction.graphics.8bit_storage.struct_mixed_types.uniform_geom
 dEQP-VK.spirv_assembly.instruction.graphics.8bit_storage.struct_mixed_types.uniform_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_unspecified_rnd_mode_frag
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_32_to_16.uniform_buffer_block_scalar_float_rtz_vert
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_32_to_16.uniform_buffer_block_scalar_float_rtz_tessc
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_32_to_16.uniform_buffer_block_scalar_float_rtz_tesse
@@ -214430,6 +214551,96 @@ dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_32
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_32.uniform_matrix_float_tesse
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_32.uniform_matrix_float_geom
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_32.uniform_matrix_float_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_4_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_4_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_4_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_4_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_4_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_4_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_4_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_4_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_4_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_4_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_5_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_5_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_5_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_5_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_5_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_5_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_5_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_5_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_5_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_5_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_6_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_6_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_6_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_6_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_6_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_6_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_6_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_6_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_4_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_4_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_4_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_4_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_4_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_4_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_4_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_4_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_4_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_4_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_5_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_5_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_5_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_5_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_5_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_5_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_5_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_5_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_5_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_5_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_6_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_6_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_6_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_6_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_6_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_6_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_6_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_6_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_matrix_float_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_matrix_float_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_matrix_float_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_matrix_float_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_matrix_float_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_matrix_float_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_matrix_float_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_matrix_float_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_matrix_float_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_matrix_float_frag
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_int_32_to_16.uniform_buffer_block_scalar_sint_vert
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_int_32_to_16.uniform_buffer_block_scalar_sint_tessc
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_int_32_to_16.uniform_buffer_block_scalar_sint_tesse
@@ -214630,6 +214841,366 @@ dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_int_16_to_32.u
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_int_16_to_32.uniform_vector_uint_const_idx_6_tesse
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_int_16_to_32.uniform_vector_uint_const_idx_6_geom
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_int_16_to_32.uniform_vector_uint_const_idx_6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_unspecified_rnd_mode_frag
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_32_to_16.scalar0_rtz_vert
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_32_to_16.scalar0_rtz_tessc
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_32_to_16.scalar0_rtz_tesse
@@ -215230,6 +215801,126 @@ dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_16.vector7_tesse
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_16.vector7_geom
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_16.vector7_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar0_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar0_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar0_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar0_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar0_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar1_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar1_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar1_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar1_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar1_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar2_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar2_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar2_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar2_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar2_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar3_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar3_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar3_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar3_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar3_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar4_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar4_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar4_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar4_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar4_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar5_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar5_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar5_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar5_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar5_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar6_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar6_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar6_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar6_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar7_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar7_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar7_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar7_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar7_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar8_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar8_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar8_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar8_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar8_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar9_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar9_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar9_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar9_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar9_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar10_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar10_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar10_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar10_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar10_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar11_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar11_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar11_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar11_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar11_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar12_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar12_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar12_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar12_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar12_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar13_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar13_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar13_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar13_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar13_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar14_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar14_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar14_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar14_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar14_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar15_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar15_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar15_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar15_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar15_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector0_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector0_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector0_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector0_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector0_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector1_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector1_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector1_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector1_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector1_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector2_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector2_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector2_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector2_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector2_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector3_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector3_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector3_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector3_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector3_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector4_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector4_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector4_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector4_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector4_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector5_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector5_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector5_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector5_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector5_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector6_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector6_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector6_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector6_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector7_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector7_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector7_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector7_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector7_frag
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_int_32_to_16.scalar_sint0_vert
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_int_32_to_16.scalar_sint0_tessc
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_int_32_to_16.scalar_sint0_tesse
@@ -215890,6 +216581,21 @@ dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_32.matrix_const_idx_6_tesse
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_32.matrix_const_idx_6_geom
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_32.matrix_const_idx_6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.scalar_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.scalar_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.scalar_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.scalar_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.scalar_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.vector_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.vector_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.vector_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.vector_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.vector_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.matrix_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.matrix_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.matrix_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.matrix_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.matrix_frag
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_int_16_to_32.sint_scalar_vert
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_int_16_to_32.sint_scalar_tessc
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_int_16_to_32.sint_scalar_tesse

diff --git a/external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsm16bitStorageTests.cpp b/external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsm16bitStorageTests.cpp
index e91613a..e76d2aa 100644 (file)
--- a/external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsm16bitStorageTests.cpp
+++ b/external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsm16bitStorageTests.cpp
@@ -208,6 +208,32 @@ bool graphicsCheck16BitFloats (const std::vector<Resource>&        originalFloats,
        return true;
 }
 
+template<RoundingModeFlags RoundingMode>
+bool graphicsCheck16BitFloats64 (const std::vector<Resource>&  originalFloats,
+                                                                const vector<AllocationSp>&    outputAllocs,
+                                                                const std::vector<Resource>&   /* expectedOutputs */,
+                                                                tcu::TestLog&                          log)
+{
+       if (outputAllocs.size() != originalFloats.size())
+               return false;
+
+       for (deUint32 outputNdx = 0; outputNdx < outputAllocs.size(); ++outputNdx)
+       {
+               vector<deUint8> originalBytes;
+               originalFloats[outputNdx].getBuffer()->getPackedBytes(originalBytes);
+
+               const deUint16* returned        = static_cast<const deUint16*>(outputAllocs[outputNdx]->getHostPtr());
+               const double*   original        = reinterpret_cast<const double*>(&originalBytes.front());
+               const deUint32  count           = static_cast<deUint32>(originalBytes.size() / sizeof(double));
+
+               for (deUint32 numNdx = 0; numNdx < count; ++numNdx)
+                       if (!compare16BitFloat64(original[numNdx], returned[numNdx], RoundingMode, log))
+                               return false;
+       }
+
+       return true;
+}
+
 bool computeCheckBuffersFloats (const std::vector<Resource>&   originalFloats,
                                                                const vector<AllocationSp>&             outputAllocs,
                                                                const std::vector<Resource>&    /*expectedOutputs*/,
@@ -260,6 +286,61 @@ bool computeCheck16BitFloats (const std::vector<Resource>& originalFloats,
        return true;
 }
 
+template<RoundingModeFlags RoundingMode>
+bool computeCheck16BitFloats64 (const std::vector<Resource>&   originalFloats,
+                                                               const vector<AllocationSp>&     outputAllocs,
+                                                               const std::vector<Resource>&    /* expectedOutputs */,
+                                                               tcu::TestLog&                                   log)
+{
+       if (outputAllocs.size() != originalFloats.size())
+               return false;
+
+       for (deUint32 outputNdx = 0; outputNdx < outputAllocs.size(); ++outputNdx)
+       {
+               vector<deUint8> originalBytes;
+               originalFloats[outputNdx].getBuffer()->getPackedBytes(originalBytes);
+
+               const deUint16* returned        = static_cast<const deUint16*>(outputAllocs[outputNdx]->getHostPtr());
+               const double*   original        = reinterpret_cast<const double*>(&originalBytes.front());
+               const deUint32  count           = static_cast<deUint32>(originalBytes.size() / sizeof(double));
+
+               for (deUint32 numNdx = 0; numNdx < count; ++numNdx)
+                       if (!compare16BitFloat64(original[numNdx], returned[numNdx], RoundingMode, log))
+                               return false;
+       }
+
+       return true;
+}
+
+// Batch function to check arrays of 64-bit floats.
+//
+// For comparing 64-bit floats, we just need the expected value precomputed in the test case.
+// So we need expected outputs here but not original floats.
+bool check64BitFloats (const std::vector<Resource>&            /* originalFloats */,
+                                          const std::vector<AllocationSp>& outputAllocs,
+                                          const std::vector<Resource>&         expectedOutputs,
+                                          tcu::TestLog&                                        log)
+{
+       if (outputAllocs.size() != expectedOutputs.size())
+               return false;
+
+       for (deUint32 outputNdx = 0; outputNdx < outputAllocs.size(); ++outputNdx)
+       {
+               vector<deUint8> expectedBytes;
+               expectedOutputs[outputNdx].getBuffer()->getPackedBytes(expectedBytes);
+
+               const double*   returnedAsDouble        = static_cast<const double*>(outputAllocs[outputNdx]->getHostPtr());
+               const double*   expectedAsDouble        = reinterpret_cast<const double*>(&expectedBytes.front());
+               const deUint32  count                   = static_cast<deUint32>(expectedBytes.size() / sizeof(double));
+
+               for (deUint32 numNdx = 0; numNdx < count; ++numNdx)
+                       if (!compare64BitFloat(expectedAsDouble[numNdx], returnedAsDouble[numNdx], log))
+                               return false;
+       }
+
+       return true;
+}
+
 // Batch function to check arrays of 32-bit floats.
 //
 // For comparing 32-bit floats, we just need the expected value precomputed in the test case.
@@ -352,6 +433,93 @@ vector<deInt16> getInt16s (de::Random& rnd, const deUint32 count)
 }
 
 // IEEE-754 floating point numbers:
+// +--------+------+----------+-------------+ | binary | sign |
+// exponent | significand | +--------+------+----------+-------------+
+// | 16-bit | 1 |  5 | 10 | +--------+------+----------+-------------+
+// | 64-bit | 1 | 11 | 52 | +--------+------+----------+-------------+
+//
+// 16-bit floats:
+//
+// 0   000 00   00 0000 0001 (0x0001: 2e-24:         minimum positive denormalized)
+// 0   000 00   11 1111 1111 (0x03ff: 2e-14 - 2e-24: maximum positive denormalized)
+// 0   000 01   00 0000 0000 (0x0400: 2e-14:         minimum positive normalized)
+//
+// 32-bit floats:
+//
+// (0x3FD2000000000000: 0.28125: with exact match in 16-bit normalized)
+// (0x3F10060000000000: exact half way within two 16-bit normalized; round to zero: 0x0401)
+// (0xBF10060000000000: exact half way within two 16-bit normalized; round to zero: 0x8402)
+// (0x3F100C0000000000: not exact half way within two 16-bit normalized; round to zero: 0x0403)
+// (0xBF100C0000000000: not exact half way within two 16-bit normalized; round to zero: 0x8404)
+// Generate and return 64-bit floats
+//
+// The first 24 number pairs are manually picked, while the rest are randomly generated.
+// Expected count to be at least 24 (numPicks).
+
+vector<double> getFloat64s (de::Random& rnd, deUint32 count)
+{
+       vector<double>          float64;
+
+       float64.reserve(count);
+
+       if (count >= 24)
+       {
+               // Zero
+               float64.push_back(0.f);
+               float64.push_back(-0.f);
+               // Infinity
+               float64.push_back(std::numeric_limits<double>::infinity());
+               float64.push_back(-std::numeric_limits<double>::infinity());
+               // SNaN
+               float64.push_back(std::numeric_limits<double>::signaling_NaN());
+               float64.push_back(-std::numeric_limits<double>::signaling_NaN());
+               // QNaN
+               float64.push_back(std::numeric_limits<double>::quiet_NaN());
+               float64.push_back(-std::numeric_limits<double>::quiet_NaN());
+
+               // Denormalized 64-bit float matching 0 in 16-bit
+               float64.push_back(ldexp((double)1.f, -1023));
+               float64.push_back(-ldexp((double)1.f, -1023));
+
+               // Normalized 64-bit float matching 0 in 16-bit
+               float64.push_back(ldexp((double)1.f, -100));
+               float64.push_back(-ldexp((double)1.f, -100));
+               // Normalized 64-bit float with exact denormalized match in 16-bit
+               float64.push_back(bitwiseCast<double>(deUint64(0x3B0357C299A88EA8)));
+               float64.push_back(bitwiseCast<double>(deUint64(0xBB0357C299A88EA8)));
+
+               // Normalized 64-bit float with exact normalized match in 16-bit
+               float64.push_back(ldexp((double)1.f, -14));  // 2e-14: minimum 16-bit positive normalized
+               float64.push_back(-ldexp((double)1.f, -14)); // 2e-14: maximum 16-bit negative normalized
+               // Normalized 64-bit float falling above half way within two 16-bit normalized
+               float64.push_back(bitwiseCast<double>(deUint64(0x3FD2000000000000)));
+               float64.push_back(bitwiseCast<double>(deUint64(0xBFD2000000000000)));
+               // Normalized 64-bit float falling exact half way within two 16-bit normalized
+               float64.push_back(bitwiseCast<double>(deUint64(0x3F100C0000000000)));
+               float64.push_back(bitwiseCast<double>(deUint64(0xBF100C0000000000)));
+               // Some number
+               float64.push_back((double)0.28125f);
+               float64.push_back((double)-0.28125f);
+               // Normalized 64-bit float matching infinity in 16-bit
+               float64.push_back(ldexp((double)1.f, 100));
+               float64.push_back(-ldexp((double)1.f, 100));
+       }
+
+       const deUint32          numPicks        = static_cast<deUint32>(float64.size());
+
+       DE_ASSERT(count >= numPicks);
+       count -= numPicks;
+
+       for (deUint32 numNdx = 0; numNdx < count; ++numNdx)
+       {
+               double randValue = rnd.getDouble();
+               float64.push_back(randValue);
+       }
+
+       return float64;
+}
+
+// IEEE-754 floating point numbers:
 // +--------+------+----------+-------------+
 // | binary | sign | exponent | significand |
 // +--------+------+----------+-------------+
@@ -1285,7 +1453,7 @@ void addCompute16bitStorageUniform16To32Group (tcu::TestCaseGroup* group)
                "OpExecutionMode %main LocalSize 1 1 1\n"
                "OpDecorate %id BuiltIn GlobalInvocationId\n"
 
-               "${stride}"
+               "${stride}\n"
 
                "OpMemberDecorate %SSBO32 0 Offset 0\n"
                "OpMemberDecorate %SSBO16 0 Offset 0\n"
@@ -6428,14 +6596,1827 @@ void addGraphics16bitStructMixedTypesGroup (tcu::TestCaseGroup* group)
        }
 }
 
+void addGraphics16BitStorageInputOutputFloat16To64Group (tcu::TestCaseGroup* testGroup)
+{
+       de::Random                              rnd                                     (deStringHash(testGroup->getName()));
+       RGBA                                    defaultColors[4];
+       vector<string>                  extensions;
+       map<string, string>             fragments                       = passthruFragments();
+       const deUint32                  numDataPoints           = 64;
+       vector<deFloat16>               float16Data                     (getFloat16s(rnd, numDataPoints));
+       vector<double>                  float64Data;
+
+       float64Data.reserve(numDataPoints);
+       for (deUint32 numIdx = 0; numIdx < numDataPoints; ++numIdx)
+               float64Data.push_back(deFloat16To64(float16Data[numIdx]));
+
+       extensions.push_back("VK_KHR_16bit_storage");
+       extensions.push_back("VK_KHR_shader_float16_int8");
+
+       fragments["capability"]                         =
+               "OpCapability StorageInputOutput16\n"
+               "OpCapability Float64\n"
+               "OpCapability Float16\n";
+       fragments["extension"]                          = "OpExtension \"SPV_KHR_16bit_storage\"\n";
+
+       getDefaultColors(defaultColors);
+
+       struct Case
+       {
+               const char*     name;
+               const char*     interfaceOpFunc;
+               const char*     preMain;
+               const char*     inputType;
+               const char*     outputType;
+               deUint32        numPerCase;
+               deUint32        numElements;
+       };
+
+       Case    cases[]         =
+       {
+               { // Scalar cases
+                       "scalar",
+
+                       "%interface_op_func = OpFunction %f64 None %f64_f16_function\n"
+                       "        %io_param1 = OpFunctionParameter %f16\n"
+                       "            %entry = OpLabel\n"
+                       "                          %ret = OpFConvert %f64 %io_param1\n"
+                       "                     OpReturnValue %ret\n"
+                       "                     OpFunctionEnd\n",
+
+                       "             %f16 = OpTypeFloat 16\n"
+                       "             %f64 = OpTypeFloat 64\n"
+                       "                       %v4f64 = OpTypeVector %f64 4\n"
+                       "          %ip_f16 = OpTypePointer Input %f16\n"
+                       "           %a3f16 = OpTypeArray %f16 %c_i32_3\n"
+                       "        %ip_a3f16 = OpTypePointer Input %a3f16\n"
+                       "%f64_f16_function = OpTypeFunction %f64 %f16\n"
+                       "           %a3f64 = OpTypeArray %f64 %c_i32_3\n"
+                       "            %op_f64 = OpTypePointer Output %f64\n"
+                       "        %op_a3f64 = OpTypePointer Output %a3f64\n",
+
+                       "f16",
+                       "f64",
+                       4,
+                       1,
+               },
+               { // Vector cases
+                       "vector",
+
+                       "%interface_op_func = OpFunction %v2f64 None %v2f64_v2f16_function\n"
+                       "        %io_param1 = OpFunctionParameter %v2f16\n"
+                       "            %entry = OpLabel\n"
+                       "                          %ret = OpFConvert %v2f64 %io_param1\n"
+                       "                     OpReturnValue %ret\n"
+                       "                     OpFunctionEnd\n",
+
+                       "                 %f16 = OpTypeFloat 16\n"
+                       "                       %v2f16 = OpTypeVector %f16 2\n"
+                       "                 %f64 = OpTypeFloat 64\n"
+                       "                       %v2f64 = OpTypeVector %f64 2\n"
+                       "                       %v4f64 = OpTypeVector %f64 4\n"
+                       "            %ip_v2f16 = OpTypePointer Input %v2f16\n"
+                       "             %a3v2f16 = OpTypeArray %v2f16 %c_i32_3\n"
+                       "          %ip_a3v2f16 = OpTypePointer Input %a3v2f16\n"
+                       "%v2f64_v2f16_function = OpTypeFunction %v2f64 %v2f16\n"
+                       "             %a3v2f64 = OpTypeArray %v2f64 %c_i32_3\n"
+                       "            %op_f64 = OpTypePointer Output %f64\n"
+                       "            %op_v2f64 = OpTypePointer Output %v2f64\n"
+                       "            %op_v4f64 = OpTypePointer Output %v4f64\n"
+                       "          %op_a3v2f64 = OpTypePointer Output %a3v2f64\n",
+
+                       "v2f16",
+                       "v2f64",
+                       2 * 4,
+                       2,
+               }
+       };
+
+       VulkanFeatures  requiredFeatures;
+       requiredFeatures.ext16BitStorage = EXT16BITSTORAGEFEATURES_INPUT_OUTPUT;
+       requiredFeatures.coreFeatures.shaderFloat64 = DE_TRUE;
+
+       for (deUint32 caseIdx = 0; caseIdx < DE_LENGTH_OF_ARRAY(cases); ++caseIdx)
+       {
+               fragments["interface_op_func"]  = cases[caseIdx].interfaceOpFunc;
+               fragments["pre_main"]                   = cases[caseIdx].preMain;
+
+               fragments["input_type"]                 = cases[caseIdx].inputType;
+               fragments["output_type"]                = cases[caseIdx].outputType;
+
+               GraphicsInterfaces      interfaces;
+               const deUint32          numPerCase      = cases[caseIdx].numPerCase;
+               vector<deFloat16>       subInputs       (numPerCase);
+               vector<double>          subOutputs      (numPerCase);
+
+               for (deUint32 caseNdx = 0; caseNdx < numDataPoints / numPerCase; ++caseNdx)
+               {
+                       string                  testName        = string(cases[caseIdx].name) + numberToString(caseNdx);
+
+                       for (deUint32 numNdx = 0; numNdx < numPerCase; ++numNdx)
+                       {
+                               subInputs[numNdx]       = float16Data[caseNdx * numPerCase + numNdx];
+                               subOutputs[numNdx]      = float64Data[caseNdx * numPerCase + numNdx];
+                       }
+                       interfaces.setInputOutput(std::make_pair(IFDataType(cases[caseIdx].numElements, NUMBERTYPE_FLOAT16), BufferSp(new Float16Buffer(subInputs))),
+                                                                         std::make_pair(IFDataType(cases[caseIdx].numElements, NUMBERTYPE_FLOAT64), BufferSp(new Float64Buffer(subOutputs))));
+                       createTestsForAllStages(testName, defaultColors, defaultColors, fragments, interfaces, extensions, testGroup, requiredFeatures);
+               }
+       }
+}
+
+void addGraphics16BitStorageUniformFloat16To64Group (tcu::TestCaseGroup* testGroup)
+{
+       de::Random                                                      rnd                                     (deStringHash(testGroup->getName()));
+       map<string, string>                                     fragments;
+       vector<string>                                          extensions;
+       const deUint32                                          numDataPoints           = 256;
+       RGBA                                                            defaultColors[4];
+       const StringTemplate                            capabilities            ("OpCapability ${cap}\n"
+                                                                                                                        "OpCapability Float64\n"
+                                                                                                                        "OpCapability Float16\n");
+       vector<deFloat16>                                       float16Data                     = getFloat16s(rnd, numDataPoints);
+
+       struct ConstantIndex
+       {
+               bool            useConstantIndex;
+               deUint32        constantIndex;
+       };
+
+       ConstantIndex   constantIndices[] =
+       {
+               { false,        0 },
+               { true,         4 },
+               { true,         5 },
+               { true,         6 }
+       };
+
+       extensions.push_back("VK_KHR_16bit_storage");
+       extensions.push_back("VK_KHR_shader_float16_int8");
+
+       fragments["extension"]  = "OpExtension \"SPV_KHR_16bit_storage\"";
+
+       getDefaultColors(defaultColors);
+
+       { // scalar cases
+               const StringTemplate preMain            (
+                       "      %f16 = OpTypeFloat 16\n"
+                       "      %f64 = OpTypeFloat 64\n"
+                       "%c_i32_256 = OpConstant %i32 256\n"
+                       " %c_i32_ci = OpConstant %i32 ${constarrayidx}\n"
+                       "   %up_f64 = OpTypePointer Uniform %f64\n"
+                       "   %up_f16 = OpTypePointer Uniform %f16\n"
+                       "   %ra_f64 = OpTypeArray %f64 %c_i32_256\n"
+                       "   %ra_f16 = OpTypeArray %f16 %c_i32_256\n"
+                       "   %SSBO64 = OpTypeStruct %ra_f64\n"
+                       "   %SSBO16 = OpTypeStruct %ra_f16\n"
+                       "%up_SSBO64 = OpTypePointer Uniform %SSBO64\n"
+                       "%up_SSBO16 = OpTypePointer Uniform %SSBO16\n"
+                       "   %ssbo64 = OpVariable %up_SSBO64 Uniform\n"
+                       "   %ssbo16 = OpVariable %up_SSBO16 Uniform\n");
+
+               const StringTemplate decoration         (
+                       "OpDecorate %ra_f64 ArrayStride 8\n"
+                       "OpDecorate %ra_f16 ArrayStride ${stride16}\n"
+                       "OpMemberDecorate %SSBO64 0 Offset 0\n"
+                       "OpMemberDecorate %SSBO16 0 Offset 0\n"
+                       "OpDecorate %SSBO64 BufferBlock\n"
+                       "OpDecorate %SSBO16 ${indecor}\n"
+                       "OpDecorate %ssbo64 DescriptorSet 0\n"
+                       "OpDecorate %ssbo16 DescriptorSet 0\n"
+                       "OpDecorate %ssbo64 Binding 1\n"
+                       "OpDecorate %ssbo16 Binding 0\n");
+
+               // ssbo64[] <- convert ssbo16[] to 64bit float
+               const StringTemplate testFun            (
+                       "%test_code = OpFunction %v4f32 None %v4f32_v4f32_function\n"
+                       "    %param = OpFunctionParameter %v4f32\n"
+
+                       "%entry = OpLabel\n"
+                       "    %i = OpVariable %fp_i32 Function\n"
+                       "         OpStore %i %c_i32_0\n"
+                       "         OpBranch %loop\n"
+
+                       " %loop = OpLabel\n"
+                       "   %15 = OpLoad %i32 %i\n"
+                       "   %lt = OpSLessThan %bool %15 %c_i32_256\n"
+                       "         OpLoopMerge %merge %inc None\n"
+                       "         OpBranchConditional %lt %write %merge\n"
+
+                       "%write = OpLabel\n"
+                       "   %30 = OpLoad %i32 %i\n"
+                       "  %src = OpAccessChain %up_f16 %ssbo16 %c_i32_0 %${arrayindex}\n"
+                       "%val16 = OpLoad %f16 %src\n"
+                       "%val64 = OpFConvert %f64 %val16\n"
+                       "  %dst = OpAccessChain %up_f64 %ssbo64 %c_i32_0 %30\n"
+                       "         OpStore %dst %val64\n"
+                       "         OpBranch %inc\n"
+
+                       "  %inc = OpLabel\n"
+                       "   %37 = OpLoad %i32 %i\n"
+                       "   %39 = OpIAdd %i32 %37 %c_i32_1\n"
+                       "         OpStore %i %39\n"
+                       "         OpBranch %loop\n"
+
+                       "%merge = OpLabel\n"
+                       "         OpReturnValue %param\n"
+
+                       "OpFunctionEnd\n");
+
+               for (deUint32 constIndexIdx = 0; constIndexIdx < DE_LENGTH_OF_ARRAY(constantIndices); ++constIndexIdx)
+               {
+                       for (deUint32 capIdx = 0; capIdx < DE_LENGTH_OF_ARRAY(CAPABILITIES); ++capIdx)
+                       {
+                               GraphicsResources       resources;
+                               map<string, string>     specs;
+                               string                          testName        = string(CAPABILITIES[capIdx].name) + "_scalar_float";
+                               bool                            useConstIdx     = constantIndices[constIndexIdx].useConstantIndex;
+                               deUint32                        constIdx        = constantIndices[constIndexIdx].constantIndex;
+                               const bool                      isUBO           = CAPABILITIES[capIdx].dtype == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER;
+
+                               specs["cap"]                                    = CAPABILITIES[capIdx].cap;
+                               specs["indecor"]                                = CAPABILITIES[capIdx].decor;
+                               specs["constarrayidx"]                  = de::toString(constIdx);
+                               specs["stride16"]                               = isUBO ? "16" : "2";
+
+                               if (useConstIdx)
+                                       specs["arrayindex"] = "c_i32_ci";
+                               else
+                                       specs["arrayindex"] = "30";
+
+                               fragments["capability"]                 = capabilities.specialize(specs);
+                               fragments["decoration"]                 = decoration.specialize(specs);
+                               fragments["pre_main"]                   = preMain.specialize(specs);
+                               fragments["testfun"]                    = testFun.specialize(specs);
+
+                               vector<double>          float64Data;
+                               float64Data.reserve(numDataPoints);
+                               for (deUint32 numIdx = 0; numIdx < numDataPoints; ++numIdx)
+                                       float64Data.push_back(deFloat16To64(float16Data[useConstIdx ? constIdx : numIdx]));
+
+                               resources.inputs.push_back(Resource(BufferSp(new Float16Buffer(float16Data, isUBO ? 14 : 0)), VK_DESCRIPTOR_TYPE_STORAGE_BUFFER));
+                               resources.outputs.push_back(Resource(BufferSp(new Float64Buffer(float64Data)), VK_DESCRIPTOR_TYPE_STORAGE_BUFFER));
+                               resources.verifyIO = check64BitFloats;
+                               resources.inputs.back().setDescriptorType(CAPABILITIES[capIdx].dtype);
+
+                               if (useConstIdx)
+                                       testName += string("_const_idx_") + de::toString(constIdx);
+
+                               VulkanFeatures features = get16BitStorageFeatures(CAPABILITIES[capIdx].name);
+                               features.coreFeatures.shaderFloat64 = DE_TRUE;
+                               createTestsForAllStages(testName, defaultColors, defaultColors, fragments, resources, extensions, testGroup, features);
+                       }
+               }
+       }
+
+       { // vector cases
+               const StringTemplate preMain            (
+                       "      %f16 = OpTypeFloat 16\n"
+                       "      %f64 = OpTypeFloat 64\n"
+                       "%c_i32_128 = OpConstant %i32 128\n"
+                       "%c_i32_ci  = OpConstant %i32 ${constarrayidx}\n"
+                       "        %v2f16 = OpTypeVector %f16 2\n"
+                       "        %v2f64 = OpTypeVector %f64 2\n"
+                       " %up_v2f64 = OpTypePointer Uniform %v2f64\n"
+                       " %up_v2f16 = OpTypePointer Uniform %v2f16\n"
+                       " %ra_v2f64 = OpTypeArray %v2f64 %c_i32_128\n"
+                       " %ra_v2f16 = OpTypeArray %v2f16 %c_i32_128\n"
+                       "   %SSBO64 = OpTypeStruct %ra_v2f64\n"
+                       "   %SSBO16 = OpTypeStruct %ra_v2f16\n"
+                       "%up_SSBO64 = OpTypePointer Uniform %SSBO64\n"
+                       "%up_SSBO16 = OpTypePointer Uniform %SSBO16\n"
+                       "   %ssbo64 = OpVariable %up_SSBO64 Uniform\n"
+                       "   %ssbo16 = OpVariable %up_SSBO16 Uniform\n");
+
+               const StringTemplate decoration         (
+                       "OpDecorate %ra_v2f64 ArrayStride 16\n"
+                       "OpDecorate %ra_v2f16 ArrayStride ${stride16}\n"
+                       "OpMemberDecorate %SSBO64 0 Offset 0\n"
+                       "OpMemberDecorate %SSBO16 0 Offset 0\n"
+                       "OpDecorate %SSBO64 BufferBlock\n"
+                       "OpDecorate %SSBO16 ${indecor}\n"
+                       "OpDecorate %ssbo64 DescriptorSet 0\n"
+                       "OpDecorate %ssbo16 DescriptorSet 0\n"
+                       "OpDecorate %ssbo64 Binding 1\n"
+                       "OpDecorate %ssbo16 Binding 0\n");
+
+               // ssbo64[] <- convert ssbo16[] to 64bit float
+               const StringTemplate testFun            (
+                       "%test_code = OpFunction %v4f32 None %v4f32_v4f32_function\n"
+                       "    %param = OpFunctionParameter %v4f32\n"
+
+                       "%entry = OpLabel\n"
+                       "    %i = OpVariable %fp_i32 Function\n"
+                       "         OpStore %i %c_i32_0\n"
+                       "         OpBranch %loop\n"
+
+                       " %loop = OpLabel\n"
+                       "   %15 = OpLoad %i32 %i\n"
+                       "   %lt = OpSLessThan %bool %15 %c_i32_128\n"
+                       "         OpLoopMerge %merge %inc None\n"
+                       "         OpBranchConditional %lt %write %merge\n"
+
+                       "%write = OpLabel\n"
+                       "   %30 = OpLoad %i32 %i\n"
+                       "  %src = OpAccessChain %up_v2f16 %ssbo16 %c_i32_0 %${arrayindex}\n"
+                       "%val16 = OpLoad %v2f16 %src\n"
+                       "%val64 = OpFConvert %v2f64 %val16\n"
+                       "  %dst = OpAccessChain %up_v2f64 %ssbo64 %c_i32_0 %30\n"
+                       "         OpStore %dst %val64\n"
+                       "         OpBranch %inc\n"
+
+                       "  %inc = OpLabel\n"
+                       "   %37 = OpLoad %i32 %i\n"
+                       "   %39 = OpIAdd %i32 %37 %c_i32_1\n"
+                       "         OpStore %i %39\n"
+                       "         OpBranch %loop\n"
+
+                       "%merge = OpLabel\n"
+                       "         OpReturnValue %param\n"
+
+                       "OpFunctionEnd\n");
+
+               for (deUint32 constIndexIdx = 0; constIndexIdx < DE_LENGTH_OF_ARRAY(constantIndices); ++constIndexIdx)
+               {
+                       for (deUint32 capIdx = 0; capIdx < DE_LENGTH_OF_ARRAY(CAPABILITIES); ++capIdx)
+                       {
+                               GraphicsResources       resources;
+                               map<string, string>     specs;
+                               string                          testName        = string(CAPABILITIES[capIdx].name) + "_vector_float";
+                               bool                            useConstIdx     = constantIndices[constIndexIdx].useConstantIndex;
+                               deUint32                        constIdx        = constantIndices[constIndexIdx].constantIndex;
+                               const bool                      isUBO           = CAPABILITIES[capIdx].dtype == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER;
+
+                               specs["cap"]                                    = CAPABILITIES[capIdx].cap;
+                               specs["indecor"]                                = CAPABILITIES[capIdx].decor;
+                               specs["constarrayidx"]                  = de::toString(constIdx);
+                               specs["stride16"]                               = isUBO ? "16" : "4";
+
+                               if (useConstIdx)
+                                       specs["arrayindex"] = "c_i32_ci";
+                               else
+                                       specs["arrayindex"] = "30";
+
+                               fragments["capability"]                 = capabilities.specialize(specs);
+                               fragments["decoration"]                 = decoration.specialize(specs);
+                               fragments["pre_main"]                   = preMain.specialize(specs);
+                               fragments["testfun"]                    = testFun.specialize(specs);
+
+                               vector<double>          float64Data;
+                               float64Data.reserve(numDataPoints);
+                               for (deUint32 numIdx = 0; numIdx < numDataPoints; ++numIdx)
+                                       float64Data.push_back(deFloat16To64(float16Data[constantIndices[constIndexIdx].useConstantIndex ? (constantIndices[constIndexIdx].constantIndex * 2 + numIdx % 2) : numIdx]));
+
+                               resources.inputs.push_back(Resource(BufferSp(new Float16Buffer(float16Data, isUBO ? 12 : 0)), VK_DESCRIPTOR_TYPE_STORAGE_BUFFER));
+                               resources.outputs.push_back(Resource(BufferSp(new Float64Buffer(float64Data)), VK_DESCRIPTOR_TYPE_STORAGE_BUFFER));
+                               resources.verifyIO = check64BitFloats;
+                               resources.inputs.back().setDescriptorType(CAPABILITIES[capIdx].dtype);
+
+                               if (constantIndices[constIndexIdx].useConstantIndex)
+                                       testName += string("_const_idx_") + de::toString(constantIndices[constIndexIdx].constantIndex);
+
+                               VulkanFeatures features = get16BitStorageFeatures(CAPABILITIES[capIdx].name);
+                               features.coreFeatures.shaderFloat64 = DE_TRUE;
+                               createTestsForAllStages(testName, defaultColors, defaultColors, fragments, resources, extensions, testGroup, features);
+                       }
+               }
+       }
+
+       { // matrix cases
+               fragments["pre_main"]                           =
+                       " %c_i32_32 = OpConstant %i32 32\n"
+                       "      %f16 = OpTypeFloat 16\n"
+                       "      %f64 = OpTypeFloat 64\n"
+                       "    %v2f16 = OpTypeVector %f16 2\n"
+                       "    %v2f64 = OpTypeVector %f64 2\n"
+                       "  %m4x2f64 = OpTypeMatrix %v2f64 4\n"
+                       "  %m4x2f16 = OpTypeMatrix %v2f16 4\n"
+                       " %up_v2f64 = OpTypePointer Uniform %v2f64\n"
+                       " %up_v2f16 = OpTypePointer Uniform %v2f16\n"
+                       "%a8m4x2f64 = OpTypeArray %m4x2f64 %c_i32_32\n"
+                       "%a8m4x2f16 = OpTypeArray %m4x2f16 %c_i32_32\n"
+                       "   %SSBO64 = OpTypeStruct %a8m4x2f64\n"
+                       "   %SSBO16 = OpTypeStruct %a8m4x2f16\n"
+                       "%up_SSBO64 = OpTypePointer Uniform %SSBO64\n"
+                       "%up_SSBO16 = OpTypePointer Uniform %SSBO16\n"
+                       "   %ssbo64 = OpVariable %up_SSBO64 Uniform\n"
+                       "   %ssbo16 = OpVariable %up_SSBO16 Uniform\n";
+
+               const StringTemplate decoration         (
+                       "OpDecorate %a8m4x2f64 ArrayStride 64\n"
+                       "OpDecorate %a8m4x2f16 ArrayStride 16\n"
+                       "OpMemberDecorate %SSBO64 0 Offset 0\n"
+                       "OpMemberDecorate %SSBO64 0 ColMajor\n"
+                       "OpMemberDecorate %SSBO64 0 MatrixStride 16\n"
+                       "OpMemberDecorate %SSBO16 0 Offset 0\n"
+                       "OpMemberDecorate %SSBO16 0 ColMajor\n"
+                       "OpMemberDecorate %SSBO16 0 MatrixStride 4\n"
+                       "OpDecorate %SSBO64 BufferBlock\n"
+                       "OpDecorate %SSBO16 ${indecor}\n"
+                       "OpDecorate %ssbo64 DescriptorSet 0\n"
+                       "OpDecorate %ssbo16 DescriptorSet 0\n"
+                       "OpDecorate %ssbo64 Binding 1\n"
+                       "OpDecorate %ssbo16 Binding 0\n");
+
+               fragments["testfun"]                            =
+                       "%test_code = OpFunction %v4f32 None %v4f32_v4f32_function\n"
+                       "    %param = OpFunctionParameter %v4f32\n"
+
+                       "%entry = OpLabel\n"
+                       "    %i = OpVariable %fp_i32 Function\n"
+                       "         OpStore %i %c_i32_0\n"
+                       "         OpBranch %loop\n"
+
+                       " %loop = OpLabel\n"
+                       "   %15 = OpLoad %i32 %i\n"
+                       "   %lt = OpSLessThan %bool %15 %c_i32_32\n"
+                       "         OpLoopMerge %merge %inc None\n"
+                       "         OpBranchConditional %lt %write %merge\n"
+
+                       "  %write = OpLabel\n"
+                       "     %30 = OpLoad %i32 %i\n"
+                       "  %src_0 = OpAccessChain %up_v2f16 %ssbo16 %c_i32_0 %30 %c_i32_0\n"
+                       "  %src_1 = OpAccessChain %up_v2f16 %ssbo16 %c_i32_0 %30 %c_i32_1\n"
+                       "  %src_2 = OpAccessChain %up_v2f16 %ssbo16 %c_i32_0 %30 %c_i32_2\n"
+                       "  %src_3 = OpAccessChain %up_v2f16 %ssbo16 %c_i32_0 %30 %c_i32_3\n"
+                       "%val16_0 = OpLoad %v2f16 %src_0\n"
+                       "%val16_1 = OpLoad %v2f16 %src_1\n"
+                       "%val16_2 = OpLoad %v2f16 %src_2\n"
+                       "%val16_3 = OpLoad %v2f16 %src_3\n"
+                       "%val64_0 = OpFConvert %v2f64 %val16_0\n"
+                       "%val64_1 = OpFConvert %v2f64 %val16_1\n"
+                       "%val64_2 = OpFConvert %v2f64 %val16_2\n"
+                       "%val64_3 = OpFConvert %v2f64 %val16_3\n"
+                       "  %dst_0 = OpAccessChain %up_v2f64 %ssbo64 %c_i32_0 %30 %c_i32_0\n"
+                       "  %dst_1 = OpAccessChain %up_v2f64 %ssbo64 %c_i32_0 %30 %c_i32_1\n"
+                       "  %dst_2 = OpAccessChain %up_v2f64 %ssbo64 %c_i32_0 %30 %c_i32_2\n"
+                       "  %dst_3 = OpAccessChain %up_v2f64 %ssbo64 %c_i32_0 %30 %c_i32_3\n"
+                       "           OpStore %dst_0 %val64_0\n"
+                       "           OpStore %dst_1 %val64_1\n"
+                       "           OpStore %dst_2 %val64_2\n"
+                       "           OpStore %dst_3 %val64_3\n"
+                       "           OpBranch %inc\n"
+
+                       "  %inc = OpLabel\n"
+                       "   %37 = OpLoad %i32 %i\n"
+                       "   %39 = OpIAdd %i32 %37 %c_i32_1\n"
+                       "         OpStore %i %39\n"
+                       "         OpBranch %loop\n"
+
+                       "%merge = OpLabel\n"
+                       "         OpReturnValue %param\n"
+
+                       "OpFunctionEnd\n";
+
+                       for (deUint32 capIdx = 0; capIdx < DE_LENGTH_OF_ARRAY(CAPABILITIES); ++capIdx)
+                       {
+                               GraphicsResources       resources;
+                               map<string, string>     specs;
+                               string                          testName        = string(CAPABILITIES[capIdx].name) + "_matrix_float";
+
+                               specs["cap"]                                    = CAPABILITIES[capIdx].cap;
+                               specs["indecor"]                                = CAPABILITIES[capIdx].decor;
+
+                               fragments["capability"]                 = capabilities.specialize(specs);
+                               fragments["decoration"]                 = decoration.specialize(specs);
+
+                               vector<double>          float64Data;
+                               float64Data.reserve(numDataPoints);
+                               for (deUint32 numIdx = 0; numIdx < numDataPoints; ++numIdx)
+                                       float64Data.push_back(deFloat16To64(float16Data[numIdx]));
+
+                               resources.inputs.push_back(Resource(BufferSp(new Float16Buffer(float16Data)), VK_DESCRIPTOR_TYPE_STORAGE_BUFFER));
+                               resources.outputs.push_back(Resource(BufferSp(new Float64Buffer(float64Data)), VK_DESCRIPTOR_TYPE_STORAGE_BUFFER));
+                               resources.verifyIO = check64BitFloats;
+                               resources.inputs.back().setDescriptorType(CAPABILITIES[capIdx].dtype);
+
+                               VulkanFeatures features = get16BitStorageFeatures(CAPABILITIES[capIdx].name);
+                               features.coreFeatures.shaderFloat64 = DE_TRUE;
+                               createTestsForAllStages(testName, defaultColors, defaultColors, fragments, resources, extensions, testGroup, features);
+               }
+       }
+}
+
+void addGraphics16BitStoragePushConstantFloat16To64Group (tcu::TestCaseGroup* testGroup)
+{
+       de::Random                                                      rnd                                     (deStringHash(testGroup->getName()));
+       map<string, string>                                     fragments;
+       RGBA                                                            defaultColors[4];
+       vector<string>                                          extensions;
+       GraphicsResources                                       resources;
+       PushConstants                                           pcs;
+       const deUint32                                          numDataPoints           = 64;
+       vector<deFloat16>                                       float16Data                     (getFloat16s(rnd, numDataPoints));
+       vector<double>                                          float64Data;
+       VulkanFeatures                                          requiredFeatures;
+
+       float64Data.reserve(numDataPoints);
+       for (deUint32 numIdx = 0; numIdx < numDataPoints; ++numIdx)
+               float64Data.push_back(deFloat16To64(float16Data[numIdx]));
+
+       extensions.push_back("VK_KHR_16bit_storage");
+       extensions.push_back("VK_KHR_shader_float16_int8");
+
+       requiredFeatures.ext16BitStorage = EXT16BITSTORAGEFEATURES_PUSH_CONSTANT;
+       requiredFeatures.coreFeatures.shaderFloat64 = DE_TRUE;
+
+       fragments["capability"]                         =
+               "OpCapability StoragePushConstant16\n"
+               "OpCapability Float64\n"
+               "OpCapability Float16\n";
+
+       fragments["extension"]                          = "OpExtension \"SPV_KHR_16bit_storage\"";
+
+       pcs.setPushConstant(BufferSp(new Float16Buffer(float16Data)));
+       resources.outputs.push_back(Resource(BufferSp(new Float64Buffer(float64Data)), VK_DESCRIPTOR_TYPE_STORAGE_BUFFER));
+       resources.verifyIO = check64BitFloats;
+
+       getDefaultColors(defaultColors);
+
+       const StringTemplate    testFun         (
+               "%test_code = OpFunction %v4f32 None %v4f32_v4f32_function\n"
+               "    %param = OpFunctionParameter %v4f32\n"
+
+               "%entry = OpLabel\n"
+               "    %i = OpVariable %fp_i32 Function\n"
+               "         OpStore %i %c_i32_0\n"
+               "         OpBranch %loop\n"
+
+               " %loop = OpLabel\n"
+               "   %15 = OpLoad %i32 %i\n"
+               "   %lt = OpSLessThan %bool %15 ${count}\n"
+               "         OpLoopMerge %merge %inc None\n"
+               "         OpBranchConditional %lt %write %merge\n"
+
+               "%write = OpLabel\n"
+               "   %30 = OpLoad %i32 %i\n"
+               "  %src = OpAccessChain ${pp_type16} %pc16 %c_i32_0 %30 ${index0:opt}\n"
+               "%val16 = OpLoad ${f_type16} %src\n"
+               "%val64 = OpFConvert ${f_type64} %val16\n"
+               "  %dst = OpAccessChain ${up_type64} %ssbo64 %c_i32_0 %30 ${index0:opt}\n"
+               "         OpStore %dst %val64\n"
+
+               "${store:opt}\n"
+
+               "         OpBranch %inc\n"
+
+               "  %inc = OpLabel\n"
+               "   %37 = OpLoad %i32 %i\n"
+               "   %39 = OpIAdd %i32 %37 %c_i32_1\n"
+               "         OpStore %i %39\n"
+               "         OpBranch %loop\n"
+
+               "%merge = OpLabel\n"
+               "         OpReturnValue %param\n"
+
+               "OpFunctionEnd\n");
+
+       {  // Scalar cases
+               fragments["pre_main"]                           =
+                       "           %f16 = OpTypeFloat 16\n"
+                       "           %f64 = OpTypeFloat 64\n"
+                       "      %c_i32_64 = OpConstant %i32 64\n"                                        // Should be the same as numDataPoints
+                       "         %v4f64 = OpTypeVector %f64 4\n"
+                       "        %a64f16 = OpTypeArray %f16 %c_i32_64\n"
+                       "        %a64f64 = OpTypeArray %f64 %c_i32_64\n"
+                       "        %pp_f16 = OpTypePointer PushConstant %f16\n"
+                       "        %up_f64 = OpTypePointer Uniform %f64\n"
+                       "        %SSBO64 = OpTypeStruct %a64f64\n"
+                       "     %up_SSBO64 = OpTypePointer Uniform %SSBO64\n"
+                       "        %ssbo64 = OpVariable %up_SSBO64 Uniform\n"
+                       "          %PC16 = OpTypeStruct %a64f16\n"
+                       "       %pp_PC16 = OpTypePointer PushConstant %PC16\n"
+                       "          %pc16 = OpVariable %pp_PC16 PushConstant\n";
+
+               fragments["decoration"]                         =
+                       "OpDecorate %a64f16 ArrayStride 2\n"
+                       "OpDecorate %a64f64 ArrayStride 8\n"
+                       "OpDecorate %SSBO64 BufferBlock\n"
+                       "OpMemberDecorate %SSBO64 0 Offset 0\n"
+                       "OpDecorate %PC16 Block\n"
+                       "OpMemberDecorate %PC16 0 Offset 0\n"
+                       "OpDecorate %ssbo64 DescriptorSet 0\n"
+                       "OpDecorate %ssbo64 Binding 0\n";
+
+               map<string, string>             specs;
+
+               specs["count"]                  = "%c_i32_64";
+               specs["pp_type16"]              = "%pp_f16";
+               specs["f_type16"]               = "%f16";
+               specs["f_type64"]               = "%f64";
+               specs["up_type64"]              = "%up_f64";
+
+               fragments["testfun"]    = testFun.specialize(specs);
+
+               createTestsForAllStages("scalar", defaultColors, defaultColors, fragments, pcs, resources, extensions, testGroup, requiredFeatures);
+       }
+
+       {  // Vector cases
+               fragments["pre_main"]                           =
+                       "      %f16 = OpTypeFloat 16\n"
+                       "      %f64 = OpTypeFloat 64\n"
+                       "    %v4f16 = OpTypeVector %f16 4\n"
+                       "    %v4f64 = OpTypeVector %f64 4\n"
+                       "    %v2f64 = OpTypeVector %f64 2\n"
+                       " %c_i32_16 = OpConstant %i32 16\n"
+                       " %a16v4f16 = OpTypeArray %v4f16 %c_i32_16\n"
+                       " %a16v4f64 = OpTypeArray %v4f64 %c_i32_16\n"
+                       " %pp_v4f16 = OpTypePointer PushConstant %v4f16\n"
+                       " %up_v4f64 = OpTypePointer Uniform %v4f64\n"
+                       "   %SSBO64 = OpTypeStruct %a16v4f64\n"
+                       "%up_SSBO64 = OpTypePointer Uniform %SSBO64\n"
+                       "   %ssbo64 = OpVariable %up_SSBO64 Uniform\n"
+                       "     %PC16 = OpTypeStruct %a16v4f16\n"
+                       "  %pp_PC16 = OpTypePointer PushConstant %PC16\n"
+                       "     %pc16 = OpVariable %pp_PC16 PushConstant\n";
+
+               fragments["decoration"]                         =
+                       "OpDecorate %a16v4f16 ArrayStride 8\n"
+                       "OpDecorate %a16v4f64 ArrayStride 32\n"
+                       "OpDecorate %SSBO64 BufferBlock\n"
+                       "OpMemberDecorate %SSBO64 0 Offset 0\n"
+                       "OpDecorate %PC16 Block\n"
+                       "OpMemberDecorate %PC16 0 Offset 0\n"
+                       "OpDecorate %ssbo64 DescriptorSet 0\n"
+                       "OpDecorate %ssbo64 Binding 0\n";
+
+               map<string, string>             specs;
+
+               specs["count"]                  = "%c_i32_16";
+               specs["pp_type16"]              = "%pp_v4f16";
+               specs["f_type16"]               = "%v4f16";
+               specs["f_type64"]               = "%v4f64";
+               specs["up_type64"]              = "%up_v4f64";
+
+               fragments["testfun"]    = testFun.specialize(specs);
+
+               createTestsForAllStages("vector", defaultColors, defaultColors, fragments, pcs, resources, extensions, testGroup, requiredFeatures);
+       }
+
+       {  // Matrix cases
+               fragments["pre_main"]                           =
+                       "  %c_i32_8 = OpConstant %i32 8\n"
+                       "      %f16 = OpTypeFloat 16\n"
+                       "    %v4f16 = OpTypeVector %f16 4\n"
+                       "      %f64 = OpTypeFloat 64\n"
+                       "    %v4f64 = OpTypeVector %f64 4\n"
+                       "  %m2v4f16 = OpTypeMatrix %v4f16 2\n"
+                       "  %m2v4f64 = OpTypeMatrix %v4f64 2\n"
+                       "%a8m2v4f16 = OpTypeArray %m2v4f16 %c_i32_8\n"
+                       "%a8m2v4f64 = OpTypeArray %m2v4f64 %c_i32_8\n"
+                       " %pp_v4f16 = OpTypePointer PushConstant %v4f16\n"
+                       " %up_v4f64 = OpTypePointer Uniform %v4f64\n"
+                       "   %SSBO64 = OpTypeStruct %a8m2v4f64\n"
+                       "%up_SSBO64 = OpTypePointer Uniform %SSBO64\n"
+                       "   %ssbo64 = OpVariable %up_SSBO64 Uniform\n"
+                       "     %PC16 = OpTypeStruct %a8m2v4f16\n"
+                       "  %pp_PC16 = OpTypePointer PushConstant %PC16\n"
+                       "     %pc16 = OpVariable %pp_PC16 PushConstant\n";
+
+               fragments["decoration"]                         =
+                       "OpDecorate %a8m2v4f16 ArrayStride 16\n"
+                       "OpDecorate %a8m2v4f64 ArrayStride 64\n"
+                       "OpDecorate %SSBO64 BufferBlock\n"
+                       "OpMemberDecorate %SSBO64 0 Offset 0\n"
+                       "OpMemberDecorate %SSBO64 0 ColMajor\n"
+                       "OpMemberDecorate %SSBO64 0 MatrixStride 32\n"
+                       "OpDecorate %PC16 Block\n"
+                       "OpMemberDecorate %PC16 0 Offset 0\n"
+                       "OpMemberDecorate %PC16 0 ColMajor\n"
+                       "OpMemberDecorate %PC16 0 MatrixStride 8\n"
+                       "OpDecorate %ssbo64 DescriptorSet 0\n"
+                       "OpDecorate %ssbo64 Binding 0\n";
+
+               map<string, string>             specs;
+
+               specs["count"]                  = "%c_i32_8";
+               specs["pp_type16"]              = "%pp_v4f16";
+               specs["up_type64"]              = "%up_v4f64";
+               specs["f_type16"]               = "%v4f16";
+               specs["f_type64"]               = "%v4f64";
+               specs["index0"]                 = "%c_i32_0";
+               specs["store"]                  =
+                       "  %src_1 = OpAccessChain %pp_v4f16 %pc16 %c_i32_0 %30 %c_i32_1\n"
+                       "%val16_1 = OpLoad %v4f16 %src_1\n"
+                       "%val64_1 = OpFConvert %v4f64 %val16_1\n"
+                       "  %dst_1 = OpAccessChain %up_v4f64 %ssbo64 %c_i32_0 %30 %c_i32_1\n"
+                       "           OpStore %dst_1 %val64_1\n";
+
+               fragments["testfun"]    = testFun.specialize(specs);
+
+               createTestsForAllStages("matrix", defaultColors, defaultColors, fragments, pcs, resources, extensions, testGroup, requiredFeatures);
+       }
+}
+
+void addCompute16bitStorageUniform64To16Group (tcu::TestCaseGroup* group)
+{
+       tcu::TestContext&                               testCtx                 = group->getTestContext();
+       de::Random                                              rnd                             (deStringHash(group->getName()));
+       const int                                               numElements             = 128;
+
+       const StringTemplate                    shaderTemplate  (
+               "OpCapability Shader\n"
+               "OpCapability ${capability}\n"
+               "OpCapability Float64\n"
+               "OpCapability Float16\n"
+               "OpExtension \"SPV_KHR_16bit_storage\"\n"
+               "OpMemoryModel Logical GLSL450\n"
+               "OpEntryPoint GLCompute %main \"main\" %id\n"
+               "OpExecutionMode %main LocalSize 1 1 1\n"
+               "OpDecorate %id BuiltIn GlobalInvocationId\n"
+
+               "${stride}\n"
+
+               "OpMemberDecorate %SSBO64 0 Offset 0\n"
+               "OpMemberDecorate %SSBO16 0 Offset 0\n"
+               "OpDecorate %SSBO64 ${storage}\n"
+               "OpDecorate %SSBO16 BufferBlock\n"
+               "OpDecorate %ssbo64 DescriptorSet 0\n"
+               "OpDecorate %ssbo16 DescriptorSet 0\n"
+               "OpDecorate %ssbo64 Binding 0\n"
+               "OpDecorate %ssbo16 Binding 1\n"
+
+               "${matrix_decor:opt}\n"
+
+               "${rounding:opt}\n"
+
+               "%bool      = OpTypeBool\n"
+               "%void      = OpTypeVoid\n"
+               "%voidf     = OpTypeFunction %void\n"
+               "%u32       = OpTypeInt 32 0\n"
+               "%i32       = OpTypeInt 32 1\n"
+               "%f32       = OpTypeFloat 32\n"
+               "%f64       = OpTypeFloat 64\n"
+               "%uvec3     = OpTypeVector %u32 3\n"
+               "%fvec3     = OpTypeVector %f32 3\n"
+               "%uvec3ptr  = OpTypePointer Input %uvec3\n"
+               "%i32ptr    = OpTypePointer Uniform %i32\n"
+               "%f64ptr    = OpTypePointer Uniform %f64\n"
+
+               "%zero      = OpConstant %i32 0\n"
+               "%c_i32_1   = OpConstant %i32 1\n"
+               "%c_i32_16  = OpConstant %i32 16\n"
+               "%c_i32_32  = OpConstant %i32 32\n"
+               "%c_i32_64  = OpConstant %i32 64\n"
+               "%c_i32_128 = OpConstant %i32 128\n"
+
+               "%i32arr    = OpTypeArray %i32 %c_i32_128\n"
+               "%f64arr    = OpTypeArray %f64 %c_i32_128\n"
+
+               "${types}\n"
+               "${matrix_types:opt}\n"
+
+               "%SSBO64    = OpTypeStruct %${matrix_prefix:opt}${base64}arr\n"
+               "%SSBO16    = OpTypeStruct %${matrix_prefix:opt}${base16}arr\n"
+               "%up_SSBO64 = OpTypePointer Uniform %SSBO64\n"
+               "%up_SSBO16 = OpTypePointer Uniform %SSBO16\n"
+               "%ssbo64    = OpVariable %up_SSBO64 Uniform\n"
+               "%ssbo16    = OpVariable %up_SSBO16 Uniform\n"
+
+               "%id        = OpVariable %uvec3ptr Input\n"
+
+               "%main      = OpFunction %void None %voidf\n"
+               "%label     = OpLabel\n"
+               "%idval     = OpLoad %uvec3 %id\n"
+               "%x         = OpCompositeExtract %u32 %idval 0\n"
+               "%inloc     = OpAccessChain %${base64}ptr %ssbo64 %zero %x ${index0:opt}\n"
+               "%val64     = OpLoad %${base64} %inloc\n"
+               "%val16     = ${convert} %${base16} %val64\n"
+               "%outloc    = OpAccessChain %${base16}ptr %ssbo16 %zero %x ${index0:opt}\n"
+               "             OpStore %outloc %val16\n"
+               "${matrix_store:opt}\n"
+               "             OpReturn\n"
+               "             OpFunctionEnd\n");
+
+       {  // Floats
+               const char                                              floatTypes[]    =
+                       "%f16       = OpTypeFloat 16\n"
+                       "%f16ptr    = OpTypePointer Uniform %f16\n"
+                       "%f16arr    = OpTypeArray %f16 %c_i32_128\n"
+                       "%v4f16     = OpTypeVector %f16 4\n"
+                       "%v4f64     = OpTypeVector %f64 4\n"
+                       "%v4f16ptr  = OpTypePointer Uniform %v4f16\n"
+                       "%v4f64ptr  = OpTypePointer Uniform %v4f64\n"
+                       "%v4f16arr  = OpTypeArray %v4f16 %c_i32_32\n"
+                       "%v4f64arr  = OpTypeArray %v4f64 %c_i32_32\n";
+
+               struct RndMode
+               {
+                       const char*                             name;
+                       const char*                             decor;
+                       VerifyIOFunc                    func;
+               };
+
+               const RndMode           rndModes[]              =
+               {
+                       {"rtz",                                         "OpDecorate %val16  FPRoundingMode RTZ",        computeCheck16BitFloats64<ROUNDINGMODE_RTZ>},
+                       {"rte",                                         "OpDecorate %val16  FPRoundingMode RTE",        computeCheck16BitFloats64<ROUNDINGMODE_RTE>},
+                       {"unspecified_rnd_mode",        "",                                                                                     computeCheck16BitFloats64<RoundingModeFlags(ROUNDINGMODE_RTE | ROUNDINGMODE_RTZ)>},
+               };
+
+               struct CompositeType
+               {
+                       const char*     name;
+                       const char*     base64;
+                       const char*     base16;
+                       const char*     strideStr;
+                       const char* stride64UBO;
+                       unsigned        padding64UBO;
+                       const char* stride64SSBO;
+                       unsigned        padding64SSBO;
+                       unsigned        count;
+               };
+
+               const CompositeType     cTypes[]        =
+               {
+                       {"scalar",      "f64",          "f16",          "OpDecorate %f16arr ArrayStride 2\nOpDecorate %f64arr ArrayStride ",                    "16",   8,      "8",    0,      numElements},
+                       {"vector",      "v4f64",        "v4f16",        "OpDecorate %v4f16arr ArrayStride 8\nOpDecorate %v4f64arr ArrayStride ",                "32",   0,      "32",   0,      numElements / 4},
+                       {"matrix",      "v4f64",        "v4f16",        "OpDecorate %m2v4f16arr ArrayStride 16\nOpDecorate %m2v4f64arr ArrayStride ",   "64",   0,      "64",   0,      numElements / 8},
+               };
+
+               vector<double>          float64Data                     = getFloat64s(rnd, numElements);
+               vector<deFloat16>       float16DummyData        (numElements, 0);
+
+               for (deUint32 capIdx = 0; capIdx < DE_LENGTH_OF_ARRAY(CAPABILITIES); ++capIdx)
+                       for (deUint32 tyIdx = 0; tyIdx < DE_LENGTH_OF_ARRAY(cTypes); ++tyIdx)
+                               for (deUint32 rndModeIdx = 0; rndModeIdx < DE_LENGTH_OF_ARRAY(rndModes); ++rndModeIdx)
+                               {
+                                       ComputeShaderSpec               spec;
+                                       map<string, string>             specs;
+                                       string                                  testName        = string(CAPABILITIES[capIdx].name) + "_" + cTypes[tyIdx].name + "_float_" + rndModes[rndModeIdx].name;
+                                       const bool                              isUBO           = CAPABILITIES[capIdx].dtype == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER;
+
+                                       specs["capability"]             = CAPABILITIES[capIdx].cap;
+                                       specs["storage"]                = CAPABILITIES[capIdx].decor;
+                                       specs["stride"]                 = cTypes[tyIdx].strideStr;
+                                       specs["base64"]                 = cTypes[tyIdx].base64;
+                                       specs["base16"]                 = cTypes[tyIdx].base16;
+                                       specs["rounding"]               = rndModes[rndModeIdx].decor;
+                                       specs["types"]                  = floatTypes;
+                                       specs["convert"]                = "OpFConvert";
+
+                                       if (isUBO)
+                                               specs["stride"] += cTypes[tyIdx].stride64UBO;
+                                       else
+                                               specs["stride"] += cTypes[tyIdx].stride64SSBO;
+
+                                       if (deStringEqual(cTypes[tyIdx].name, "matrix"))
+                                       {
+                                               if (strcmp(rndModes[rndModeIdx].name, "rtz") == 0)
+                                                       specs["rounding"] += "\nOpDecorate %val16_1  FPRoundingMode RTZ\n";
+                                               else if (strcmp(rndModes[rndModeIdx].name, "rte") == 0)
+                                                       specs["rounding"] += "\nOpDecorate %val16_1  FPRoundingMode RTE\n";
+
+                                               specs["index0"]                 = "%zero";
+                                               specs["matrix_prefix"]  = "m2";
+                                               specs["matrix_types"]   =
+                                                       "%m2v4f16 = OpTypeMatrix %v4f16 2\n"
+                                                       "%m2v4f64 = OpTypeMatrix %v4f64 2\n"
+                                                       "%m2v4f16arr = OpTypeArray %m2v4f16 %c_i32_16\n"
+                                                       "%m2v4f64arr = OpTypeArray %m2v4f64 %c_i32_16\n";
+                                               specs["matrix_decor"]   =
+                                                       "OpMemberDecorate %SSBO64 0 ColMajor\n"
+                                                       "OpMemberDecorate %SSBO64 0 MatrixStride 32\n"
+                                                       "OpMemberDecorate %SSBO16 0 ColMajor\n"
+                                                       "OpMemberDecorate %SSBO16 0 MatrixStride 8\n";
+                                               specs["matrix_store"]   =
+                                                       "%inloc_1  = OpAccessChain %v4f64ptr %ssbo64 %zero %x %c_i32_1\n"
+                                                       "%val64_1  = OpLoad %v4f64 %inloc_1\n"
+                                                       "%val16_1  = OpFConvert %v4f16 %val64_1\n"
+                                                       "%outloc_1 = OpAccessChain %v4f16ptr %ssbo16 %zero %x %c_i32_1\n"
+                                                       "            OpStore %outloc_1 %val16_1\n";
+                                       }
+
+                                       spec.assembly                   = shaderTemplate.specialize(specs);
+                                       spec.numWorkGroups              = IVec3(cTypes[tyIdx].count, 1, 1);
+                                       spec.verifyIO                   = rndModes[rndModeIdx].func;
+                                       const unsigned padding  = isUBO ? cTypes[tyIdx].padding64UBO : cTypes[tyIdx].padding64SSBO;
+
+                                       spec.inputs.push_back(Resource(BufferSp(new Float64Buffer(float64Data, padding)), CAPABILITIES[capIdx].dtype));
+                                       // We provided a custom verifyIO in the above in which inputs will be used for checking.
+                                       // So put dummy data in the expected values.
+                                       spec.outputs.push_back(BufferSp(new Float16Buffer(float16DummyData)));
+                                       spec.extensions.push_back("VK_KHR_16bit_storage");
+                                       spec.extensions.push_back("VK_KHR_shader_float16_int8");
+                                       spec.requestedVulkanFeatures = get16BitStorageFeatures(CAPABILITIES[capIdx].name);
+                                       const ComputeTestFeatures features = COMPUTE_TEST_USES_FLOAT64;
+                                       group->addChild(new SpvAsmComputeShaderCase(testCtx, testName.c_str(), testName.c_str(), spec, features));
+                               }
+       }
+}
+
+void addGraphics16BitStorageUniformFloat64To16Group (tcu::TestCaseGroup* testGroup)
+{
+       de::Random                                                      rnd                                     (deStringHash(testGroup->getName()));
+       map<string, string>                                     fragments;
+       GraphicsResources                                       resources;
+       vector<string>                                          extensions;
+       const deUint32                                          numDataPoints           = 256;
+       RGBA                                                            defaultColors[4];
+       vector<double>                                          float64Data                     = getFloat64s(rnd, numDataPoints);
+       vector<deFloat16>                                       float16DummyData        (numDataPoints, 0);
+       const StringTemplate                            capabilities            ("OpCapability Float64\n"
+                                                                                                                        "OpCapability Float16\n"
+                                                                                                                        "OpCapability ${cap}\n");
+       // We use a custom verifyIO to check the result via computing directly from inputs; the contents in outputs do not matter.
+       resources.outputs.push_back(Resource(BufferSp(new Float16Buffer(float16DummyData)), VK_DESCRIPTOR_TYPE_STORAGE_BUFFER));
+
+       extensions.push_back("VK_KHR_16bit_storage");
+       extensions.push_back("VK_KHR_shader_float16_int8");
+
+       fragments["extension"]  = "OpExtension \"SPV_KHR_16bit_storage\"";
+
+       struct RndMode
+       {
+               const char*                             name;
+               const char*                             decor;
+               VerifyIOFunc                    f;
+       };
+
+       getDefaultColors(defaultColors);
+
+       {  // scalar cases
+               fragments["pre_main"]                           =
+                       "      %f16 = OpTypeFloat 16\n"
+                       "      %f64 = OpTypeFloat 64\n"
+                       "%c_i32_256 = OpConstant %i32 256\n"
+                       "   %up_f64 = OpTypePointer Uniform %f64\n"
+                       "   %up_f16 = OpTypePointer Uniform %f16\n"
+                       "   %ra_f64 = OpTypeArray %f64 %c_i32_256\n"
+                       "   %ra_f16 = OpTypeArray %f16 %c_i32_256\n"
+                       "   %SSBO64 = OpTypeStruct %ra_f64\n"
+                       "   %SSBO16 = OpTypeStruct %ra_f16\n"
+                       "%up_SSBO64 = OpTypePointer Uniform %SSBO64\n"
+                       "%up_SSBO16 = OpTypePointer Uniform %SSBO16\n"
+                       "   %ssbo64 = OpVariable %up_SSBO64 Uniform\n"
+                       "   %ssbo16 = OpVariable %up_SSBO16 Uniform\n";
+
+               const StringTemplate decoration         (
+                       "OpDecorate %ra_f64 ArrayStride ${stride64}\n"
+                       "OpDecorate %ra_f16 ArrayStride 2\n"
+                       "OpMemberDecorate %SSBO64 0 Offset 0\n"
+                       "OpMemberDecorate %SSBO16 0 Offset 0\n"
+                       "OpDecorate %SSBO64 ${indecor}\n"
+                       "OpDecorate %SSBO16 BufferBlock\n"
+                       "OpDecorate %ssbo64 DescriptorSet 0\n"
+                       "OpDecorate %ssbo16 DescriptorSet 0\n"
+                       "OpDecorate %ssbo64 Binding 0\n"
+                       "OpDecorate %ssbo16 Binding 1\n"
+                       "${rounddecor}\n");
+
+               fragments["testfun"]                            =
+                       "%test_code = OpFunction %v4f32 None %v4f32_v4f32_function\n"
+                       "    %param = OpFunctionParameter %v4f32\n"
+
+                       "%entry = OpLabel\n"
+                       "    %i = OpVariable %fp_i32 Function\n"
+                       "         OpStore %i %c_i32_0\n"
+                       "         OpBranch %loop\n"
+
+                       " %loop = OpLabel\n"
+                       "   %15 = OpLoad %i32 %i\n"
+                       "   %lt = OpSLessThan %bool %15 %c_i32_256\n"
+                       "         OpLoopMerge %merge %inc None\n"
+                       "         OpBranchConditional %lt %write %merge\n"
+
+                       "%write = OpLabel\n"
+                       "   %30 = OpLoad %i32 %i\n"
+                       "  %src = OpAccessChain %up_f64 %ssbo64 %c_i32_0 %30\n"
+                       "%val64 = OpLoad %f64 %src\n"
+                       "%val16 = OpFConvert %f16 %val64\n"
+                       "  %dst = OpAccessChain %up_f16 %ssbo16 %c_i32_0 %30\n"
+                       "         OpStore %dst %val16\n"
+                       "         OpBranch %inc\n"
+
+                       "  %inc = OpLabel\n"
+                       "   %37 = OpLoad %i32 %i\n"
+                       "   %39 = OpIAdd %i32 %37 %c_i32_1\n"
+                       "         OpStore %i %39\n"
+                       "         OpBranch %loop\n"
+
+                       "%merge = OpLabel\n"
+                       "         OpReturnValue %param\n"
+
+                       "OpFunctionEnd\n";
+
+               const RndMode   rndModes[] =
+               {
+                       {"rtz",                                         "OpDecorate %val16  FPRoundingMode RTZ",        graphicsCheck16BitFloats64<ROUNDINGMODE_RTZ>},
+                       {"rte",                                         "OpDecorate %val16  FPRoundingMode RTE",        graphicsCheck16BitFloats64<ROUNDINGMODE_RTE>},
+                       {"unspecified_rnd_mode",        "",                                                                                     graphicsCheck16BitFloats64<RoundingModeFlags(ROUNDINGMODE_RTE | ROUNDINGMODE_RTZ)>},
+               };
+
+               for (deUint32 capIdx = 0; capIdx < DE_LENGTH_OF_ARRAY(CAPABILITIES); ++capIdx)
+                       for (deUint32 rndModeIdx = 0; rndModeIdx < DE_LENGTH_OF_ARRAY(rndModes); ++rndModeIdx)
+                       {
+                               map<string, string>     specs;
+                               string                          testName        = string(CAPABILITIES[capIdx].name) + "_scalar_float_" + rndModes[rndModeIdx].name;
+                               const bool                      isUBO           = CAPABILITIES[capIdx].dtype == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER;
+
+                               specs["cap"]                                    = CAPABILITIES[capIdx].cap;
+                               specs["indecor"]                                = CAPABILITIES[capIdx].decor;
+                               specs["rounddecor"]                             = rndModes[rndModeIdx].decor;
+                               specs["stride64"]                               = isUBO ? "16" : "8";
+
+                               fragments["capability"]                 = capabilities.specialize(specs);
+                               fragments["decoration"]                 = decoration.specialize(specs);
+
+                               resources.inputs.clear();
+                               resources.inputs.push_back(Resource(BufferSp(new Float64Buffer(float64Data, isUBO ? 8 : 0)), CAPABILITIES[capIdx].dtype));
+
+                               resources.verifyIO                              = rndModes[rndModeIdx].f;
+                               VulkanFeatures features = get16BitStorageFeatures(CAPABILITIES[capIdx].name);
+                               features.coreFeatures.shaderFloat64 = DE_TRUE;
+
+                               createTestsForAllStages(testName, defaultColors, defaultColors, fragments, resources, extensions, testGroup, features);
+                       }
+       }
+
+       {  // vector cases
+               fragments["pre_main"]                           =
+                       "      %f16 = OpTypeFloat 16\n"
+                       "      %f64 = OpTypeFloat 64\n"
+                       " %c_i32_64 = OpConstant %i32 64\n"
+                       "        %v4f16 = OpTypeVector %f16 4\n"
+                       "        %v4f64 = OpTypeVector %f64 4\n"
+                       " %up_v4f64 = OpTypePointer Uniform %v4f64\n"
+                       " %up_v4f16 = OpTypePointer Uniform %v4f16\n"
+                       " %ra_v4f64 = OpTypeArray %v4f64 %c_i32_64\n"
+                       " %ra_v4f16 = OpTypeArray %v4f16 %c_i32_64\n"
+                       "   %SSBO64 = OpTypeStruct %ra_v4f64\n"
+                       "   %SSBO16 = OpTypeStruct %ra_v4f16\n"
+                       "%up_SSBO64 = OpTypePointer Uniform %SSBO64\n"
+                       "%up_SSBO16 = OpTypePointer Uniform %SSBO16\n"
+                       "   %ssbo64 = OpVariable %up_SSBO64 Uniform\n"
+                       "   %ssbo16 = OpVariable %up_SSBO16 Uniform\n";
+
+               const StringTemplate decoration         (
+                       "OpDecorate %ra_v4f64 ArrayStride 32\n"
+                       "OpDecorate %ra_v4f16 ArrayStride 8\n"
+                       "OpMemberDecorate %SSBO64 0 Offset 0\n"
+                       "OpMemberDecorate %SSBO16 0 Offset 0\n"
+                       "OpDecorate %SSBO64 ${indecor}\n"
+                       "OpDecorate %SSBO16 BufferBlock\n"
+                       "OpDecorate %ssbo64 DescriptorSet 0\n"
+                       "OpDecorate %ssbo16 DescriptorSet 0\n"
+                       "OpDecorate %ssbo64 Binding 0\n"
+                       "OpDecorate %ssbo16 Binding 1\n"
+                       "${rounddecor}\n");
+
+               // ssbo16[] <- convert ssbo64[] to 16bit float
+               fragments["testfun"]                            =
+                       "%test_code = OpFunction %v4f32 None %v4f32_v4f32_function\n"
+                       "    %param = OpFunctionParameter %v4f32\n"
+
+                       "%entry = OpLabel\n"
+                       "    %i = OpVariable %fp_i32 Function\n"
+                       "         OpStore %i %c_i32_0\n"
+                       "         OpBranch %loop\n"
+
+                       " %loop = OpLabel\n"
+                       "   %15 = OpLoad %i32 %i\n"
+                       "   %lt = OpSLessThan %bool %15 %c_i32_64\n"
+                       "         OpLoopMerge %merge %inc None\n"
+                       "         OpBranchConditional %lt %write %merge\n"
+
+                       "%write = OpLabel\n"
+                       "   %30 = OpLoad %i32 %i\n"
+                       "  %src = OpAccessChain %up_v4f64 %ssbo64 %c_i32_0 %30\n"
+                       "%val64 = OpLoad %v4f64 %src\n"
+                       "%val16 = OpFConvert %v4f16 %val64\n"
+                       "  %dst = OpAccessChain %up_v4f16 %ssbo16 %c_i32_0 %30\n"
+                       "         OpStore %dst %val16\n"
+                       "         OpBranch %inc\n"
+
+                       "  %inc = OpLabel\n"
+                       "   %37 = OpLoad %i32 %i\n"
+                       "   %39 = OpIAdd %i32 %37 %c_i32_1\n"
+                       "         OpStore %i %39\n"
+                       "         OpBranch %loop\n"
+
+                       "%merge = OpLabel\n"
+                       "         OpReturnValue %param\n"
+
+                       "OpFunctionEnd\n";
+
+               const RndMode   rndModes[] =
+               {
+                       {"rtz",                                         "OpDecorate %val16  FPRoundingMode RTZ",        graphicsCheck16BitFloats64<ROUNDINGMODE_RTZ>},
+                       {"rte",                                         "OpDecorate %val16  FPRoundingMode RTE",        graphicsCheck16BitFloats64<ROUNDINGMODE_RTE>},
+                       {"unspecified_rnd_mode",        "",                                                                                     graphicsCheck16BitFloats64<RoundingModeFlags(ROUNDINGMODE_RTE | ROUNDINGMODE_RTZ)>},
+               };
+
+               for (deUint32 capIdx = 0; capIdx < DE_LENGTH_OF_ARRAY(CAPABILITIES); ++capIdx)
+                       for (deUint32 rndModeIdx = 0; rndModeIdx < DE_LENGTH_OF_ARRAY(rndModes); ++rndModeIdx)
+                       {
+                               map<string, string>     specs;
+                               string                          testName        = string(CAPABILITIES[capIdx].name) + "_vector_float_" + rndModes[rndModeIdx].name;
+
+                               specs["cap"]                                    = CAPABILITIES[capIdx].cap;
+                               specs["indecor"]                                = CAPABILITIES[capIdx].decor;
+                               specs["rounddecor"]                             = rndModes[rndModeIdx].decor;
+
+                               fragments["capability"]                 = capabilities.specialize(specs);
+                               fragments["decoration"]                 = decoration.specialize(specs);
+
+                               resources.inputs.clear();
+                               resources.inputs.push_back(Resource(BufferSp(new Float64Buffer(float64Data)), CAPABILITIES[capIdx].dtype));
+                               resources.verifyIO                              = rndModes[rndModeIdx].f;
+                               VulkanFeatures features = get16BitStorageFeatures(CAPABILITIES[capIdx].name);
+                               features.coreFeatures.shaderFloat64 = DE_TRUE;
+
+                               createTestsForAllStages(testName, defaultColors, defaultColors, fragments, resources, extensions, testGroup, features);
+                       }
+       }
+
+       {  // matrix cases
+               fragments["pre_main"]                           =
+                       "       %f16 = OpTypeFloat 16\n"
+                       "       %f64 = OpTypeFloat 64\n"
+                       "  %c_i32_16 = OpConstant %i32 16\n"
+                       "     %v4f16 = OpTypeVector %f16 4\n"
+                       "     %v4f64 = OpTypeVector %f64 4\n"
+                       "   %m4x4f64 = OpTypeMatrix %v4f64 4\n"
+                       "   %m4x4f16 = OpTypeMatrix %v4f16 4\n"
+                       "  %up_v4f64 = OpTypePointer Uniform %v4f64\n"
+                       "  %up_v4f16 = OpTypePointer Uniform %v4f16\n"
+                       "%a16m4x4f64 = OpTypeArray %m4x4f64 %c_i32_16\n"
+                       "%a16m4x4f16 = OpTypeArray %m4x4f16 %c_i32_16\n"
+                       "    %SSBO64 = OpTypeStruct %a16m4x4f64\n"
+                       "    %SSBO16 = OpTypeStruct %a16m4x4f16\n"
+                       " %up_SSBO64 = OpTypePointer Uniform %SSBO64\n"
+                       " %up_SSBO16 = OpTypePointer Uniform %SSBO16\n"
+                       "    %ssbo64 = OpVariable %up_SSBO64 Uniform\n"
+                       "    %ssbo16 = OpVariable %up_SSBO16 Uniform\n";
+
+               const StringTemplate decoration         (
+                       "OpDecorate %a16m4x4f64 ArrayStride 128\n"
+                       "OpDecorate %a16m4x4f16 ArrayStride 32\n"
+                       "OpMemberDecorate %SSBO64 0 Offset 0\n"
+                       "OpMemberDecorate %SSBO64 0 ColMajor\n"
+                       "OpMemberDecorate %SSBO64 0 MatrixStride 32\n"
+                       "OpMemberDecorate %SSBO16 0 Offset 0\n"
+                       "OpMemberDecorate %SSBO16 0 ColMajor\n"
+                       "OpMemberDecorate %SSBO16 0 MatrixStride 8\n"
+                       "OpDecorate %SSBO64 ${indecor}\n"
+                       "OpDecorate %SSBO16 BufferBlock\n"
+                       "OpDecorate %ssbo64 DescriptorSet 0\n"
+                       "OpDecorate %ssbo16 DescriptorSet 0\n"
+                       "OpDecorate %ssbo64 Binding 0\n"
+                       "OpDecorate %ssbo16 Binding 1\n"
+                       "${rounddecor}\n");
+
+               fragments["testfun"]                            =
+                       "%test_code = OpFunction %v4f32 None %v4f32_v4f32_function\n"
+                       "    %param = OpFunctionParameter %v4f32\n"
+
+                       "%entry = OpLabel\n"
+                       "    %i = OpVariable %fp_i32 Function\n"
+                       "         OpStore %i %c_i32_0\n"
+                       "         OpBranch %loop\n"
+
+                       " %loop = OpLabel\n"
+                       "   %15 = OpLoad %i32 %i\n"
+                       "   %lt = OpSLessThan %bool %15 %c_i32_16\n"
+                       "         OpLoopMerge %merge %inc None\n"
+                       "         OpBranchConditional %lt %write %merge\n"
+
+                       "  %write = OpLabel\n"
+                       "     %30 = OpLoad %i32 %i\n"
+                       "  %src_0 = OpAccessChain %up_v4f64 %ssbo64 %c_i32_0 %30 %c_i32_0\n"
+                       "  %src_1 = OpAccessChain %up_v4f64 %ssbo64 %c_i32_0 %30 %c_i32_1\n"
+                       "  %src_2 = OpAccessChain %up_v4f64 %ssbo64 %c_i32_0 %30 %c_i32_2\n"
+                       "  %src_3 = OpAccessChain %up_v4f64 %ssbo64 %c_i32_0 %30 %c_i32_3\n"
+                       "%val64_0 = OpLoad %v4f64 %src_0\n"
+                       "%val64_1 = OpLoad %v4f64 %src_1\n"
+                       "%val64_2 = OpLoad %v4f64 %src_2\n"
+                       "%val64_3 = OpLoad %v4f64 %src_3\n"
+                       "%val16_0 = OpFConvert %v4f16 %val64_0\n"
+                       "%val16_1 = OpFConvert %v4f16 %val64_1\n"
+                       "%val16_2 = OpFConvert %v4f16 %val64_2\n"
+                       "%val16_3 = OpFConvert %v4f16 %val64_3\n"
+                       "  %dst_0 = OpAccessChain %up_v4f16 %ssbo16 %c_i32_0 %30 %c_i32_0\n"
+                       "  %dst_1 = OpAccessChain %up_v4f16 %ssbo16 %c_i32_0 %30 %c_i32_1\n"
+                       "  %dst_2 = OpAccessChain %up_v4f16 %ssbo16 %c_i32_0 %30 %c_i32_2\n"
+                       "  %dst_3 = OpAccessChain %up_v4f16 %ssbo16 %c_i32_0 %30 %c_i32_3\n"
+                       "           OpStore %dst_0 %val16_0\n"
+                       "           OpStore %dst_1 %val16_1\n"
+                       "           OpStore %dst_2 %val16_2\n"
+                       "           OpStore %dst_3 %val16_3\n"
+                       "           OpBranch %inc\n"
+
+                       "  %inc = OpLabel\n"
+                       "   %37 = OpLoad %i32 %i\n"
+                       "   %39 = OpIAdd %i32 %37 %c_i32_1\n"
+                       "         OpStore %i %39\n"
+                       "         OpBranch %loop\n"
+
+                       "%merge = OpLabel\n"
+                       "         OpReturnValue %param\n"
+
+                       "OpFunctionEnd\n";
+
+               const RndMode   rndModes[] =
+               {
+                       {"rte",                                         "OpDecorate %val16_0  FPRoundingMode RTE\nOpDecorate %val16_1  FPRoundingMode RTE\nOpDecorate %val16_2  FPRoundingMode RTE\nOpDecorate %val16_3  FPRoundingMode RTE",   graphicsCheck16BitFloats64<ROUNDINGMODE_RTE>},
+                       {"rtz",                                         "OpDecorate %val16_0  FPRoundingMode RTZ\nOpDecorate %val16_1  FPRoundingMode RTZ\nOpDecorate %val16_2  FPRoundingMode RTZ\nOpDecorate %val16_3  FPRoundingMode RTZ",   graphicsCheck16BitFloats64<ROUNDINGMODE_RTZ>},
+                       {"unspecified_rnd_mode",        "",                                                                                                                                                                                                                                                                                                                                             graphicsCheck16BitFloats64<RoundingModeFlags(ROUNDINGMODE_RTE | ROUNDINGMODE_RTZ)>},
+               };
+
+               for (deUint32 capIdx = 0; capIdx < DE_LENGTH_OF_ARRAY(CAPABILITIES); ++capIdx)
+                       for (deUint32 rndModeIdx = 0; rndModeIdx < DE_LENGTH_OF_ARRAY(rndModes); ++rndModeIdx)
+                       {
+                               map<string, string>     specs;
+                               string                          testName        = string(CAPABILITIES[capIdx].name) + "_matrix_float_" + rndModes[rndModeIdx].name;
+
+                               specs["cap"]                                    = CAPABILITIES[capIdx].cap;
+                               specs["indecor"]                                = CAPABILITIES[capIdx].decor;
+                               specs["rounddecor"]                             = rndModes[rndModeIdx].decor;
+
+                               fragments["capability"]                 = capabilities.specialize(specs);
+                               fragments["decoration"]                 = decoration.specialize(specs);
+
+                               resources.inputs.clear();
+                               resources.inputs.push_back(Resource(BufferSp(new Float64Buffer(float64Data)), CAPABILITIES[capIdx].dtype));
+                               resources.verifyIO                              = rndModes[rndModeIdx].f;
+                               VulkanFeatures features = get16BitStorageFeatures(CAPABILITIES[capIdx].name);
+                               features.coreFeatures.shaderFloat64 = DE_TRUE;
+
+                               createTestsForAllStages(testName, defaultColors, defaultColors, fragments, resources, extensions, testGroup, features);
+                       }
+       }
+}
+
+void addGraphics16BitStorageInputOutputFloat64To16Group (tcu::TestCaseGroup* testGroup)
+{
+       de::Random                      rnd                                     (deStringHash(testGroup->getName()));
+       RGBA                            defaultColors[4];
+       vector<string>          extensions;
+       map<string, string>     fragments                       = passthruFragments();
+       const deUint32          numDataPoints           = 64;
+       vector<double>          float64Data                     = getFloat64s(rnd, numDataPoints);
+
+       extensions.push_back("VK_KHR_16bit_storage");
+       extensions.push_back("VK_KHR_shader_float16_int8");
+
+       fragments["capability"]                         =
+               "OpCapability StorageInputOutput16\n"
+               "OpCapability Float16\n"
+               "OpCapability Float64\n";
+       fragments["extension"]                          = "OpExtension \"SPV_KHR_16bit_storage\"\n";
+
+       getDefaultColors(defaultColors);
+
+       struct RndMode
+       {
+               const char*                             name;
+               const char*                             decor;
+               const char*                             decor_tessc;
+               RoundingModeFlags               flags;
+       };
+
+       const RndMode           rndModes[]              =
+       {
+               {"rtz",
+                "OpDecorate %ret0  FPRoundingMode RTZ\n",
+                "OpDecorate %ret1  FPRoundingMode RTZ\n"
+                "OpDecorate %ret2  FPRoundingMode RTZ\n",
+                ROUNDINGMODE_RTZ},
+               {"rte",
+                "OpDecorate %ret0  FPRoundingMode RTE\n",
+                "OpDecorate %ret1  FPRoundingMode RTE\n"
+                "OpDecorate %ret2  FPRoundingMode RTE\n",
+                 ROUNDINGMODE_RTE},
+               {"unspecified_rnd_mode",        "",             "",                     RoundingModeFlags(ROUNDINGMODE_RTE | ROUNDINGMODE_RTZ)},
+       };
+
+       struct Case
+       {
+               const char*     name;
+               const char*     interfaceOpFunc;
+               const char* postInterfaceOp;
+               const char* postInterfaceOpGeom;
+               const char* postInterfaceOpTessc;
+               const char*     preMain;
+               const char*     inputType;
+               const char*     outputType;
+               deUint32        numPerCase;
+               deUint32        numElements;
+       };
+
+       const Case      cases[]         =
+       {
+               { // Scalar cases
+                       "scalar",
+
+                       "%interface_op_func = OpFunction %f16 None %f16_f64_function\n"
+                       "        %io_param1 = OpFunctionParameter %f64\n"
+                       "            %entry = OpLabel\n"
+                       "                     OpReturnValue %f16_0\n"
+                       "                     OpFunctionEnd\n",
+
+                       "             %ret0 = OpFConvert %f16 %IF_input_val\n"
+                       "                OpStore %IF_output %ret0\n",
+
+                       "             %ret0 = OpFConvert %f16 %IF_input_val0\n"
+                       "                OpStore %IF_output %ret0\n",
+
+                       "             %ret0 = OpFConvert %f16 %IF_input_val0\n"
+                       "                OpStore %IF_output_ptr0 %ret0\n"
+                       "             %ret1 = OpFConvert %f16 %IF_input_val1\n"
+                       "                OpStore %IF_output_ptr1 %ret1\n"
+                       "             %ret2 = OpFConvert %f16 %IF_input_val2\n"
+                       "                OpStore %IF_output_ptr2 %ret2\n",
+
+                       "             %f16 = OpTypeFloat 16\n"
+                       "             %f64 = OpTypeFloat 64\n"
+                       "          %op_f16 = OpTypePointer Output %f16\n"
+                       "           %a3f16 = OpTypeArray %f16 %c_i32_3\n"
+                       "        %op_a3f16 = OpTypePointer Output %a3f16\n"
+                       "%f16_f64_function = OpTypeFunction %f16 %f64\n"
+                       "           %a3f64 = OpTypeArray %f64 %c_i32_3\n"
+                       "        %ip_a3f64 = OpTypePointer Input %a3f64\n"
+                       "          %ip_f64 = OpTypePointer Input %f64\n"
+                       "           %f16_0 = OpConstant %f16 0\n",
+
+                       "f64",
+                       "f16",
+                       4,
+                       1,
+               },
+               { // Vector cases
+                       "vector",
+
+                       "%interface_op_func = OpFunction %v2f16 None %v2f16_v2f64_function\n"
+                       "        %io_param1 = OpFunctionParameter %v2f64\n"
+                       "            %entry = OpLabel\n"
+                       "                     OpReturnValue %v2f16_0\n"
+                       "                     OpFunctionEnd\n",
+
+                       "             %ret0 = OpFConvert %v2f16 %IF_input_val\n"
+                       "                OpStore %IF_output %ret0\n",
+
+                       "             %ret0 = OpFConvert %v2f16 %IF_input_val0\n"
+                       "                OpStore %IF_output %ret0\n",
+
+                       "             %ret0 = OpFConvert %v2f16 %IF_input_val0\n"
+                       "                OpStore %IF_output_ptr0 %ret0\n"
+                       "             %ret1 = OpFConvert %v2f16 %IF_input_val1\n"
+                       "                OpStore %IF_output_ptr1 %ret1\n"
+                       "             %ret2 = OpFConvert %v2f16 %IF_input_val2\n"
+                       "                OpStore %IF_output_ptr2 %ret2\n",
+
+                       "                 %f16 = OpTypeFloat 16\n"
+                       "                 %f64 = OpTypeFloat 64\n"
+                       "               %v2f16 = OpTypeVector %f16 2\n"
+                       "               %v2f64 = OpTypeVector %f64 2\n"
+                       "            %op_v2f16 = OpTypePointer Output %v2f16\n"
+                       "             %a3v2f16 = OpTypeArray %v2f16 %c_i32_3\n"
+                       "          %op_a3v2f16 = OpTypePointer Output %a3v2f16\n"
+                       "%v2f16_v2f64_function = OpTypeFunction %v2f16 %v2f64\n"
+                       "             %a3v2f64 = OpTypeArray %v2f64 %c_i32_3\n"
+                       "          %ip_a3v2f64 = OpTypePointer Input %a3v2f64\n"
+                       "          %ip_v2f64 = OpTypePointer Input %v2f64\n"
+                       "               %f16_0 = OpConstant %f16 0\n"
+                       "             %v2f16_0 = OpConstantComposite %v2f16 %f16_0 %f16_0\n",
+
+                       "v2f64",
+                       "v2f16",
+                       2 * 4,
+                       2,
+               }
+       };
+
+       VulkanFeatures  requiredFeatures;
+       requiredFeatures.ext16BitStorage = EXT16BITSTORAGEFEATURES_INPUT_OUTPUT;
+       requiredFeatures.coreFeatures.shaderFloat64 = DE_TRUE;
+
+       for (deUint32 caseIdx = 0; caseIdx < DE_LENGTH_OF_ARRAY(cases); ++caseIdx)
+               for (deUint32 rndModeIdx = 0; rndModeIdx < DE_LENGTH_OF_ARRAY(rndModes); ++rndModeIdx)
+               {
+                       fragments["interface_op_func"]                  = cases[caseIdx].interfaceOpFunc;
+                       fragments["post_interface_op_frag"]             = cases[caseIdx].postInterfaceOp;
+                       fragments["post_interface_op_vert"]             = cases[caseIdx].postInterfaceOp;
+                       fragments["post_interface_op_geom"]             = cases[caseIdx].postInterfaceOpGeom;
+                       fragments["post_interface_op_tesse"]    = cases[caseIdx].postInterfaceOpGeom;
+                       fragments["post_interface_op_tessc"]    = cases[caseIdx].postInterfaceOpTessc;
+                       fragments["pre_main"]                                   = cases[caseIdx].preMain;
+                       fragments["decoration"]                                 = rndModes[rndModeIdx].decor;
+                       fragments["decoration_tessc"]                   = rndModes[rndModeIdx].decor_tessc;
+
+                       fragments["input_type"]                 = cases[caseIdx].inputType;
+                       fragments["output_type"]                = cases[caseIdx].outputType;
+
+                       GraphicsInterfaces      interfaces;
+                       const deUint32          numPerCase      = cases[caseIdx].numPerCase;
+                       vector<double>          subInputs       (numPerCase);
+                       vector<deFloat16>       subOutputs      (numPerCase);
+
+                       // The pipeline need this to call compare16BitFloat() when checking the result.
+                       interfaces.setRoundingMode(rndModes[rndModeIdx].flags);
+
+                       for (deUint32 caseNdx = 0; caseNdx < numDataPoints / numPerCase; ++caseNdx)
+                       {
+                               string                  testName        = string(cases[caseIdx].name) + numberToString(caseNdx) + "_" + rndModes[rndModeIdx].name;
+
+                               for (deUint32 numNdx = 0; numNdx < numPerCase; ++numNdx)
+                               {
+                                       subInputs[numNdx]       = float64Data[caseNdx * numPerCase + numNdx];
+                                       // We derive the expected result from inputs directly in the graphics pipeline.
+                                       subOutputs[numNdx]      = 0;
+                               }
+                               interfaces.setInputOutput(std::make_pair(IFDataType(cases[caseIdx].numElements, NUMBERTYPE_FLOAT64), BufferSp(new Float64Buffer(subInputs))),
+                                                                                 std::make_pair(IFDataType(cases[caseIdx].numElements, NUMBERTYPE_FLOAT16), BufferSp(new Float16Buffer(subOutputs))));
+                               createTestsForAllStages(testName, defaultColors, defaultColors, fragments, interfaces, extensions, testGroup, requiredFeatures);
+                       }
+               }
+}
+
+void addCompute16bitStorageUniform16To64Group (tcu::TestCaseGroup* group)
+{
+       tcu::TestContext&                               testCtx                 = group->getTestContext();
+       de::Random                                              rnd                             (deStringHash(group->getName()));
+       const int                                               numElements             = 128;
+
+       const StringTemplate                    shaderTemplate  (
+               "OpCapability Shader\n"
+               "OpCapability Float64\n"
+               "OpCapability Float16\n"
+               "OpCapability ${capability}\n"
+               "OpExtension \"SPV_KHR_16bit_storage\"\n"
+               "OpMemoryModel Logical GLSL450\n"
+               "OpEntryPoint GLCompute %main \"main\" %id\n"
+               "OpExecutionMode %main LocalSize 1 1 1\n"
+               "OpDecorate %id BuiltIn GlobalInvocationId\n"
+
+               "${stride}\n"
+
+               "OpMemberDecorate %SSBO64 0 Offset 0\n"
+               "OpMemberDecorate %SSBO16 0 Offset 0\n"
+               "OpDecorate %SSBO64 BufferBlock\n"
+               "OpDecorate %SSBO16 ${storage}\n"
+               "OpDecorate %ssbo64 DescriptorSet 0\n"
+               "OpDecorate %ssbo16 DescriptorSet 0\n"
+               "OpDecorate %ssbo64 Binding 1\n"
+               "OpDecorate %ssbo16 Binding 0\n"
+
+               "${matrix_decor:opt}\n"
+
+               "%bool      = OpTypeBool\n"
+               "%void      = OpTypeVoid\n"
+               "%voidf     = OpTypeFunction %void\n"
+               "%u32       = OpTypeInt 32 0\n"
+               "%i32       = OpTypeInt 32 1\n"
+               "%f64       = OpTypeFloat 64\n"
+               "%v3u32     = OpTypeVector %u32 3\n"
+               "%uvec3ptr  = OpTypePointer Input %v3u32\n"
+               "%i32ptr    = OpTypePointer Uniform %i32\n"
+               "%f64ptr    = OpTypePointer Uniform %f64\n"
+
+               "%zero      = OpConstant %i32 0\n"
+               "%c_i32_1   = OpConstant %i32 1\n"
+               "%c_i32_2   = OpConstant %i32 2\n"
+               "%c_i32_3   = OpConstant %i32 3\n"
+               "%c_i32_16  = OpConstant %i32 16\n"
+               "%c_i32_32  = OpConstant %i32 32\n"
+               "%c_i32_64  = OpConstant %i32 64\n"
+               "%c_i32_128 = OpConstant %i32 128\n"
+               "%c_i32_ci  = OpConstant %i32 ${constarrayidx}\n"
+
+               "%i32arr    = OpTypeArray %i32 %c_i32_128\n"
+               "%f64arr    = OpTypeArray %f64 %c_i32_128\n"
+
+               "${types}\n"
+               "${matrix_types:opt}\n"
+
+               "%SSBO64    = OpTypeStruct %${matrix_prefix:opt}${base64}arr\n"
+               "%SSBO16    = OpTypeStruct %${matrix_prefix:opt}${base16}arr\n"
+               "%up_SSBO64 = OpTypePointer Uniform %SSBO64\n"
+               "%up_SSBO16 = OpTypePointer Uniform %SSBO16\n"
+               "%ssbo64    = OpVariable %up_SSBO64 Uniform\n"
+               "%ssbo16    = OpVariable %up_SSBO16 Uniform\n"
+
+               "%id        = OpVariable %uvec3ptr Input\n"
+
+               "%main      = OpFunction %void None %voidf\n"
+               "%label     = OpLabel\n"
+               "%idval     = OpLoad %v3u32 %id\n"
+               "%x         = OpCompositeExtract %u32 %idval 0\n"
+               "%inloc     = OpAccessChain %${base16}ptr %ssbo16 %zero %${arrayindex} ${index0:opt}\n"
+               "%val16     = OpLoad %${base16} %inloc\n"
+               "%val64     = ${convert} %${base64} %val16\n"
+               "%outloc    = OpAccessChain %${base64}ptr %ssbo64 %zero %x ${index0:opt}\n"
+               "             OpStore %outloc %val64\n"
+               "${matrix_store:opt}\n"
+               "             OpReturn\n"
+               "             OpFunctionEnd\n");
+
+       {  // floats
+               const char                                                                              floatTypes[]    =
+                       "%f16       = OpTypeFloat 16\n"
+                       "%f16ptr    = OpTypePointer Uniform %f16\n"
+                       "%f16arr    = OpTypeArray %f16 %c_i32_128\n"
+                       "%v2f16     = OpTypeVector %f16 2\n"
+                       "%v2f64     = OpTypeVector %f64 2\n"
+                       "%v2f16ptr  = OpTypePointer Uniform %v2f16\n"
+                       "%v2f64ptr  = OpTypePointer Uniform %v2f64\n"
+                       "%v2f16arr  = OpTypeArray %v2f16 %c_i32_64\n"
+                       "%v2f64arr  = OpTypeArray %v2f64 %c_i32_64\n";
+
+               struct CompositeType
+               {
+                       const char*     name;
+                       const char*     base64;
+                       const char*     base16;
+                       const char*     strideStr;
+                       const char* stride16UBO;
+                       unsigned        padding16UBO;
+                       const char* stride16SSBO;
+                       unsigned        padding16SSBO;
+                       bool            useConstantIndex;
+                       unsigned        constantIndex;
+                       unsigned        count;
+               };
+
+               const CompositeType     cTypes[]        =
+               {
+                       {"scalar",                              "f64",          "f16",          "OpDecorate %f64arr ArrayStride 8\nOpDecorate %f16arr ArrayStride ",                    "16",   14,     "2",    0,      false,  0,      numElements},
+                       {"scalar_const_idx_5",  "f64",          "f16",          "OpDecorate %f64arr ArrayStride 8\nOpDecorate %f16arr ArrayStride ",                    "16",   14,     "2",    0,      true,   5,      numElements},
+                       {"scalar_const_idx_8",  "f64",          "f16",          "OpDecorate %f64arr ArrayStride 8\nOpDecorate %f16arr ArrayStride ",                    "16",   14,     "2",    0,      true,   8,      numElements},
+                       {"vector",                              "v2f64",        "v2f16",        "OpDecorate %v2f64arr ArrayStride 16\nOpDecorate %v2f16arr ArrayStride ",               "16",   12,     "4",    0,      false,  0,      numElements / 2},
+                       {"matrix",                              "v2f64",        "v2f16",        "OpDecorate %m4v2f64arr ArrayStride 64\nOpDecorate %m4v2f16arr ArrayStride ",   "16",   0, "16",        0,      false,  0,      numElements / 8},
+               };
+
+               vector<deFloat16>       float16Data                     = getFloat16s(rnd, numElements);
+               vector<double>          float64Data;
+
+               float64Data.reserve(numElements);
+               for (deUint32 numIdx = 0; numIdx < numElements; ++numIdx)
+                       float64Data.push_back(deFloat16To64(float16Data[numIdx]));
+
+               for (deUint32 capIdx = 0; capIdx < DE_LENGTH_OF_ARRAY(CAPABILITIES); ++capIdx)
+                       for (deUint32 tyIdx = 0; tyIdx < DE_LENGTH_OF_ARRAY(cTypes); ++tyIdx)
+                       {
+                               ComputeShaderSpec               spec;
+                               map<string, string>             specs;
+                               string                                  testName        = string(CAPABILITIES[capIdx].name) + "_" + cTypes[tyIdx].name + "_float";
+                               const bool                              isUBO           = CAPABILITIES[capIdx].dtype == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER;
+
+                               specs["capability"]             = CAPABILITIES[capIdx].cap;
+                               specs["storage"]                = CAPABILITIES[capIdx].decor;
+                               specs["stride"]                 = cTypes[tyIdx].strideStr;
+                               specs["base64"]                 = cTypes[tyIdx].base64;
+                               specs["base16"]                 = cTypes[tyIdx].base16;
+                               specs["types"]                  = floatTypes;
+                               specs["convert"]                = "OpFConvert";
+                               specs["constarrayidx"]  = de::toString(cTypes[tyIdx].constantIndex);
+
+                               if (isUBO)
+                                       specs["stride"] += cTypes[tyIdx].stride16UBO;
+                               else
+                                       specs["stride"] += cTypes[tyIdx].stride16SSBO;
+
+                               if (cTypes[tyIdx].useConstantIndex)
+                                       specs["arrayindex"] = "c_i32_ci";
+                               else
+                                       specs["arrayindex"] = "x";
+
+                               vector<double>                  float64DataConstIdx;
+                               if (cTypes[tyIdx].useConstantIndex)
+                               {
+                                       const deUint32 numFloats = numElements / cTypes[tyIdx].count;
+                                       for (deUint32 numIdx = 0; numIdx < numElements; ++numIdx)
+                                               float64DataConstIdx.push_back(float64Data[cTypes[tyIdx].constantIndex * numFloats + numIdx % numFloats]);
+                               }
+
+                               if (deStringEqual(cTypes[tyIdx].name, "matrix"))
+                               {
+                                       specs["index0"]                 = "%zero";
+                                       specs["matrix_prefix"]  = "m4";
+                                       specs["matrix_types"]   =
+                                               "%m4v2f16 = OpTypeMatrix %v2f16 4\n"
+                                               "%m4v2f64 = OpTypeMatrix %v2f64 4\n"
+                                               "%m4v2f16arr = OpTypeArray %m4v2f16 %c_i32_16\n"
+                                               "%m4v2f64arr = OpTypeArray %m4v2f64 %c_i32_16\n";
+                                       specs["matrix_decor"]   =
+                                               "OpMemberDecorate %SSBO64 0 ColMajor\n"
+                                               "OpMemberDecorate %SSBO64 0 MatrixStride 16\n"
+                                               "OpMemberDecorate %SSBO16 0 ColMajor\n"
+                                               "OpMemberDecorate %SSBO16 0 MatrixStride 4\n";
+                                       specs["matrix_store"]   =
+                                               "%inloc_1  = OpAccessChain %v2f16ptr %ssbo16 %zero %x %c_i32_1\n"
+                                               "%val16_1  = OpLoad %v2f16 %inloc_1\n"
+                                               "%val64_1  = OpFConvert %v2f64 %val16_1\n"
+                                               "%outloc_1 = OpAccessChain %v2f64ptr %ssbo64 %zero %x %c_i32_1\n"
+                                               "            OpStore %outloc_1 %val64_1\n"
+
+                                               "%inloc_2  = OpAccessChain %v2f16ptr %ssbo16 %zero %x %c_i32_2\n"
+                                               "%val16_2  = OpLoad %v2f16 %inloc_2\n"
+                                               "%val64_2  = OpFConvert %v2f64 %val16_2\n"
+                                               "%outloc_2 = OpAccessChain %v2f64ptr %ssbo64 %zero %x %c_i32_2\n"
+                                               "            OpStore %outloc_2 %val64_2\n"
+
+                                               "%inloc_3  = OpAccessChain %v2f16ptr %ssbo16 %zero %x %c_i32_3\n"
+                                               "%val16_3  = OpLoad %v2f16 %inloc_3\n"
+                                               "%val64_3  = OpFConvert %v2f64 %val16_3\n"
+                                               "%outloc_3 = OpAccessChain %v2f64ptr %ssbo64 %zero %x %c_i32_3\n"
+                                               "            OpStore %outloc_3 %val64_3\n";
+                               }
+
+                               spec.assembly                   = shaderTemplate.specialize(specs);
+                               spec.numWorkGroups              = IVec3(cTypes[tyIdx].count, 1, 1);
+                               spec.verifyIO                   = check64BitFloats;
+                               const unsigned padding  = isUBO ? cTypes[tyIdx].padding16UBO : cTypes[tyIdx].padding16SSBO;
+
+                               spec.inputs.push_back(Resource(BufferSp(new Float16Buffer(float16Data, padding)), CAPABILITIES[capIdx].dtype));
+                               spec.outputs.push_back(Resource(BufferSp(new Float64Buffer(cTypes[tyIdx].useConstantIndex ? float64DataConstIdx : float64Data))));
+                               spec.extensions.push_back("VK_KHR_16bit_storage");
+                               spec.extensions.push_back("VK_KHR_shader_float16_int8");
+                               spec.requestedVulkanFeatures = get16BitStorageFeatures(CAPABILITIES[capIdx].name);
+                               const ComputeTestFeatures features = COMPUTE_TEST_USES_FLOAT64;
+
+                               group->addChild(new SpvAsmComputeShaderCase(testCtx, testName.c_str(), testName.c_str(), spec, features));
+                       }
+       }
+}
+
+void addCompute16bitStoragePushConstant16To64Group (tcu::TestCaseGroup* group)
+{
+       tcu::TestContext&                               testCtx                 = group->getTestContext();
+       de::Random                                              rnd                             (deStringHash(group->getName()));
+       const int                                               numElements             = 64;
+
+       const StringTemplate                    shaderTemplate  (
+               "OpCapability Shader\n"
+               "OpCapability StoragePushConstant16\n"
+               "OpCapability Float64\n"
+               "OpCapability Float16\n"
+               "OpExtension \"SPV_KHR_16bit_storage\"\n"
+               "OpMemoryModel Logical GLSL450\n"
+               "OpEntryPoint GLCompute %main \"main\" %id\n"
+               "OpExecutionMode %main LocalSize 1 1 1\n"
+               "OpDecorate %id BuiltIn GlobalInvocationId\n"
+
+               "${stride}"
+
+               "OpDecorate %PC16 Block\n"
+               "OpMemberDecorate %PC16 0 Offset 0\n"
+               "OpMemberDecorate %SSBO64 0 Offset 0\n"
+               "OpDecorate %SSBO64 BufferBlock\n"
+               "OpDecorate %ssbo64 DescriptorSet 0\n"
+               "OpDecorate %ssbo64 Binding 0\n"
+
+               "${matrix_decor:opt}\n"
+
+               "%bool      = OpTypeBool\n"
+               "%void      = OpTypeVoid\n"
+               "%voidf     = OpTypeFunction %void\n"
+               "%u32       = OpTypeInt 32 0\n"
+               "%i32       = OpTypeInt 32 1\n"
+               "%f32       = OpTypeFloat 32\n"
+               "%uvec3     = OpTypeVector %u32 3\n"
+               "%fvec3     = OpTypeVector %f32 3\n"
+               "%uvec3ptr  = OpTypePointer Input %uvec3\n"
+               "%i32ptr    = OpTypePointer Uniform %i32\n"
+               "%f32ptr    = OpTypePointer Uniform %f32\n"
+
+               "%zero      = OpConstant %i32 0\n"
+               "%c_i32_1   = OpConstant %i32 1\n"
+               "%c_i32_8   = OpConstant %i32 8\n"
+               "%c_i32_16  = OpConstant %i32 16\n"
+               "%c_i32_32  = OpConstant %i32 32\n"
+               "%c_i32_64  = OpConstant %i32 64\n"
+
+               "%i32arr    = OpTypeArray %i32 %c_i32_64\n"
+               "%f32arr    = OpTypeArray %f32 %c_i32_64\n"
+
+               "${types}\n"
+               "${matrix_types:opt}\n"
+
+               "%PC16      = OpTypeStruct %${matrix_prefix:opt}${base16}arr\n"
+               "%pp_PC16   = OpTypePointer PushConstant %PC16\n"
+               "%pc16      = OpVariable %pp_PC16 PushConstant\n"
+               "%SSBO64    = OpTypeStruct %${matrix_prefix:opt}${base64}arr\n"
+               "%up_SSBO64 = OpTypePointer Uniform %SSBO64\n"
+               "%ssbo64    = OpVariable %up_SSBO64 Uniform\n"
+
+               "%id        = OpVariable %uvec3ptr Input\n"
+
+               "%main      = OpFunction %void None %voidf\n"
+               "%label     = OpLabel\n"
+               "%idval     = OpLoad %uvec3 %id\n"
+               "%x         = OpCompositeExtract %u32 %idval 0\n"
+               "%inloc     = OpAccessChain %${base16}ptr %pc16 %zero %x ${index0:opt}\n"
+               "%val16     = OpLoad %${base16} %inloc\n"
+               "%val64     = ${convert} %${base64} %val16\n"
+               "%outloc    = OpAccessChain %${base64}ptr %ssbo64 %zero %x ${index0:opt}\n"
+               "             OpStore %outloc %val64\n"
+               "${matrix_store:opt}\n"
+               "             OpReturn\n"
+               "             OpFunctionEnd\n");
+
+       {  // floats
+               const char                                                                              floatTypes[]    =
+                       "%f16       = OpTypeFloat 16\n"
+                       "%f16ptr    = OpTypePointer PushConstant %f16\n"
+                       "%f16arr    = OpTypeArray %f16 %c_i32_64\n"
+                       "%f64       = OpTypeFloat 64\n"
+                       "%f64ptr    = OpTypePointer Uniform %f64\n"
+                       "%f64arr    = OpTypeArray %f64 %c_i32_64\n"
+                       "%v4f16     = OpTypeVector %f16 4\n"
+                       "%v4f32     = OpTypeVector %f32 4\n"
+                       "%v4f64     = OpTypeVector %f64 4\n"
+                       "%v4f16ptr  = OpTypePointer PushConstant %v4f16\n"
+                       "%v4f32ptr  = OpTypePointer Uniform %v4f32\n"
+                       "%v4f64ptr  = OpTypePointer Uniform %v4f64\n"
+                       "%v4f16arr  = OpTypeArray %v4f16 %c_i32_16\n"
+                       "%v4f32arr  = OpTypeArray %v4f32 %c_i32_16\n"
+                       "%v4f64arr  = OpTypeArray %v4f64 %c_i32_16\n";
+
+               struct CompositeType
+               {
+                       const char*     name;
+                       const char*     base64;
+                       const char*     base16;
+                       const char*     stride;
+                       unsigned        count;
+               };
+
+               const CompositeType     cTypes[]        =
+               {
+                       {"scalar",      "f64",          "f16",          "OpDecorate %f64arr ArrayStride 8\nOpDecorate %f16arr ArrayStride 2\n",                         numElements},
+                       {"vector",      "v4f64",        "v4f16",        "OpDecorate %v4f64arr ArrayStride 32\nOpDecorate %v4f16arr ArrayStride 8\n",            numElements / 4},
+                       {"matrix",      "v4f64",        "v4f16",        "OpDecorate %m2v4f64arr ArrayStride 64\nOpDecorate %m2v4f16arr ArrayStride 16\n",       numElements / 8},
+               };
+
+               vector<deFloat16>       float16Data                     = getFloat16s(rnd, numElements);
+               vector<double>          float64Data;
+
+               float64Data.reserve(numElements);
+               for (deUint32 numIdx = 0; numIdx < numElements; ++numIdx)
+                       float64Data.push_back(deFloat16To64(float16Data[numIdx]));
+
+               for (deUint32 tyIdx = 0; tyIdx < DE_LENGTH_OF_ARRAY(cTypes); ++tyIdx)
+               {
+                       ComputeShaderSpec               spec;
+                       map<string, string>             specs;
+                       string                                  testName        = string(cTypes[tyIdx].name) + "_float";
+
+                       specs["stride"]                 = cTypes[tyIdx].stride;
+                       specs["base64"]                 = cTypes[tyIdx].base64;
+                       specs["base16"]                 = cTypes[tyIdx].base16;
+                       specs["types"]                  = floatTypes;
+                       specs["convert"]                = "OpFConvert";
+
+                       if (strcmp(cTypes[tyIdx].name, "matrix") == 0)
+                       {
+                               specs["index0"]                 = "%zero";
+                               specs["matrix_prefix"]  = "m2";
+                               specs["matrix_types"]   =
+                                       "%m2v4f16 = OpTypeMatrix %v4f16 2\n"
+                                       "%m2v4f64 = OpTypeMatrix %v4f64 2\n"
+                                       "%m2v4f16arr = OpTypeArray %m2v4f16 %c_i32_8\n"
+                                       "%m2v4f64arr = OpTypeArray %m2v4f64 %c_i32_8\n";
+                               specs["matrix_decor"]   =
+                                       "OpMemberDecorate %SSBO64 0 ColMajor\n"
+                                       "OpMemberDecorate %SSBO64 0 MatrixStride 32\n"
+                                       "OpMemberDecorate %PC16 0 ColMajor\n"
+                                       "OpMemberDecorate %PC16 0 MatrixStride 8\n";
+                               specs["matrix_store"]   =
+                                       "%inloc_1  = OpAccessChain %v4f16ptr %pc16 %zero %x %c_i32_1\n"
+                                       "%val16_1  = OpLoad %v4f16 %inloc_1\n"
+                                       "%val64_1  = OpFConvert %v4f64 %val16_1\n"
+                                       "%outloc_1 = OpAccessChain %v4f64ptr %ssbo64 %zero %x %c_i32_1\n"
+                                       "            OpStore %outloc_1 %val64_1\n";
+                       }
+
+                       spec.assembly                   = shaderTemplate.specialize(specs);
+                       spec.numWorkGroups              = IVec3(cTypes[tyIdx].count, 1, 1);
+                       spec.verifyIO                   = check64BitFloats;
+                       spec.pushConstants              = BufferSp(new Float16Buffer(float16Data));
+
+                       spec.outputs.push_back(BufferSp(new Float64Buffer(float64Data)));
+                       spec.extensions.push_back("VK_KHR_16bit_storage");
+                       spec.extensions.push_back("VK_KHR_shader_float16_int8");
+                       spec.requestedVulkanFeatures.ext16BitStorage = EXT16BITSTORAGEFEATURES_PUSH_CONSTANT;
+                       const ComputeTestFeatures features = COMPUTE_TEST_USES_FLOAT64;
+
+                       group->addChild(new SpvAsmComputeShaderCase(testCtx, testName.c_str(), testName.c_str(), spec, features));
+               }
+       }
+}
+
 } // anonymous
 
 tcu::TestCaseGroup* create16BitStorageComputeGroup (tcu::TestContext& testCtx)
 {
        de::MovePtr<tcu::TestCaseGroup> group           (new tcu::TestCaseGroup(testCtx, "16bit_storage", "Compute tests for VK_KHR_16bit_storage extension"));
+       addTestGroup(group.get(), "uniform_64_to_16", "64bit floats to 16bit tests under capability StorageUniform{|BufferBlock}", addCompute16bitStorageUniform64To16Group);
        addTestGroup(group.get(), "uniform_32_to_16", "32bit floats/ints to 16bit tests under capability StorageUniform{|BufferBlock}", addCompute16bitStorageUniform32To16Group);
        addTestGroup(group.get(), "uniform_16_to_32", "16bit floats/ints to 32bit tests under capability StorageUniform{|BufferBlock}", addCompute16bitStorageUniform16To32Group);
+       addTestGroup(group.get(), "uniform_16_to_64", "16bit floats to 64bit tests under capability StorageUniform{|BufferBlock}", addCompute16bitStorageUniform16To64Group);
        addTestGroup(group.get(), "push_constant_16_to_32", "16bit floats/ints to 32bit tests under capability StoragePushConstant16", addCompute16bitStoragePushConstant16To32Group);
+       addTestGroup(group.get(), "push_constant_16_to_64", "16bit floats to 64bit tests under capability StoragePushConstant16", addCompute16bitStoragePushConstant16To64Group);
        addTestGroup(group.get(), "uniform_16struct_to_32struct", "16bit floats struct to 32bit tests under capability StorageUniform{|BufferBlock}", addCompute16bitStorageUniform16StructTo32StructGroup);
        addTestGroup(group.get(), "uniform_32struct_to_16struct", "32bit floats struct to 16bit tests under capability StorageUniform{|BufferBlock}", addCompute16bitStorageUniform32StructTo16StructGroup);
        addTestGroup(group.get(), "struct_mixed_types", "mixed type of 8bit and 32bit struct", addCompute16bitStructMixedTypesGroup);
@@ -6449,17 +8430,22 @@ tcu::TestCaseGroup* create16BitStorageGraphicsGroup (tcu::TestContext& testCtx)
 {
        de::MovePtr<tcu::TestCaseGroup> group           (new tcu::TestCaseGroup(testCtx, "16bit_storage", "Graphics tests for VK_KHR_16bit_storage extension"));
 
+       addTestGroup(group.get(), "uniform_float_64_to_16", "64-bit floats into 16-bit tests under capability StorageUniform{|BufferBlock}16", addGraphics16BitStorageUniformFloat64To16Group);
        addTestGroup(group.get(), "uniform_float_32_to_16", "32-bit floats into 16-bit tests under capability StorageUniform{|BufferBlock}16", addGraphics16BitStorageUniformFloat32To16Group);
        addTestGroup(group.get(), "uniform_float_16_to_32", "16-bit floats into 32-bit testsunder capability StorageUniform{|BufferBlock}16", addGraphics16BitStorageUniformFloat16To32Group);
+       addTestGroup(group.get(), "uniform_float_16_to_64", "16-bit floats into 64-bit testsunder capability StorageUniform{|BufferBlock}16", addGraphics16BitStorageUniformFloat16To64Group);
        addTestGroup(group.get(), "uniform_int_32_to_16", "32-bit int into 16-bit tests under capability StorageUniform{|BufferBlock}16", addGraphics16BitStorageUniformInt32To16Group);
        addTestGroup(group.get(), "uniform_int_16_to_32", "16-bit int into 32-bit tests under capability StorageUniform{|BufferBlock}16", addGraphics16BitStorageUniformInt16To32Group);
+       addTestGroup(group.get(), "input_output_float_64_to_16", "64-bit floats into 16-bit tests under capability StorageInputOutput16", addGraphics16BitStorageInputOutputFloat64To16Group);
        addTestGroup(group.get(), "input_output_float_32_to_16", "32-bit floats into 16-bit tests under capability StorageInputOutput16", addGraphics16BitStorageInputOutputFloat32To16Group);
        addTestGroup(group.get(), "input_output_float_16_to_32", "16-bit floats into 32-bit tests under capability StorageInputOutput16", addGraphics16BitStorageInputOutputFloat16To32Group);
        addTestGroup(group.get(), "input_output_float_16_to_16", "16-bit floats pass-through tests under capability StorageInputOutput16", addGraphics16BitStorageInputOutputFloat16To16Group);
+       addTestGroup(group.get(), "input_output_float_16_to_64", "16-bit floats into 64-bit tests under capability StorageInputOutput16", addGraphics16BitStorageInputOutputFloat16To64Group);
        addTestGroup(group.get(), "input_output_int_32_to_16", "32-bit int into 16-bit tests under capability StorageInputOutput16", addGraphics16BitStorageInputOutputInt32To16Group);
        addTestGroup(group.get(), "input_output_int_16_to_32", "16-bit int into 32-bit tests under capability StorageInputOutput16", addGraphics16BitStorageInputOutputInt16To32Group);
        addTestGroup(group.get(), "input_output_int_16_to_16", "16-bit int into 16-bit tests under capability StorageInputOutput16", addGraphics16BitStorageInputOutputInt16To16Group);
        addTestGroup(group.get(), "push_constant_float_16_to_32", "16-bit floats into 32-bit tests under capability StoragePushConstant16", addGraphics16BitStoragePushConstantFloat16To32Group);
+       addTestGroup(group.get(), "push_constant_float_16_to_64", "16-bit floats into 64-bit tests under capability StoragePushConstant16", addGraphics16BitStoragePushConstantFloat16To64Group);
        addTestGroup(group.get(), "push_constant_int_16_to_32", "16-bit int into 32-bit tests under capability StoragePushConstant16", addGraphics16BitStoragePushConstantInt16To32Group);
        addTestGroup(group.get(), "uniform_16struct_to_32struct", "16-bit float struct into 32-bit tests under capability StorageUniform{|BufferBlock}16", addGraphics16BitStorageUniformStructFloat16To32Group);
        addTestGroup(group.get(), "uniform_32struct_to_16struct", "32-bit float struct into 16-bit tests under capability StorageUniform{|BufferBlock}16", addGraphics16BitStorageUniformStructFloat32To16Group);

diff --git a/external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsmComputeShaderTestUtil.hpp b/external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsmComputeShaderTestUtil.hpp
index 7f2c27c..66cf37d 100644 (file)
--- a/external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsmComputeShaderTestUtil.hpp
+++ b/external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsmComputeShaderTestUtil.hpp
@@ -312,6 +312,7 @@ DE_STATIC_ASSERT(sizeof(tcu::Vec4) == 4 * sizeof(float));
 
 typedef Buffer<float>          Float32Buffer;
 typedef Buffer<deFloat16>      Float16Buffer;
+typedef Buffer<double>     Float64Buffer;
 typedef Buffer<deInt64>                Int64Buffer;
 typedef Buffer<deInt32>                Int32Buffer;
 typedef Buffer<deInt16>                Int16Buffer;

diff --git a/external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsmGraphicsShaderTestUtil.cpp b/external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsmGraphicsShaderTestUtil.cpp
index 8d4dd11..8aac8c4 100644 (file)
--- a/external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsmGraphicsShaderTestUtil.cpp
+++ b/external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsmGraphicsShaderTestUtil.cpp
@@ -49,6 +49,7 @@ using std::string;
 using std::vector;
 using tcu::Float16;
 using tcu::Float32;
+using tcu::Float64;
 using tcu::IVec3;
 using tcu::IVec4;
 using tcu::RGBA;
@@ -64,7 +65,10 @@ deUint32 IFDataType::getElementNumBytes (void) const
        if (elementType < NUMBERTYPE_END32)
                return 4;
 
-       return 2;
+       if (elementType < NUMBERTYPE_END16)
+               return 2;
+
+       return 8;
 }
 
 VkFormat IFDataType::getVkFormat (void) const
@@ -73,6 +77,7 @@ VkFormat IFDataType::getVkFormat (void) const
        {
                switch (elementType)
                {
+                       case NUMBERTYPE_FLOAT64:        return VK_FORMAT_R64_SFLOAT;
                        case NUMBERTYPE_FLOAT32:        return VK_FORMAT_R32_SFLOAT;
                        case NUMBERTYPE_INT32:          return VK_FORMAT_R32_SINT;
                        case NUMBERTYPE_UINT32:         return VK_FORMAT_R32_UINT;
@@ -86,6 +91,7 @@ VkFormat IFDataType::getVkFormat (void) const
        {
                switch (elementType)
                {
+                       case NUMBERTYPE_FLOAT64:        return VK_FORMAT_R64G64_SFLOAT;
                        case NUMBERTYPE_FLOAT32:        return VK_FORMAT_R32G32_SFLOAT;
                        case NUMBERTYPE_INT32:          return VK_FORMAT_R32G32_SINT;
                        case NUMBERTYPE_UINT32:         return VK_FORMAT_R32G32_UINT;
@@ -99,6 +105,7 @@ VkFormat IFDataType::getVkFormat (void) const
        {
                switch (elementType)
                {
+                       case NUMBERTYPE_FLOAT64:        return VK_FORMAT_R64G64B64_SFLOAT;
                        case NUMBERTYPE_FLOAT32:        return VK_FORMAT_R32G32B32_SFLOAT;
                        case NUMBERTYPE_INT32:          return VK_FORMAT_R32G32B32_SINT;
                        case NUMBERTYPE_UINT32:         return VK_FORMAT_R32G32B32_UINT;
@@ -112,6 +119,7 @@ VkFormat IFDataType::getVkFormat (void) const
        {
                switch (elementType)
                {
+                       case NUMBERTYPE_FLOAT64:        return VK_FORMAT_R64G64B64A64_SFLOAT;
                        case NUMBERTYPE_FLOAT32:        return VK_FORMAT_R32G32B32A32_SFLOAT;
                        case NUMBERTYPE_INT32:          return VK_FORMAT_R32G32B32A32_SINT;
                        case NUMBERTYPE_UINT32:         return VK_FORMAT_R32G32B32A32_UINT;
@@ -133,6 +141,7 @@ tcu::TextureFormat IFDataType::getTextureFormat (void) const
 
        switch (elementType)
        {
+               case NUMBERTYPE_FLOAT64:        ct = tcu::TextureFormat::FLOAT64;                       break;
                case NUMBERTYPE_FLOAT32:        ct = tcu::TextureFormat::FLOAT;                         break;
                case NUMBERTYPE_INT32:          ct = tcu::TextureFormat::SIGNED_INT32;          break;
                case NUMBERTYPE_UINT32:         ct = tcu::TextureFormat::UNSIGNED_INT32;        break;
@@ -160,6 +169,7 @@ string IFDataType::str (void) const
 
        switch (elementType)
        {
+               case NUMBERTYPE_FLOAT64:        ret = "f64"; break;
                case NUMBERTYPE_FLOAT32:        ret = "f32"; break;
                case NUMBERTYPE_INT32:          ret = "i32"; break;
                case NUMBERTYPE_UINT32:         ret = "u32"; break;
@@ -1024,21 +1034,33 @@ map<string, string> passthruInterface (const IFDataType& data_type)
 
        if (!data_type.elementIs32bit())
        {
-               if (data_type.elementType == NUMBERTYPE_FLOAT16)
+               if (data_type.elementType == NUMBERTYPE_FLOAT64)
+               {
+                       fragments["capability"]         = "OpCapability Float64\n\n";
+                       fragments["pre_main"]   += "%f64 = OpTypeFloat 64\n";
+               }
+               else if (data_type.elementType == NUMBERTYPE_FLOAT16)
                {
+                       fragments["capability"]         = "OpCapability StorageInputOutput16\n";
+                       fragments["extension"]          = "OpExtension \"SPV_KHR_16bit_storage\"\n";
                        fragments["pre_main"]   += "%f16 = OpTypeFloat 16\n";
                }
                else if (data_type.elementType == NUMBERTYPE_INT16)
                {
+                       fragments["capability"]         = "OpCapability StorageInputOutput16\n";
+                       fragments["extension"]          = "OpExtension \"SPV_KHR_16bit_storage\"\n";
                        fragments["pre_main"]   += "%i16 = OpTypeInt 16 1\n";
                }
-               else
+               else if (data_type.elementType == NUMBERTYPE_UINT16)
                {
+                       fragments["capability"]         = "OpCapability StorageInputOutput16\n";
+                       fragments["extension"]          = "OpExtension \"SPV_KHR_16bit_storage\"\n";
                        fragments["pre_main"]   += "%u16 = OpTypeInt 16 0\n";
                }
-
-               fragments["capability"]         = "OpCapability StorageInputOutput16\n";
-               fragments["extension"]          = "OpExtension \"SPV_KHR_16bit_storage\"\n";
+               else
+               {
+                       DE_ASSERT(0 && "unhandled type");
+               }
 
                if (data_type.isVector())
                {
@@ -2167,6 +2189,69 @@ bool compare16BitFloat(deUint16 original, float returned, tcu::TestLog & log)
        return false;
 }
 
+bool compare16BitFloat64 (double original, deUint16 returned, RoundingModeFlags flags, tcu::TestLog& log)
+{
+       // We only support RTE, RTZ, or both.
+       DE_ASSERT(static_cast<int>(flags) > 0 && static_cast<int>(flags) < 4);
+
+       const Float64   originalFloat   (original);
+       const Float16   returnedFloat   (returned);
+
+       // Zero are turned into zero under both RTE and RTZ.
+       if (originalFloat.isZero())
+       {
+               if (returnedFloat.isZero())
+                       return true;
+
+               log << TestLog::Message << "Error: expected zero but returned " << returned << TestLog::EndMessage;
+               return false;
+       }
+
+       // Any denormalized value input into a shader may be flushed to 0.
+       if (originalFloat.isDenorm() && returnedFloat.isZero())
+               return true;
+
+       // Inf are always turned into Inf with the same sign, too.
+       if (originalFloat.isInf())
+       {
+               if (returnedFloat.isInf() && originalFloat.signBit() == returnedFloat.signBit())
+                       return true;
+
+               log << TestLog::Message << "Error: expected Inf but returned " << returned << TestLog::EndMessage;
+               return false;
+       }
+
+       // NaN are always turned into NaN, too.
+       if (originalFloat.isNaN())
+       {
+               if (returnedFloat.isNaN())
+                       return true;
+
+               log << TestLog::Message << "Error: expected NaN but returned " << returned << TestLog::EndMessage;
+               return false;
+       }
+
+       // Check all rounding modes
+       for (int bitNdx = 0; bitNdx < 2; ++bitNdx)
+       {
+               if ((flags & (1u << bitNdx)) == 0)
+                       continue;       // This rounding mode is not selected.
+
+               const Float16   expectedFloat   (deFloat64To16Round(original, deRoundingMode(bitNdx)));
+
+               // Any denormalized value potentially generated by any instruction in a shader may be flushed to 0.
+               if (expectedFloat.isDenorm() && returnedFloat.isZero())
+                       return true;
+
+               // If not matched in the above cases, they should have the same bit pattern.
+               if (expectedFloat.bits() == returnedFloat.bits())
+                       return true;
+       }
+
+       log << TestLog::Message << "Error: found unmatched 64-bit and 16-bit floats: " << originalFloat.bits() << " vs " << returned << TestLog::EndMessage;
+       return false;
+}
+
 bool compare32BitFloat (float expected, float returned, tcu::TestLog& log)
 {
        const Float32   expectedFloat   (expected);
@@ -2200,6 +2285,39 @@ bool compare32BitFloat (float expected, float returned, tcu::TestLog& log)
        return false;
 }
 
+bool compare64BitFloat (double expected, double returned, tcu::TestLog& log)
+{
+       const Float64   expectedDouble  (expected);
+       const Float64   returnedDouble  (returned);
+
+       // Any denormalized value potentially generated by any instruction in a shader may be flushed to 0.
+       if (expectedDouble.isDenorm() && returnedDouble.isZero())
+               return true;
+
+       {
+               const Float16   originalDouble  (deFloat64To16(expected));
+
+               // Any denormalized value input into a shader may be flushed to 0.
+               if (originalDouble.isDenorm() && returnedDouble.isZero())
+                       return true;
+       }
+
+       if (expectedDouble.isNaN())
+       {
+               if (returnedDouble.isNaN())
+                       return true;
+
+               log << TestLog::Message << "Error: expected NaN but returned " << returned << TestLog::EndMessage;
+               return false;
+       }
+
+       if (returned == expected)
+               return true;
+
+       log << TestLog::Message << "Error: found unmatched 64-bit float: expected " << expectedDouble.bits() << " vs. returned " << returnedDouble.bits() << TestLog::EndMessage;
+       return false;
+}
+
 Move<VkBuffer> createBufferForResource (const DeviceInterface& vk, const VkDevice vkDevice, const Resource& resource, deUint32 queueFamilyIndex)
 {
        const vk::VkDescriptorType resourceType = resource.getDescriptorType();
@@ -2440,6 +2558,12 @@ TestStatus runAndVerifyDefaultPipeline (Context& context, InstanceContext instan
                }
        }
 
+       // 64bit float feature
+       {
+               if (instance.requestedFeatures.coreFeatures.shaderFloat64 == DE_TRUE && features.shaderFloat64 == DE_FALSE)
+                       TCU_THROW(NotSupportedError, "Requested shaderFloat64 feature not supported");
+       }
+
        // fragment stores and atomics feature
        {
                if (features.fragmentStoresAndAtomics == DE_FALSE &&
@@ -3883,7 +4007,16 @@ TestStatus runAndVerifyDefaultPipeline (Context& context, InstanceContext instan
                                        if (expected[eleNdx] != actual[eleNdx])
                                                equal = false;
                        }
-                       else if (outputType.elementType == NUMBERTYPE_FLOAT16)
+                       else if (outputType.elementType == NUMBERTYPE_FLOAT16 && inputType.elementType == NUMBERTYPE_FLOAT64)
+                       {
+                               const double*           original        = static_cast<const double*>(inputData) + posNdx * outputType.numElements;
+                               const deFloat16*        actual          = static_cast<const deFloat16*>(fragOutputBufferAccess.getPixelPtr(x, y));
+
+                               for (deUint32 eleNdx = 0; eleNdx < outputType.numElements; ++eleNdx)
+                                       if (!compare16BitFloat64(original[eleNdx], actual[eleNdx], instance.interfaces.getRoundingMode(), context.getTestContext().getLog()))
+                                               equal = false;
+                       }
+                       else if (outputType.elementType == NUMBERTYPE_FLOAT16 && inputType.elementType == NUMBERTYPE_FLOAT32)
                        {
                                if (inputType.elementType == NUMBERTYPE_FLOAT16)
                                {
@@ -3922,6 +4055,15 @@ TestStatus runAndVerifyDefaultPipeline (Context& context, InstanceContext instan
                                        if (expected[eleNdx] != actual[eleNdx])
                                                equal = false;
                        }
+                       else if (outputType.elementType == NUMBERTYPE_FLOAT64)
+                       {
+                               const double*           expected        = static_cast<const double*>(outputData) + posNdx * outputType.numElements;
+                               const double*           actual          = static_cast<const double*>(fragOutputBufferAccess.getPixelPtr(x, y));
+
+                               for (deUint32 eleNdx = 0; eleNdx < outputType.numElements; ++eleNdx)
+                                       if (!compare64BitFloat(expected[eleNdx], actual[eleNdx], context.getTestContext().getLog()))
+                                               equal = false;
+                       }
                        else {
                                DE_ASSERT(0 && "unhandled type");
                        }

diff --git a/external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsmGraphicsShaderTestUtil.hpp b/external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsmGraphicsShaderTestUtil.hpp
index b53d2f9..3dd356d 100644 (file)
--- a/external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsmGraphicsShaderTestUtil.hpp
+++ b/external/vulkancts/modules/vulkan/spirv_assembly/vktSpvAsmGraphicsShaderTestUtil.hpp
@@ -67,6 +67,8 @@ enum NumberType
        NUMBERTYPE_INT16,
        NUMBERTYPE_UINT16,
        NUMBERTYPE_FLOAT16,
+       NUMBERTYPE_END16,               // Marks the end of 16-bit scalar types
+       NUMBERTYPE_FLOAT64,
 };
 
 typedef enum RoundingModeFlags_e
@@ -114,7 +116,7 @@ struct IFDataType
                                                        , elementType   (elementT)
                                                {
                                                        DE_ASSERT(numE > 0 && numE < 5);
-                                                       DE_ASSERT(elementT != NUMBERTYPE_END32);
+                                                       DE_ASSERT(elementT != NUMBERTYPE_END32 && elementT != NUMBERTYPE_END16);
                                                }
 
                                                IFDataType                      (const IFDataType& that)
@@ -132,6 +134,8 @@ struct IFDataType
        std::string                     str                                     (void) const;
 
        bool                            elementIs32bit          (void) const { return elementType < NUMBERTYPE_END32; }
+       bool                            elementIs64bit          (void) const { return elementType > NUMBERTYPE_END16; }
+
        bool                            isVector                        (void) const { return numElements > 1; }
 
        deUint32                        numElements;
@@ -612,6 +616,19 @@ bool compare16BitFloat (float original, deUint16 returned, RoundingModeFlags fla
 // * For the rest, require exactly the same bit pattern.
 bool compare16BitFloat (deUint16 returned, float original, tcu::TestLog& log);
 
+// Given the original 64-bit float value, computes the corresponding 16-bit
+// float value under the given rounding mode flags and compares with the
+// returned 16-bit float value. Returns true if they are considered as equal.
+//
+// The following equivalence criteria are respected:
+// * Positive and negative zeros are considered equivalent.
+// * Denormalized floats are allowed to be flushed to zeros, including
+//   * Inputted 64bit denormalized float
+//   * Generated 16bit denormalized float
+// * Different bit patterns of NaNs are allowed.
+// * For the rest, require exactly the same bit pattern.
+bool compare16BitFloat64 (double original, deUint16 returned, RoundingModeFlags flags, tcu::TestLog& log);
+
 // Compare the returned 32-bit float against its expected value.
 //
 // The following equivalence criteria are respected:
@@ -622,6 +639,16 @@ bool compare16BitFloat (deUint16 returned, float original, tcu::TestLog& log);
 // * For the rest, use C++ float equivalence check.
 bool compare32BitFloat (float expected, float returned, tcu::TestLog& log);
 
+// Compare the returned 64-bit float against its expected value.
+//
+// The following equivalence criteria are respected:
+// * Denormalized floats are allowed to be flushed to zeros, including
+//   * The expected value itself is a denormalized float
+//   * The expected value is a denormalized float if converted to 16bit
+// * Different bit patterns of NaNs/Infs are allowed.
+// * For the rest, use C++ float equivalence check.
+bool compare64BitFloat (double expected, double returned, tcu::TestLog& log);
+
 } // SpirVAssembly
 } // vkt
 

diff --git a/external/vulkancts/mustpass/1.1.2/vk-default-no-waivers.txt b/external/vulkancts/mustpass/1.1.2/vk-default-no-waivers.txt
index 2f2f33b..55ed947 100644 (file)
--- a/external/vulkancts/mustpass/1.1.2/vk-default-no-waivers.txt
+++ b/external/vulkancts/mustpass/1.1.2/vk-default-no-waivers.txt
@@ -212296,6 +212296,24 @@ dEQP-VK.spirv_assembly.instruction.compute.8bit_storage.uniform_8struct_to_32str
 dEQP-VK.spirv_assembly.instruction.compute.8bit_storage.storagebuffer_32struct_to_8struct.storage_buffer
 dEQP-VK.spirv_assembly.instruction.compute.8bit_storage.struct_mixed_types.storage_buffer
 dEQP-VK.spirv_assembly.instruction.compute.8bit_storage.struct_mixed_types.uniform
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_scalar_float_rtz
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_scalar_float_rte
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_scalar_float_unspecified_rnd_mode
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_vector_float_rtz
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_vector_float_rte
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_vector_float_unspecified_rnd_mode
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_matrix_float_rtz
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_matrix_float_rte
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_matrix_float_unspecified_rnd_mode
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_scalar_float_rtz
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_scalar_float_rte
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_scalar_float_unspecified_rnd_mode
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_vector_float_rtz
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_vector_float_rte
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_vector_float_unspecified_rnd_mode
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_matrix_float_rtz
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_matrix_float_rte
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_matrix_float_unspecified_rnd_mode
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_32_to_16.uniform_buffer_block_scalar_float_rtz
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_32_to_16.uniform_buffer_block_scalar_float_rte
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_32_to_16.uniform_buffer_block_scalar_float_unspecified_rnd_mode
@@ -212348,6 +212366,16 @@ dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_32.unifor
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_32.uniform_scalar_uint_const_idx_8
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_32.uniform_vector_sint
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_32.uniform_vector_uint
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_buffer_block_scalar_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_buffer_block_scalar_const_idx_5_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_buffer_block_scalar_const_idx_8_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_buffer_block_vector_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_buffer_block_matrix_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_scalar_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_scalar_const_idx_5_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_scalar_const_idx_8_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_vector_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_matrix_float
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_32.scalar_float
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_32.scalar_const_idx_5_float
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_32.scalar_const_idx_8_float
@@ -212361,6 +212389,9 @@ dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_32.
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_32.scalar_uint_const_idx_8
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_32.vector_sint
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_32.vector_uint
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_64.scalar_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_64.vector_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_64.matrix_float
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16struct_to_32struct.uniform_buffer_block
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16struct_to_32struct.uniform
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_32struct_to_16struct.uniform_buffer_block
@@ -214231,6 +214262,96 @@ dEQP-VK.spirv_assembly.instruction.graphics.8bit_storage.struct_mixed_types.unif
 dEQP-VK.spirv_assembly.instruction.graphics.8bit_storage.struct_mixed_types.uniform_tesse
 dEQP-VK.spirv_assembly.instruction.graphics.8bit_storage.struct_mixed_types.uniform_geom
 dEQP-VK.spirv_assembly.instruction.graphics.8bit_storage.struct_mixed_types.uniform_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_unspecified_rnd_mode_frag
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_32_to_16.uniform_buffer_block_scalar_float_rtz_vert
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_32_to_16.uniform_buffer_block_scalar_float_rtz_tessc
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_32_to_16.uniform_buffer_block_scalar_float_rtz_tesse
@@ -214411,6 +214532,96 @@ dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_32
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_32.uniform_matrix_float_tesse
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_32.uniform_matrix_float_geom
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_32.uniform_matrix_float_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_4_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_4_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_4_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_4_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_4_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_4_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_4_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_4_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_4_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_4_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_5_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_5_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_5_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_5_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_5_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_5_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_5_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_5_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_5_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_5_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_6_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_6_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_6_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_6_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_6_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_6_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_6_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_6_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_4_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_4_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_4_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_4_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_4_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_4_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_4_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_4_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_4_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_4_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_5_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_5_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_5_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_5_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_5_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_5_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_5_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_5_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_5_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_5_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_6_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_6_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_6_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_6_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_6_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_6_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_6_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_6_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_matrix_float_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_matrix_float_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_matrix_float_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_matrix_float_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_matrix_float_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_matrix_float_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_matrix_float_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_matrix_float_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_matrix_float_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_matrix_float_frag
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_int_32_to_16.uniform_buffer_block_scalar_sint_vert
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_int_32_to_16.uniform_buffer_block_scalar_sint_tessc
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_int_32_to_16.uniform_buffer_block_scalar_sint_tesse
@@ -214611,6 +214822,366 @@ dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_int_16_to_32.u
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_int_16_to_32.uniform_vector_uint_const_idx_6_tesse
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_int_16_to_32.uniform_vector_uint_const_idx_6_geom
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_int_16_to_32.uniform_vector_uint_const_idx_6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_unspecified_rnd_mode_frag
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_32_to_16.scalar0_rtz_vert
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_32_to_16.scalar0_rtz_tessc
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_32_to_16.scalar0_rtz_tesse
@@ -215211,6 +215782,126 @@ dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_16.vector7_tesse
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_16.vector7_geom
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_16.vector7_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar0_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar0_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar0_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar0_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar0_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar1_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar1_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar1_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar1_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar1_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar2_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar2_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar2_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar2_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar2_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar3_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar3_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar3_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar3_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar3_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar4_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar4_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar4_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar4_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar4_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar5_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar5_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar5_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar5_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar5_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar6_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar6_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar6_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar6_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar7_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar7_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar7_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar7_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar7_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar8_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar8_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar8_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar8_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar8_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar9_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar9_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar9_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar9_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar9_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar10_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar10_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar10_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar10_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar10_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar11_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar11_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar11_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar11_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar11_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar12_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar12_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar12_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar12_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar12_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar13_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar13_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar13_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar13_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar13_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar14_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar14_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar14_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar14_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar14_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar15_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar15_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar15_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar15_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar15_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector0_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector0_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector0_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector0_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector0_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector1_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector1_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector1_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector1_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector1_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector2_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector2_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector2_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector2_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector2_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector3_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector3_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector3_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector3_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector3_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector4_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector4_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector4_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector4_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector4_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector5_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector5_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector5_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector5_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector5_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector6_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector6_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector6_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector6_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector7_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector7_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector7_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector7_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector7_frag
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_int_32_to_16.scalar_sint0_vert
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_int_32_to_16.scalar_sint0_tessc
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_int_32_to_16.scalar_sint0_tesse
@@ -215871,6 +216562,21 @@ dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_32.matrix_const_idx_6_tesse
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_32.matrix_const_idx_6_geom
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_32.matrix_const_idx_6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.scalar_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.scalar_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.scalar_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.scalar_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.scalar_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.vector_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.vector_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.vector_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.vector_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.vector_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.matrix_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.matrix_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.matrix_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.matrix_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.matrix_frag
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_int_16_to_32.sint_scalar_vert
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_int_16_to_32.sint_scalar_tessc
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_int_16_to_32.sint_scalar_tesse

diff --git a/external/vulkancts/mustpass/1.1.2/vk-default.txt b/external/vulkancts/mustpass/1.1.2/vk-default.txt
index df6f926..13bd7de 100644 (file)
--- a/external/vulkancts/mustpass/1.1.2/vk-default.txt
+++ b/external/vulkancts/mustpass/1.1.2/vk-default.txt
@@ -212296,6 +212296,24 @@ dEQP-VK.spirv_assembly.instruction.compute.8bit_storage.uniform_8struct_to_32str
 dEQP-VK.spirv_assembly.instruction.compute.8bit_storage.storagebuffer_32struct_to_8struct.storage_buffer
 dEQP-VK.spirv_assembly.instruction.compute.8bit_storage.struct_mixed_types.storage_buffer
 dEQP-VK.spirv_assembly.instruction.compute.8bit_storage.struct_mixed_types.uniform
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_scalar_float_rtz
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_scalar_float_rte
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_scalar_float_unspecified_rnd_mode
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_vector_float_rtz
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_vector_float_rte
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_vector_float_unspecified_rnd_mode
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_matrix_float_rtz
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_matrix_float_rte
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_buffer_block_matrix_float_unspecified_rnd_mode
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_scalar_float_rtz
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_scalar_float_rte
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_scalar_float_unspecified_rnd_mode
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_vector_float_rtz
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_vector_float_rte
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_vector_float_unspecified_rnd_mode
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_matrix_float_rtz
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_matrix_float_rte
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_64_to_16.uniform_matrix_float_unspecified_rnd_mode
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_32_to_16.uniform_buffer_block_scalar_float_rtz
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_32_to_16.uniform_buffer_block_scalar_float_rte
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_32_to_16.uniform_buffer_block_scalar_float_unspecified_rnd_mode
@@ -212348,6 +212366,16 @@ dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_32.unifor
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_32.uniform_scalar_uint_const_idx_8
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_32.uniform_vector_sint
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_32.uniform_vector_uint
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_buffer_block_scalar_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_buffer_block_scalar_const_idx_5_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_buffer_block_scalar_const_idx_8_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_buffer_block_vector_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_buffer_block_matrix_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_scalar_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_scalar_const_idx_5_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_scalar_const_idx_8_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_vector_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16_to_64.uniform_matrix_float
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_32.scalar_float
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_32.scalar_const_idx_5_float
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_32.scalar_const_idx_8_float
@@ -212361,6 +212389,9 @@ dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_32.
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_32.scalar_uint_const_idx_8
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_32.vector_sint
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_32.vector_uint
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_64.scalar_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_64.vector_float
+dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.push_constant_16_to_64.matrix_float
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16struct_to_32struct.uniform_buffer_block
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_16struct_to_32struct.uniform
 dEQP-VK.spirv_assembly.instruction.compute.16bit_storage.uniform_32struct_to_16struct.uniform_buffer_block
@@ -214231,6 +214262,96 @@ dEQP-VK.spirv_assembly.instruction.graphics.8bit_storage.struct_mixed_types.unif
 dEQP-VK.spirv_assembly.instruction.graphics.8bit_storage.struct_mixed_types.uniform_tesse
 dEQP-VK.spirv_assembly.instruction.graphics.8bit_storage.struct_mixed_types.uniform_geom
 dEQP-VK.spirv_assembly.instruction.graphics.8bit_storage.struct_mixed_types.uniform_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_scalar_float_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_scalar_float_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_vector_float_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_vector_float_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_buffer_block_matrix_float_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_64_to_16.uniform_matrix_float_unspecified_rnd_mode_frag
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_32_to_16.uniform_buffer_block_scalar_float_rtz_vert
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_32_to_16.uniform_buffer_block_scalar_float_rtz_tessc
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_32_to_16.uniform_buffer_block_scalar_float_rtz_tesse
@@ -214411,6 +214532,96 @@ dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_32
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_32.uniform_matrix_float_tesse
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_32.uniform_matrix_float_geom
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_32.uniform_matrix_float_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_4_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_4_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_4_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_4_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_4_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_4_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_4_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_4_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_4_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_4_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_5_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_5_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_5_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_5_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_5_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_5_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_5_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_5_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_5_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_5_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_6_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_6_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_6_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_6_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_scalar_float_const_idx_6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_6_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_6_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_6_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_6_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_scalar_float_const_idx_6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_4_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_4_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_4_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_4_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_4_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_4_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_4_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_4_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_4_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_4_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_5_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_5_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_5_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_5_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_5_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_5_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_5_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_5_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_5_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_5_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_6_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_6_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_6_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_6_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_vector_float_const_idx_6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_6_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_6_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_6_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_6_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_vector_float_const_idx_6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_matrix_float_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_matrix_float_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_matrix_float_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_matrix_float_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_buffer_block_matrix_float_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_matrix_float_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_matrix_float_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_matrix_float_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_matrix_float_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_float_16_to_64.uniform_matrix_float_frag
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_int_32_to_16.uniform_buffer_block_scalar_sint_vert
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_int_32_to_16.uniform_buffer_block_scalar_sint_tessc
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_int_32_to_16.uniform_buffer_block_scalar_sint_tesse
@@ -214611,6 +214822,366 @@ dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_int_16_to_32.u
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_int_16_to_32.uniform_vector_uint_const_idx_6_tesse
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_int_16_to_32.uniform_vector_uint_const_idx_6_geom
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.uniform_int_16_to_32.uniform_vector_uint_const_idx_6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar0_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar1_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar2_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar3_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar4_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar5_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar6_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar7_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar8_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar9_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar10_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar11_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar12_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar13_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar14_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.scalar15_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rtz_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rtz_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rtz_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rtz_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rtz_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rte_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rte_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rte_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rte_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_rte_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector0_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector1_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector2_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector3_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector4_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector5_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector6_unspecified_rnd_mode_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_unspecified_rnd_mode_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_unspecified_rnd_mode_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_unspecified_rnd_mode_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_unspecified_rnd_mode_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_64_to_16.vector7_unspecified_rnd_mode_frag
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_32_to_16.scalar0_rtz_vert
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_32_to_16.scalar0_rtz_tessc
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_32_to_16.scalar0_rtz_tesse
@@ -215211,6 +215782,126 @@ dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_16.vector7_tesse
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_16.vector7_geom
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_16.vector7_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar0_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar0_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar0_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar0_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar0_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar1_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar1_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar1_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar1_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar1_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar2_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar2_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar2_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar2_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar2_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar3_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar3_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar3_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar3_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar3_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar4_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar4_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar4_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar4_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar4_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar5_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar5_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar5_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar5_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar5_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar6_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar6_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar6_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar6_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar7_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar7_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar7_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar7_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar7_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar8_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar8_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar8_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar8_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar8_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar9_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar9_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar9_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar9_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar9_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar10_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar10_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar10_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar10_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar10_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar11_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar11_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar11_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar11_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar11_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar12_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar12_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar12_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar12_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar12_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar13_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar13_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar13_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar13_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar13_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar14_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar14_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar14_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar14_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar14_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar15_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar15_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar15_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar15_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.scalar15_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector0_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector0_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector0_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector0_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector0_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector1_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector1_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector1_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector1_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector1_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector2_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector2_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector2_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector2_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector2_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector3_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector3_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector3_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector3_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector3_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector4_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector4_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector4_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector4_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector4_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector5_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector5_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector5_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector5_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector5_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector6_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector6_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector6_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector6_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector7_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector7_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector7_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector7_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_float_16_to_64.vector7_frag
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_int_32_to_16.scalar_sint0_vert
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_int_32_to_16.scalar_sint0_tessc
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_int_32_to_16.scalar_sint0_tesse
@@ -215871,6 +216562,21 @@ dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_32.matrix_const_idx_6_tesse
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_32.matrix_const_idx_6_geom
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_32.matrix_const_idx_6_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.scalar_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.scalar_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.scalar_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.scalar_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.scalar_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.vector_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.vector_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.vector_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.vector_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.vector_frag
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.matrix_vert
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.matrix_tessc
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.matrix_tesse
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.matrix_geom
+dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_float_16_to_64.matrix_frag
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_int_16_to_32.sint_scalar_vert
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_int_16_to_32.sint_scalar_tessc
 dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.push_constant_int_16_to_32.sint_scalar_tesse

diff --git a/framework/delibs/debase/deFloat16.c b/framework/delibs/debase/deFloat16.c
index e8a1057..dd195e9 100644 (file)
--- a/framework/delibs/debase/deFloat16.c
+++ b/framework/delibs/debase/deFloat16.c
@@ -99,6 +99,79 @@ deFloat16 deFloat32To16 (float val32)
        }
 }
 
+deFloat16 deFloat64To16 (double val64)
+{
+       deUint64        sign;
+       long            expotent;
+       deUint64        mantissa;
+       union
+       {
+               double          f;
+               deUint64        u;
+       } x;
+
+       x.f                     = val64;
+       sign            = (x.u >> 48u) & 0x00008000u;
+       expotent        = (long int)((x.u >> 52u) & 0x000007ffu) - (1023 - 15);
+       mantissa        = x.u & 0x00fffffffffffffu;
+
+       if (expotent <= 0)
+       {
+               if (expotent < -10)
+               {
+                       /* Rounds to zero. */
+                       return (deFloat16) sign;
+               }
+
+               /* Converted to denormalized half, add leading 1 to significand. */
+               mantissa = mantissa | 0x0010000000000000u;
+
+               /* Round mantissa to nearest (10+e) */
+               {
+                       deUint64 t = 43u - expotent;
+                       deUint64 a = (1u << (t - 1u)) - 1u;
+                       deUint64 b = (mantissa >> t) & 1u;
+
+                       mantissa = (mantissa + a + b) >> t;
+               }
+
+               return (deFloat16) (sign | mantissa);
+       }
+       else if (expotent == 0x7ff - (1023 - 15))
+       {
+               if (mantissa == 0u)
+               {
+                       /* InF */
+                       return (deFloat16) (sign | 0x7c00u);
+               }
+               else
+               {
+                       /* NaN */
+                       mantissa >>= 42u;
+                       return (deFloat16) (sign | 0x7c00u | mantissa | (mantissa == 0u));
+               }
+       }
+       else
+       {
+               /* Normalized float. */
+               mantissa = mantissa + 0x000001ffffffffffu + ((mantissa >> 42u) & 1u);
+
+               if (mantissa & 0x010000000000000u)
+               {
+                       /* Overflow in mantissa. */
+                       mantissa  = 0u;
+                       expotent += 1;
+               }
+
+               if (expotent > 30)
+               {
+                       return (deFloat16) (sign | 0x7c00u);
+               }
+
+               return (deFloat16) (sign | ((deUint32)expotent << 10u) | (mantissa >> 13u));
+       }
+}
+
 /*--------------------------------------------------------------------*//*!
  * \brief Round the given number `val` to nearest even by discarding
  *        the last `numBitsToDiscard` bits.
@@ -256,6 +329,163 @@ deFloat16 deFloat32To16Round (float val32, deRoundingMode mode)
        return (deFloat16) 0;
 }
 
+/*--------------------------------------------------------------------*//*!
+ * \brief Round the given number `val` to nearest even by discarding
+ *        the last `numBitsToDiscard` bits.
+ * \param val value to round
+ * \param numBitsToDiscard number of (least significant) bits to discard
+ * \return The rounded value with the last `numBitsToDiscard` removed
+ *//*--------------------------------------------------------------------*/
+static deUint64 roundToNearestEven64 (deUint64 val, const deUint64 numBitsToDiscard)
+{
+       const deUint64  lastBits        = val & (((deUint64)1 << numBitsToDiscard) - 1);
+       const deUint64  headBit         = val & ((deUint64)1 << (numBitsToDiscard - 1));
+
+       DE_ASSERT(numBitsToDiscard > 0 && numBitsToDiscard < 64);       /* Make sure no overflow. */
+       val >>= numBitsToDiscard;
+
+       if (headBit == 0)
+       {
+               return val;
+       }
+       else if (headBit == lastBits)
+       {
+               if ((val & 0x1) == 0x1)
+               {
+                       return val + 1;
+               }
+               else
+               {
+                       return val;
+               }
+       }
+       else
+       {
+               return val + 1;
+       }
+}
+
+deFloat16 deFloat64To16Round (double val64, deRoundingMode mode)
+{
+       union
+       {
+               double          f;              /* Interpret as 64-bit float */
+               deUint64        u;              /* Interpret as 64-bit unsigned integer */
+       } x;
+       deUint64        sign;           /* sign : 0000 0000 0000 0000 X000 0000 0000 0000 */
+       deUint64        exp64;          /* exp32: biased exponent for 64-bit floats */
+       int                     exp16;          /* exp16: biased exponent for 16-bit floats */
+       deUint64        mantissa;
+
+       /* We only support these two rounding modes for now */
+       DE_ASSERT(mode == DE_ROUNDINGMODE_TO_ZERO || mode == DE_ROUNDINGMODE_TO_NEAREST_EVEN);
+
+       x.f                     = val64;
+       sign            = (x.u >> 48u) & 0x00008000u;
+       exp64           = (x.u >> 52u) & 0x000007ffu;
+       exp16           = (int) (exp64) - 1023 + 15;    /* 15/127: exponent bias for 16-bit/32-bit floats */
+       mantissa        = x.u & 0x00fffffffffffffu;
+
+       /* Case: zero and denormalized floats */
+       if (exp64 == 0)
+       {
+               /* Denormalized floats are < 2^(1-1023), not representable in 16-bit floats, rounding to zero. */
+               return (deFloat16) sign;
+       }
+       /* Case: Inf and NaN */
+       else if (exp64 == 0x000007ffu)
+       {
+               if (mantissa == 0u)
+               {
+                       /* Inf */
+                       return (deFloat16) (sign | 0x7c00u);
+               }
+               else
+               {
+                       /* NaN */
+                       mantissa >>= 42u;       /* 16-bit floats has 10-bit for mantissa, 42-bit less than 64-bit floats. */
+                       /* Make sure we don't turn NaN into zero by | (mantissa == 0). */
+                       return (deFloat16) (sign | 0x7c00u | mantissa | (mantissa == 0u));
+               }
+       }
+       /* The following are cases for normalized floats.
+        *
+        * * If exp16 is less than 0, we are experiencing underflow for the exponent. To encode this underflowed exponent,
+        *   we can only shift the mantissa further right.
+        *   The real exponent is exp16 - 15. A denormalized 16-bit float can represent -14 via its exponent.
+        *   Note that the most significant bit in the mantissa of a denormalized float is already -1 as for exponent.
+        *   So, we just need to right shift the mantissa -exp16 bits.
+        * * If exp16 is 0, mantissa shifting requirement is similar to the above.
+        * * If exp16 is greater than 30 (0b11110), we are experiencing overflow for the exponent of 16-bit normalized floats.
+        */
+       /* Case: normalized floats -> zero */
+       else if (exp16 < -10)
+       {
+               /* 16-bit floats have only 10 bits for mantissa. Minimal 16-bit denormalized float is (2^-10) * (2^-14). */
+               /* Expecting a number < (2^-10) * (2^-14) here, not representable, round to zero. */
+               return (deFloat16) sign;
+       }
+       /* Case: normalized floats -> zero and denormalized halfs */
+       else if (exp16 <= 0)
+       {
+               /* Add the implicit leading 1 in mormalized float to mantissa. */
+               mantissa |= 0x0010000000000000u;
+               /* We have a (23 + 1)-bit mantissa, but 16-bit floats only expect 10-bit mantissa.
+                * Need to discard the last 14-bits considering rounding mode.
+                * We also need to shift right -exp16 bits to encode the underflowed exponent.
+                */
+               if (mode == DE_ROUNDINGMODE_TO_ZERO)
+               {
+                       mantissa >>= (43 - exp16);
+               }
+               else
+               {
+                       /* mantissa in the above may exceed 10-bits, in which case overflow happens.
+                        * The overflowed bit is automatically carried to exponent then.
+                        */
+                       mantissa = roundToNearestEven64(mantissa, 43 - exp16);
+               }
+               return (deFloat16) (sign | mantissa);
+       }
+       /* Case: normalized floats -> normalized floats */
+       else if (exp16 <= 30)
+       {
+               if (mode == DE_ROUNDINGMODE_TO_ZERO)
+               {
+                       return (deFloat16) (sign | ((deUint32)exp16 << 10u) | (mantissa >> 42u));
+               }
+               else
+               {
+                       mantissa        = roundToNearestEven64(mantissa, 42);
+                       /* Handle overflow. exp16 may overflow (and become Inf) itself, but that's correct. */
+                       exp16           = (exp16 << 10u) + (deFloat16)(mantissa & (1 << 10));
+                       mantissa        &= (1u << 10) - 1;
+                       return (deFloat16) (sign | ((deUint32) exp16) | mantissa);
+               }
+       }
+       /* Case: normalized floats (too large to be representable as 16-bit floats) */
+       else
+       {
+               /* According to IEEE Std 754-2008 Section 7.4,
+                * * roundTiesToEven and roundTiesToAway carry all overflows to Inf with the sign
+                *   of the intermediate  result.
+                * * roundTowardZero carries all overflows to the format’s largest finite number
+                *   with the sign of the intermediate result.
+                */
+               if (mode == DE_ROUNDINGMODE_TO_ZERO)
+               {
+                       return (deFloat16) (sign | 0x7bffu); /* 111 1011 1111 1111 */
+               }
+               else
+               {
+                       return (deFloat16) (sign | (0x1f << 10));
+               }
+       }
+
+       /* Make compiler happy */
+       return (deFloat16) 0;
+}
+
 float deFloat16To32 (deFloat16 val16)
 {
        deUint32 sign;
@@ -318,4 +548,66 @@ float deFloat16To32 (deFloat16 val16)
        return x.f;
 }
 
+double deFloat16To64 (deFloat16 val16)
+{
+       deUint64 sign;
+       deUint64 expotent;
+       deUint64 mantissa;
+       union
+       {
+               double          f;
+               deUint64        u;
+       } x;
+
+       x.u                     = 0u;
+
+       sign            = ((deUint32)val16 >> 15u) & 0x00000001u;
+       expotent        = ((deUint32)val16 >> 10u) & 0x0000001fu;
+       mantissa        = (deUint32)val16 & 0x000003ffu;
+
+       if (expotent == 0u)
+       {
+               if (mantissa == 0u)
+               {
+                       /* +/- 0 */
+                       x.u = sign << 63u;
+                       return x.f;
+               }
+               else
+               {
+                       /* Denormalized, normalize it. */
+
+                       while (!(mantissa & 0x00000400u))
+                       {
+                               mantissa <<= 1u;
+                               expotent -=  1u;
+                       }
+
+                       expotent += 1u;
+                       mantissa &= ~0x00000400u;
+               }
+       }
+       else if (expotent == 31u)
+       {
+               if (mantissa == 0u)
+               {
+                       /* +/- InF */
+                       x.u = (sign << 63u) | 0x7ff0000000000000u;
+                       return x.f;
+               }
+               else
+               {
+                       /* +/- NaN */
+                       x.u = (sign << 63u) | 0x7ff0000000000000u | (mantissa << 42u);
+                       return x.f;
+               }
+       }
+
+       expotent = expotent + (1023u - 15u);
+       mantissa = mantissa << 42u;
+
+       x.u = (sign << 63u) | (expotent << 52u) | mantissa;
+       return x.f;
+}
+
 DE_END_EXTERN_C

diff --git a/framework/delibs/debase/deFloat16.h b/framework/delibs/debase/deFloat16.h
index ab81199..576b1b7 100644 (file)
--- a/framework/delibs/debase/deFloat16.h
+++ b/framework/delibs/debase/deFloat16.h
@@ -43,6 +43,9 @@ deFloat16     deFloat32To16                           (float val32);
 deFloat16      deFloat32To16Round                      (float val32, deRoundingMode mode);
 void           deFloat16_selfTest                      (void);
 
+deFloat16      deFloat64To16                           (double val64);
+deFloat16      deFloat64To16Round                      (double val64, deRoundingMode mode);
+
 /*--------------------------------------------------------------------*//*!
  * \brief Convert 16-bit floating point number to 32 bit.
  * \param val16        Input value.
@@ -50,6 +53,12 @@ void         deFloat16_selfTest                      (void);
  *//*--------------------------------------------------------------------*/
 float          deFloat16To32           (deFloat16 val16);
 
+/*--------------------------------------------------------------------*//*!
+ * \brief Convert 16-bit floating point number to 64 bit.
+ * \param val16        Input value.
+ * \return Converted 64-bit floating-point value.
+ *//*--------------------------------------------------------------------*/
+double         deFloat16To64           (deFloat16 val16);
 DE_END_EXTERN_C
 
 #endif /* _DEFLOAT16_H */