+2009-07-10 David Daney <ddaney@caviumnetworks.com>
+
+ PR target/39079
+ * config.gcc (supported_defaults): Add synci.
+ (with_synci): Add validation.
+ (all_defaults): Add synci.
+ * config/mips/mips.md (clear_cache): Use TARGET_SYNCI instead of
+ ISA_HAS_SYNCI.
+ (synci): Same.
+ * config/mips/mips.opt (msynci): New option.
+ * config/mips/mips.c (mips_override_options): Warn on use of
+ -msynci for targets that do now support it.
+ * gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for
+ msynci.
+ * gcc/doc/invoke.texi (-msynci): Document the new option.
+ * doc/install.texi (--with-synci): Document the new option.
+
2009-07-10 Richard Guenther <rguenther@suse.de>
PR tree-optimization/40496
;;
mips*-*-*)
- supported_defaults="abi arch arch_32 arch_64 float tune tune_32 tune_64 divide llsc mips-plt"
+ supported_defaults="abi arch arch_32 arch_64 float tune tune_32 tune_64 divide llsc mips-plt synci"
case ${with_float} in
"" | soft | hard)
exit 1
;;
esac
+
+ case ${with_synci} in
+ yes)
+ with_synci=synci
+ ;;
+ "" | no)
+ # No is the default.
+ with_synci=no-synci
+ ;;
+ *)
+ echo "Unknown synci type used in --with-synci" 1>&2
+ exit 1
+ ;;
+ esac
;;
powerpc*-*-* | rs6000-*-*)
esac
t=
-all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu divide llsc mips-plt"
+all_defaults="abi cpu cpu_32 cpu_64 arch arch_32 arch_64 tune tune_32 tune_64 schedule float mode fpu divide llsc mips-plt synci"
for option in $all_defaults
do
eval "val=\$with_"`echo $option | sed s/-/_/g`
: !TARGET_BRANCHLIKELY))
sorry ("%qs requires branch-likely instructions", "-mfix-r10000");
+ if (TARGET_SYNCI && !ISA_HAS_SYNCI)
+ {
+ warning (0, "the %qs architecture does not support the synci "
+ "instruction", mips_arch_info->name);
+ target_flags &= ~MASK_SYNCI;
+ }
+
/* Save base state of options. */
mips_base_target_flags = target_flags;
mips_base_schedule_insns = flag_schedule_insns;
{"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \
{"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \
{"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \
- {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }
+ {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \
+ {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" }
/* A spec that infers the -mdsp setting from an -march argument. */
""
"
{
- if (ISA_HAS_SYNCI)
+ if (TARGET_SYNCI)
{
mips_expand_synci_loop (operands[0], operands[1]);
emit_insn (gen_sync ());
(define_insn "synci"
[(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")]
UNSPEC_SYNCI)]
- "ISA_HAS_SYNCI"
+ "TARGET_SYNCI"
"synci\t0(%0)")
(define_insn "rdhwr_synci_step_<mode>"
Target Report Var(TARGET_SYM32)
Assume all symbols have 32-bit values
+msynci
+Target Report Mask(SYNCI)
+Use synci instruction to invalidate i-cache
+
mtune=
Target RejectNegative Joined Var(mips_tune_string)
-mtune=PROCESSOR Optimize the output for PROCESSOR
On MIPS targets, make @option{-mno-llsc} the default when no
@option{-mllsc} option is passed.
+@item --with-synci
+On MIPS targets, make @option{-msynci} the default when no
+@option{-mno-synci} option is passed.
+
+@item --without-synci
+On MIPS targets, make @option{-mno-synci} the default when no
+@option{-msynci} option is passed. This is the default.
+
@item --with-mips-plt
On MIPS targets, make use of copy relocations and PLTs.
These features are extensions to the traditional
-mflush-func=@var{func} -mno-flush-func @gol
-mbranch-cost=@var{num} -mbranch-likely -mno-branch-likely @gol
-mfp-exceptions -mno-fp-exceptions @gol
--mvr4130-align -mno-vr4130-align}
+-mvr4130-align -mno-vr4130-align -msynci -mno-synci}
@emph{MMIX Options}
@gccoptlist{-mlibfuncs -mno-libfuncs -mepsilon -mno-epsilon -mabi=gnu @gol
This option only has an effect when optimizing for the VR4130.
It normally makes code faster, but at the expense of making it bigger.
It is enabled by default at optimization level @option{-O3}.
+
+@item -msynci
+@itemx -mno-synci
+@opindex msynci
+Enable (disable) generation of @code{synci} instructions on
+architectures that support it. The @code{synci} instructions (if
+enabled) will be generated when @code{__builtin___clear_cache()} is
+compiled.
+
+This option defaults to @code{-mno-synci}, but the default can be
+overridden by configuring with @code{--with-synci}.
+
+When compiling code for single processor systems, it is generally safe
+to use @code{synci}. However, on many multi-core (SMP) systems, it
+will not invalidate the instruction caches on all cores and may lead
+to undefined behavior.
@end table
@node MMIX Options
+2009-07-10 David Daney <ddaney@caviumnetworks.com>
+
+ PR target/39079
+ * testsuite/gcc.target/mips/mips.exp: Make -msynci a known option.
+ * gcc.target/mips/clear-cache-1.c (dg-options): Add -msynci.
+
2009-07-10 Jakub Jelinek <jakub@redhat.com>
PR c++/40502
/* { dg-do compile } */
-/* { dg-options "-O2 isa_rev>=2" } */
+/* { dg-options "-O2 -msynci isa_rev>=2" } */
/* { dg-final { scan-assembler "synci" } } */
/* { dg-final { scan-assembler "jr.hb" } } */
/* { dg-final { scan-assembler-not "_flush_cache" } } */
shared
smartmips
sym32
+ synci
} {
lappend mips_option_groups $option "-m(no-|)$option"
}