Reduce noise in a6xx.xml by removing LO/HI versions of address registers.
Also fix type="address" registers in register packing (use bit size instead
of checking for "waddress" to use qword)
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8423>
00000000 0xc00: 00000000
00000001 VSC_ADDR_MODE_CNTL: ADDR_64B
00000101 VSC_BIN_SIZE: { WIDTH = 32 | HEIGHT = 16 }
- 00000000 VSC_DRAW_STRM_SIZE_ADDRESS_LO: 0
+ 00000000 VSC_DRAW_STRM_SIZE_ADDRESS: 0
00000000 VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0
00000000 VSC_BIN_COUNT: { NX = 0 | NY = 0 }
00000000 VSC_PIPE_CONFIG[0].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
00000000 VSC_PIPE_CONFIG[0x1d].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
00000000 VSC_PIPE_CONFIG[0x1e].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
00000000 VSC_PIPE_CONFIG[0x1f].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
- 00000000 VSC_PRIM_STRM_ADDRESS_LO: 0
+ 00000000 VSC_PRIM_STRM_ADDRESS: 0
00000000 VSC_PRIM_STRM_ADDRESS_HI: 0
00000000 VSC_PRIM_STRM_PITCH: 0
00000000 VSC_PRIM_STRM_LIMIT: 0
- 00000000 VSC_DRAW_STRM_ADDRESS_LO: 0
+ 00000000 VSC_DRAW_STRM_ADDRESS: 0
00000000 VSC_DRAW_STRM_ADDRESS_HI: 0
00000000 VSC_DRAW_STRM_PITCH: 0
00000000 VSC_DRAW_STRM_LIMIT: 0
00000000 0x9e05: 00000000
00000000 0x9e06: 00000000
00000000 0x9e07: 00000000
- 00000000 PC_TESSFACTOR_ADDR_LO: 0
+ 00000000 PC_TESSFACTOR_ADDR: 0
00000000 PC_TESSFACTOR_ADDR_HI: 0
00000001 0x9e0a: 00000001
00004080 0x9e0b: 00004080
00000000 0x9e0e: 00000000
00010000 PC_VSTREAM_CONTROL: { VSC_SIZE = 1 | VSC_N = 0 }
00000000 PC_BIN_PRIM_STRM: 0
- 00000000 PC_BIN_PRIM_STRM+0x1: 0
+ 00000000 PC_BIN_PRIM_STRM_HI: 0
00000000 PC_BIN_DRAW_STRM: 0
- 00000000 PC_BIN_DRAW_STRM+0x1: 0
+ 00000000 PC_BIN_DRAW_STRM_HI: 0
00000000 0x9e16: 00000000
00000000 0x9e19: 00000000
00000000 0x9e1c: 00000000
00000000 GRAS_LRZ_CNTL: { 0 }
00000000 GRAS_UNKNOWN_8101: 0
00000000 GRAS_2D_BLIT_INFO: { COLOR_FORMAT = 0 }
- 00000000 GRAS_LRZ_BUFFER_BASE_LO: 0
+ 00000000 GRAS_LRZ_BUFFER_BASE: 0
00000000 GRAS_LRZ_BUFFER_BASE_HI: 0
00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO: 0
+ 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0
00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0
00000000 GRAS_SAMPLE_CNTL: { 0 }
00000000 GRAS_UNKNOWN_8110: 0
00000000 GRAS_LRZ_CNTL: { 0 }
00000000 GRAS_UNKNOWN_8101: 0
00000000 GRAS_2D_BLIT_INFO: { COLOR_FORMAT = 0 }
- 00000000 GRAS_LRZ_BUFFER_BASE_LO: 0
+ 00000000 GRAS_LRZ_BUFFER_BASE: 0
00000000 GRAS_LRZ_BUFFER_BASE_HI: 0
00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO: 0
+ 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0
00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0
00000000 GRAS_SAMPLE_CNTL: { 0 }
00000000 GRAS_UNKNOWN_8110: 0
00000000 RB_MRT[0].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX }
00000000 RB_MRT[0].PITCH: 0
00000000 RB_MRT[0].ARRAY_PITCH: 0
- 00000000 RB_MRT[0].BASE_LO: 0
+ 00000000 RB_MRT[0].BASE: 0
00000000 RB_MRT[0].BASE_HI: 0
00000000 RB_MRT[0].BASE_GMEM: 0
00000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 }
00000000 RB_MRT[0x1].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX }
00000000 RB_MRT[0x1].PITCH: 0
00000000 RB_MRT[0x1].ARRAY_PITCH: 0
- 00000000 RB_MRT[0x1].BASE_LO: 0
+ 00000000 RB_MRT[0x1].BASE: 0
00000000 RB_MRT[0x1].BASE_HI: 0
00000000 RB_MRT[0x1].BASE_GMEM: 0
00000000 RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 }
00000000 RB_MRT[0x2].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX }
00000000 RB_MRT[0x2].PITCH: 0
00000000 RB_MRT[0x2].ARRAY_PITCH: 0
- 00000000 RB_MRT[0x2].BASE_LO: 0
+ 00000000 RB_MRT[0x2].BASE: 0
00000000 RB_MRT[0x2].BASE_HI: 0
00000000 RB_MRT[0x2].BASE_GMEM: 0
00000000 RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 }
00000000 RB_MRT[0x3].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX }
00000000 RB_MRT[0x3].PITCH: 0
00000000 RB_MRT[0x3].ARRAY_PITCH: 0
- 00000000 RB_MRT[0x3].BASE_LO: 0
+ 00000000 RB_MRT[0x3].BASE: 0
00000000 RB_MRT[0x3].BASE_HI: 0
00000000 RB_MRT[0x3].BASE_GMEM: 0
00000000 RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 }
00000000 RB_MRT[0x4].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX }
00000000 RB_MRT[0x4].PITCH: 0
00000000 RB_MRT[0x4].ARRAY_PITCH: 0
- 00000000 RB_MRT[0x4].BASE_LO: 0
+ 00000000 RB_MRT[0x4].BASE: 0
00000000 RB_MRT[0x4].BASE_HI: 0
00000000 RB_MRT[0x4].BASE_GMEM: 0
00000000 RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 }
00000000 RB_MRT[0x5].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX }
00000000 RB_MRT[0x5].PITCH: 0
00000000 RB_MRT[0x5].ARRAY_PITCH: 0
- 00000000 RB_MRT[0x5].BASE_LO: 0
+ 00000000 RB_MRT[0x5].BASE: 0
00000000 RB_MRT[0x5].BASE_HI: 0
00000000 RB_MRT[0x5].BASE_GMEM: 0
00000000 RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 }
00000000 RB_MRT[0x6].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX }
00000000 RB_MRT[0x6].PITCH: 0
00000000 RB_MRT[0x6].ARRAY_PITCH: 0
- 00000000 RB_MRT[0x6].BASE_LO: 0
+ 00000000 RB_MRT[0x6].BASE: 0
00000000 RB_MRT[0x6].BASE_HI: 0
00000000 RB_MRT[0x6].BASE_GMEM: 0
00000000 RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 }
00000000 RB_MRT[0x7].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX }
00000000 RB_MRT[0x7].PITCH: 0
00000000 RB_MRT[0x7].ARRAY_PITCH: 0
- 00000000 RB_MRT[0x7].BASE_LO: 0
+ 00000000 RB_MRT[0x7].BASE: 0
00000000 RB_MRT[0x7].BASE_HI: 0
00000000 RB_MRT[0x7].BASE_GMEM: 0
00000000 RB_BLEND_RED_F32: 0.000000
00000000 RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
00000000 RB_DEPTH_BUFFER_PITCH: 0
00000000 RB_DEPTH_BUFFER_ARRAY_PITCH: 0
- 00000000 RB_DEPTH_BUFFER_BASE_LO: 0
+ 00000000 RB_DEPTH_BUFFER_BASE: 0
00000000 RB_DEPTH_BUFFER_BASE_HI: 0
00000000 RB_DEPTH_BUFFER_BASE_GMEM: 0
00000000 RB_Z_BOUNDS_MIN: 0.000000
00000000 RB_STENCIL_INFO: { 0 }
00000000 RB_STENCIL_BUFFER_PITCH: 0
00000000 RB_STENCIL_BUFFER_ARRAY_PITCH: 0
- 00000000 RB_STENCIL_BUFFER_BASE_LO: 0
+ 00000000 RB_STENCIL_BUFFER_BASE: 0
00000000 RB_STENCIL_BUFFER_BASE_HI: 0
00000000 RB_STENCIL_BUFFER_BASE_GMEM: 0
00000000 RB_STENCILREF: { REF = 0 | BFREF = 0 }
00000000 RB_BLIT_BASE_GMEM: 0
00004100 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_32_32_32_32_FLOAT }
00000000 RB_BLIT_DST: 0
- 00000000 RB_BLIT_DST+0x1: 0
+ 00000000 RB_BLIT_DST_HI: 0
00000000 RB_BLIT_DST_PITCH: 0
00000000 RB_BLIT_DST_ARRAY_PITCH: 0
00000000 RB_BLIT_FLAG_DST: 0
- 00000000 RB_BLIT_FLAG_DST+0x1: 0
+ 00000000 RB_BLIT_FLAG_DST_HI: 0
00000000 RB_BLIT_FLAG_DST_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
00000000 RB_BLIT_CLEAR_COLOR_DW0: 0
00000000 RB_BLIT_CLEAR_COLOR_DW1: 0
00000000 RB_BLIT_CLEAR_COLOR_DW2: 0
00000000 RB_BLIT_CLEAR_COLOR_DW3: 0
000000f2 RB_BLIT_INFO: { GMEM | CLEAR_MASK = 0xf }
- 00000000 RB_DEPTH_FLAG_BUFFER_BASE_LO: 0
+ 00000000 RB_DEPTH_FLAG_BUFFER_BASE: 0
00000000 RB_DEPTH_FLAG_BUFFER_BASE_HI: 0
00000000 RB_DEPTH_FLAG_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_LO: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0].ADDR: 0
00000000 RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0
00000000 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- 00000000 RB_MRT_FLAG_BUFFER[0x1].ADDR_LO: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0x1].ADDR: 0
00000000 RB_MRT_FLAG_BUFFER[0x1].ADDR_HI: 0
00000000 RB_MRT_FLAG_BUFFER[0x1].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- 00000000 RB_MRT_FLAG_BUFFER[0x2].ADDR_LO: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0x2].ADDR: 0
00000000 RB_MRT_FLAG_BUFFER[0x2].ADDR_HI: 0
00000000 RB_MRT_FLAG_BUFFER[0x2].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- 00000000 RB_MRT_FLAG_BUFFER[0x3].ADDR_LO: 0
- 00000000 RB_MRT_FLAG_BUFFER[0x4].ADDR_LO: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0x3].ADDR: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0x4].ADDR: 0
00000000 RB_MRT_FLAG_BUFFER[0x4].ADDR_HI: 0
00000000 RB_MRT_FLAG_BUFFER[0x4].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- 00000000 RB_MRT_FLAG_BUFFER[0x5].ADDR_LO: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0x5].ADDR: 0
00000000 RB_MRT_FLAG_BUFFER[0x5].ADDR_HI: 0
00000000 RB_MRT_FLAG_BUFFER[0x5].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- 00000000 RB_MRT_FLAG_BUFFER[0x6].ADDR_LO: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0x6].ADDR: 0
00000000 RB_MRT_FLAG_BUFFER[0x6].ADDR_HI: 0
00000000 RB_MRT_FLAG_BUFFER[0x6].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- 00000000 RB_MRT_FLAG_BUFFER[0x7].ADDR_LO: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0x7].ADDR: 0
00000000 RB_MRT_FLAG_BUFFER[0x7].ADDR_HI: 0
00000000 RB_MRT_FLAG_BUFFER[0x7].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
00000000 RB_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_RAW }
00000000 0x8c0f: 00000000
00000000 0x8c10: 00000000
00000000 RB_2D_DST_INFO: { COLOR_FORMAT = 0 | TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX | SAMPLES = MSAA_ONE }
- 00000000 RB_2D_DST_LO: 0
+ 00000000 RB_2D_DST: 0
00000000 RB_2D_DST_HI: 0
00000000 RB_2D_DST_PITCH: 0
00000000 RB_2D_DST_PLANE1: 0
- 00000000 RB_2D_DST_PLANE1+0x1: 0
+ 00000000 RB_2D_DST_PLANE1_HI: 0
00000000 RB_2D_DST_PLANE_PITCH: 0
00000000 RB_2D_DST_PLANE2: 0
- 00000000 RB_2D_DST_PLANE2+0x1: 0
+ 00000000 RB_2D_DST_PLANE2_HI: 0
00000000 0x8c26: 00000000
00000000 0x8c27: 00000000
00000000 0x8c28: 00000000
00000000 RB_MRT[0].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX }
00000000 RB_MRT[0].PITCH: 0
00000000 RB_MRT[0].ARRAY_PITCH: 0
- 00000000 RB_MRT[0].BASE_LO: 0
+ 00000000 RB_MRT[0].BASE: 0
00000000 RB_MRT[0].BASE_HI: 0
00000000 RB_MRT[0].BASE_GMEM: 0
00000000 RB_MRT[0x1].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 }
00000000 RB_MRT[0x1].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX }
00000000 RB_MRT[0x1].PITCH: 0
00000000 RB_MRT[0x1].ARRAY_PITCH: 0
- 00000000 RB_MRT[0x1].BASE_LO: 0
+ 00000000 RB_MRT[0x1].BASE: 0
00000000 RB_MRT[0x1].BASE_HI: 0
00000000 RB_MRT[0x1].BASE_GMEM: 0
00000000 RB_MRT[0x2].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 }
00000000 RB_MRT[0x2].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX }
00000000 RB_MRT[0x2].PITCH: 0
00000000 RB_MRT[0x2].ARRAY_PITCH: 0
- 00000000 RB_MRT[0x2].BASE_LO: 0
+ 00000000 RB_MRT[0x2].BASE: 0
00000000 RB_MRT[0x2].BASE_HI: 0
00000000 RB_MRT[0x2].BASE_GMEM: 0
00000000 RB_MRT[0x3].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 }
00000000 RB_MRT[0x3].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX }
00000000 RB_MRT[0x3].PITCH: 0
00000000 RB_MRT[0x3].ARRAY_PITCH: 0
- 00000000 RB_MRT[0x3].BASE_LO: 0
+ 00000000 RB_MRT[0x3].BASE: 0
00000000 RB_MRT[0x3].BASE_HI: 0
00000000 RB_MRT[0x3].BASE_GMEM: 0
00000000 RB_MRT[0x4].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 }
00000000 RB_MRT[0x4].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX }
00000000 RB_MRT[0x4].PITCH: 0
00000000 RB_MRT[0x4].ARRAY_PITCH: 0
- 00000000 RB_MRT[0x4].BASE_LO: 0
+ 00000000 RB_MRT[0x4].BASE: 0
00000000 RB_MRT[0x4].BASE_HI: 0
00000000 RB_MRT[0x4].BASE_GMEM: 0
00000000 RB_MRT[0x5].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 }
00000000 RB_MRT[0x5].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX }
00000000 RB_MRT[0x5].PITCH: 0
00000000 RB_MRT[0x5].ARRAY_PITCH: 0
- 00000000 RB_MRT[0x5].BASE_LO: 0
+ 00000000 RB_MRT[0x5].BASE: 0
00000000 RB_MRT[0x5].BASE_HI: 0
00000000 RB_MRT[0x5].BASE_GMEM: 0
00000000 RB_MRT[0x6].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 }
00000000 RB_MRT[0x6].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX }
00000000 RB_MRT[0x6].PITCH: 0
00000000 RB_MRT[0x6].ARRAY_PITCH: 0
- 00000000 RB_MRT[0x6].BASE_LO: 0
+ 00000000 RB_MRT[0x6].BASE: 0
00000000 RB_MRT[0x6].BASE_HI: 0
00000000 RB_MRT[0x6].BASE_GMEM: 0
00000000 RB_MRT[0x7].CONTROL: { ROP_CODE = ROP_CLEAR | COMPONENT_ENABLE = 0 }
00000000 RB_MRT[0x7].BUF_INFO: { COLOR_FORMAT = 0 | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX }
00000000 RB_MRT[0x7].PITCH: 0
00000000 RB_MRT[0x7].ARRAY_PITCH: 0
- 00000000 RB_MRT[0x7].BASE_LO: 0
+ 00000000 RB_MRT[0x7].BASE: 0
00000000 RB_MRT[0x7].BASE_HI: 0
00000000 RB_MRT[0x7].BASE_GMEM: 0
00000000 RB_BLEND_RED_F32: 0.000000
00000000 RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
00000000 RB_DEPTH_BUFFER_PITCH: 0
00000000 RB_DEPTH_BUFFER_ARRAY_PITCH: 0
- 00000000 RB_DEPTH_BUFFER_BASE_LO: 0
+ 00000000 RB_DEPTH_BUFFER_BASE: 0
00000000 RB_DEPTH_BUFFER_BASE_HI: 0
00000000 RB_DEPTH_BUFFER_BASE_GMEM: 0
00000000 RB_Z_BOUNDS_MIN: 0.000000
00000000 RB_STENCIL_INFO: { 0 }
00000000 RB_STENCIL_BUFFER_PITCH: 0
00000000 RB_STENCIL_BUFFER_ARRAY_PITCH: 0
- 00000000 RB_STENCIL_BUFFER_BASE_LO: 0
+ 00000000 RB_STENCIL_BUFFER_BASE: 0
00000000 RB_STENCIL_BUFFER_BASE_HI: 0
00000000 RB_STENCIL_BUFFER_BASE_GMEM: 0
00000000 RB_STENCILREF: { REF = 0 | BFREF = 0 }
00000000 RB_BLIT_BASE_GMEM: 0
00004100 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_32_32_32_32_FLOAT }
00000000 RB_BLIT_DST: 0
- 00000000 RB_BLIT_DST+0x1: 0
+ 00000000 RB_BLIT_DST_HI: 0
00000000 RB_BLIT_DST_PITCH: 0
00000000 RB_BLIT_DST_ARRAY_PITCH: 0
00000000 RB_BLIT_FLAG_DST: 0
- 00000000 RB_BLIT_FLAG_DST+0x1: 0
+ 00000000 RB_BLIT_FLAG_DST_HI: 0
00000000 RB_BLIT_FLAG_DST_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
00000000 RB_BLIT_CLEAR_COLOR_DW0: 0
00000000 RB_BLIT_CLEAR_COLOR_DW1: 0
00000000 RB_BLIT_CLEAR_COLOR_DW2: 0
00000000 RB_BLIT_CLEAR_COLOR_DW3: 0
000000f2 RB_BLIT_INFO: { GMEM | CLEAR_MASK = 0xf }
- 00000000 RB_DEPTH_FLAG_BUFFER_BASE_LO: 0
+ 00000000 RB_DEPTH_FLAG_BUFFER_BASE: 0
00000000 RB_DEPTH_FLAG_BUFFER_BASE_HI: 0
00000000 RB_DEPTH_FLAG_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_LO: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0].ADDR: 0
00000000 RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0
00000000 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- 00000000 RB_MRT_FLAG_BUFFER[0x1].ADDR_LO: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0x1].ADDR: 0
00000000 RB_MRT_FLAG_BUFFER[0x1].ADDR_HI: 0
00000000 RB_MRT_FLAG_BUFFER[0x1].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- 00000000 RB_MRT_FLAG_BUFFER[0x2].ADDR_LO: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0x2].ADDR: 0
00000000 RB_MRT_FLAG_BUFFER[0x2].ADDR_HI: 0
00000000 RB_MRT_FLAG_BUFFER[0x2].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- 00000000 RB_MRT_FLAG_BUFFER[0x3].ADDR_LO: 0
- 00000000 RB_MRT_FLAG_BUFFER[0x4].ADDR_LO: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0x3].ADDR: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0x4].ADDR: 0
00000000 RB_MRT_FLAG_BUFFER[0x4].ADDR_HI: 0
00000000 RB_MRT_FLAG_BUFFER[0x4].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- 00000000 RB_MRT_FLAG_BUFFER[0x5].ADDR_LO: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0x5].ADDR: 0
00000000 RB_MRT_FLAG_BUFFER[0x5].ADDR_HI: 0
00000000 RB_MRT_FLAG_BUFFER[0x5].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- 00000000 RB_MRT_FLAG_BUFFER[0x6].ADDR_LO: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0x6].ADDR: 0
00000000 RB_MRT_FLAG_BUFFER[0x6].ADDR_HI: 0
00000000 RB_MRT_FLAG_BUFFER[0x6].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- 00000000 RB_MRT_FLAG_BUFFER[0x7].ADDR_LO: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0x7].ADDR: 0
00000000 RB_MRT_FLAG_BUFFER[0x7].ADDR_HI: 0
00000000 RB_MRT_FLAG_BUFFER[0x7].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
00000000 RB_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | COLOR_FORMAT = 0 | MASK = 0 | IFMT = R2D_RAW }
00000000 0x8c0f: 00000000
00000000 0x8c10: 00000000
00000000 RB_2D_DST_INFO: { COLOR_FORMAT = 0 | TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX | SAMPLES = MSAA_ONE }
- 00000000 RB_2D_DST_LO: 0
+ 00000000 RB_2D_DST: 0
00000000 RB_2D_DST_HI: 0
00000000 RB_2D_DST_PITCH: 0
00000000 RB_2D_DST_PLANE1: 0
- 00000000 RB_2D_DST_PLANE1+0x1: 0
+ 00000000 RB_2D_DST_PLANE1_HI: 0
00000000 RB_2D_DST_PLANE_PITCH: 0
00000000 RB_2D_DST_PLANE2: 0
- 00000000 RB_2D_DST_PLANE2+0x1: 0
+ 00000000 RB_2D_DST_PLANE2_HI: 0
00000000 0x8c26: 00000000
00000000 0x8c27: 00000000
00000000 0x8c28: 00000000
- context: 0
00000000 RB_UNKNOWN_88F0: 0
00000000 RB_UNK_FLAG_BUFFER_BASE: 0
- 00000000 RB_UNK_FLAG_BUFFER_BASE+0x1: 0
+ 00000000 RB_UNK_FLAG_BUFFER_BASE_HI: 0
00000000 RB_UNK_FLAG_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
00000000 RB_MRT_FLAG_BUFFER[0x3].ADDR_HI: 0
00000000 RB_MRT_FLAG_BUFFER[0x3].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- 00000000 RB_SAMPLE_COUNT_ADDR_LO: 0
+ 00000000 RB_SAMPLE_COUNT_ADDR: 0
00000000 RB_SAMPLE_COUNT_ADDR_HI: 0
00000000 0x8bf0: 00000000
00000000 0x8bf1: 00000000
00000000 0x8c14: 00000000
00000000 0x8c15: 00000000
00000000 0x8c16: 00000000
- 00000000 RB_2D_DST_FLAGS_LO: 0
+ 00000000 RB_2D_DST_FLAGS: 0
00000000 RB_2D_DST_FLAGS_HI: 0
00000000 RB_2D_DST_FLAGS_PITCH: 0
00000000 RB_2D_DST_FLAGS_PLANE: 0
- 00000000 RB_2D_DST_FLAGS_PLANE+0x1: 0
+ 00000000 RB_2D_DST_FLAGS_PLANE_HI: 0
00000000 RB_2D_DST_FLAGS_PLANE_PITCH: 0
- context: 1
00000000 RB_UNKNOWN_88F0: 0
00000000 RB_UNK_FLAG_BUFFER_BASE: 0
- 00000000 RB_UNK_FLAG_BUFFER_BASE+0x1: 0
+ 00000000 RB_UNK_FLAG_BUFFER_BASE_HI: 0
00000000 RB_UNK_FLAG_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
00000000 RB_MRT_FLAG_BUFFER[0x3].ADDR_HI: 0
00000000 RB_MRT_FLAG_BUFFER[0x3].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- 00000000 RB_SAMPLE_COUNT_ADDR_LO: 0
+ 00000000 RB_SAMPLE_COUNT_ADDR: 0
00000000 RB_SAMPLE_COUNT_ADDR_HI: 0
00000000 0x8bf0: 00000000
00000000 0x8bf1: 00000000
00000000 0x8c14: 00000000
00000000 0x8c15: 00000000
00000000 0x8c16: 00000000
- 00000000 RB_2D_DST_FLAGS_LO: 0
+ 00000000 RB_2D_DST_FLAGS: 0
00000000 RB_2D_DST_FLAGS_HI: 0
00000000 RB_2D_DST_FLAGS_PITCH: 0
00000000 RB_2D_DST_FLAGS_PLANE: 0
- 00000000 RB_2D_DST_FLAGS_PLANE+0x1: 0
+ 00000000 RB_2D_DST_FLAGS_PLANE_HI: 0
00000000 RB_2D_DST_FLAGS_PLANE_PITCH: 0
- cluster-name: CLUSTER_PS
- context: 0
00000000 VPC_VAR[0x2].DISABLE: 0
00000000 VPC_VAR[0x3].DISABLE: 0
00000000 VPC_SO_CNTL: { ADDR = 0 }
- 00000000 VPC_SO_STREAM_COUNTS_LO: 0
+ 00000000 VPC_SO_STREAM_COUNTS: 0
00000000 VPC_SO_STREAM_COUNTS_HI: 0
00000000 VPC_SO[0].BUFFER_BASE: 0
- 00000000 VPC_SO[0].BUFFER_BASE+0x1: 0
+ 00000000 VPC_SO[0].BUFFER_BASE_HI: 0
00000000 VPC_SO[0].BUFFER_SIZE: 0
00000001 VPC_SO[0].NCOMP: 0x1
00000000 VPC_SO[0].BUFFER_OFFSET: 0
00000000 VPC_SO[0].FLUSH_BASE: 0
- 00000000 VPC_SO[0].FLUSH_BASE+0x1: 0
+ 00000000 VPC_SO[0].FLUSH_BASE_HI: 0
00000000 VPC_SO[0x1].BUFFER_BASE: 0
- 00000000 VPC_SO[0x1].BUFFER_BASE+0x1: 0
+ 00000000 VPC_SO[0x1].BUFFER_BASE_HI: 0
00000000 VPC_SO[0x1].BUFFER_SIZE: 0
00000001 VPC_SO[0x1].NCOMP: 0x1
00000000 VPC_SO[0x1].BUFFER_OFFSET: 0
00000000 VPC_SO[0x1].FLUSH_BASE: 0
- 00000000 VPC_SO[0x1].FLUSH_BASE+0x1: 0
+ 00000000 VPC_SO[0x1].FLUSH_BASE_HI: 0
00000000 VPC_SO[0x2].BUFFER_BASE: 0
- 00000000 VPC_SO[0x2].BUFFER_BASE+0x1: 0
+ 00000000 VPC_SO[0x2].BUFFER_BASE_HI: 0
00000000 VPC_SO[0x2].BUFFER_SIZE: 0
00000001 VPC_SO[0x2].NCOMP: 0x1
00000000 VPC_SO[0x2].BUFFER_OFFSET: 0
00000000 VPC_SO[0x2].FLUSH_BASE: 0
- 00000000 VPC_SO[0x2].FLUSH_BASE+0x1: 0
+ 00000000 VPC_SO[0x2].FLUSH_BASE_HI: 0
00000000 VPC_SO[0x3].BUFFER_BASE: 0
- 00000000 VPC_SO[0x3].BUFFER_BASE+0x1: 0
+ 00000000 VPC_SO[0x3].BUFFER_BASE_HI: 0
00000000 VPC_SO[0x3].BUFFER_SIZE: 0
00000001 VPC_SO[0x3].NCOMP: 0x1
00000000 VPC_SO[0x3].BUFFER_OFFSET: 0
00000000 VPC_SO[0x3].FLUSH_BASE: 0
- 00000000 VPC_SO[0x3].FLUSH_BASE+0x1: 0
+ 00000000 VPC_SO[0x3].FLUSH_BASE_HI: 0
00000000 VPC_POINT_COORD_INVERT: { 0 }
00000000 VPC_UNKNOWN_9300: 0
00ff0001 VPC_VS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
00000000 VPC_VAR[0x2].DISABLE: 0
00000000 VPC_VAR[0x3].DISABLE: 0
00000000 VPC_SO_CNTL: { ADDR = 0 }
- 00000000 VPC_SO_STREAM_COUNTS_LO: 0
+ 00000000 VPC_SO_STREAM_COUNTS: 0
00000000 VPC_SO_STREAM_COUNTS_HI: 0
00000000 VPC_SO[0].BUFFER_BASE: 0
- 00000000 VPC_SO[0].BUFFER_BASE+0x1: 0
+ 00000000 VPC_SO[0].BUFFER_BASE_HI: 0
00000000 VPC_SO[0].BUFFER_SIZE: 0
00000001 VPC_SO[0].NCOMP: 0x1
00000000 VPC_SO[0].BUFFER_OFFSET: 0
00000000 VPC_SO[0].FLUSH_BASE: 0
- 00000000 VPC_SO[0].FLUSH_BASE+0x1: 0
+ 00000000 VPC_SO[0].FLUSH_BASE_HI: 0
00000000 VPC_SO[0x1].BUFFER_BASE: 0
- 00000000 VPC_SO[0x1].BUFFER_BASE+0x1: 0
+ 00000000 VPC_SO[0x1].BUFFER_BASE_HI: 0
00000000 VPC_SO[0x1].BUFFER_SIZE: 0
00000001 VPC_SO[0x1].NCOMP: 0x1
00000000 VPC_SO[0x1].BUFFER_OFFSET: 0
00000000 VPC_SO[0x1].FLUSH_BASE: 0
- 00000000 VPC_SO[0x1].FLUSH_BASE+0x1: 0
+ 00000000 VPC_SO[0x1].FLUSH_BASE_HI: 0
00000000 VPC_SO[0x2].BUFFER_BASE: 0
- 00000000 VPC_SO[0x2].BUFFER_BASE+0x1: 0
+ 00000000 VPC_SO[0x2].BUFFER_BASE_HI: 0
00000000 VPC_SO[0x2].BUFFER_SIZE: 0
00000001 VPC_SO[0x2].NCOMP: 0x1
00000000 VPC_SO[0x2].BUFFER_OFFSET: 0
00000000 VPC_SO[0x2].FLUSH_BASE: 0
- 00000000 VPC_SO[0x2].FLUSH_BASE+0x1: 0
+ 00000000 VPC_SO[0x2].FLUSH_BASE_HI: 0
00000000 VPC_SO[0x3].BUFFER_BASE: 0
- 00000000 VPC_SO[0x3].BUFFER_BASE+0x1: 0
+ 00000000 VPC_SO[0x3].BUFFER_BASE_HI: 0
00000000 VPC_SO[0x3].BUFFER_SIZE: 0
00000001 VPC_SO[0x3].NCOMP: 0x1
00000000 VPC_SO[0x3].BUFFER_OFFSET: 0
00000000 VPC_SO[0x3].FLUSH_BASE: 0
- 00000000 VPC_SO[0x3].FLUSH_BASE+0x1: 0
+ 00000000 VPC_SO[0x3].FLUSH_BASE_HI: 0
00000000 VPC_POINT_COORD_INVERT: { 0 }
00000000 VPC_UNKNOWN_9300: 0
00ff0001 VPC_VS_PACK: { STRIDE_IN_VPC = 1 | POSITIONLOC = 0 | PSIZELOC = 255 | EXTRAPOS = 0 }
00000000 VFD_INDEX_OFFSET: 0
00000000 VFD_INSTANCE_START_OFFSET: 0
1618e045 VFD_FETCH[0].BASE: 0x1618e045
- 00005505 VFD_FETCH[0].BASE+0x1: 0x5505
+ 00005505 VFD_FETCH[0].BASE_HI: 0x5505
00840800 VFD_FETCH[0].SIZE: 8652800
00000051 VFD_FETCH[0].STRIDE: 81
01100401 VFD_FETCH[0x1].BASE: 0x1100401
- 00000040 VFD_FETCH[0x1].BASE+0x1: 0x40
+ 00000040 VFD_FETCH[0x1].BASE_HI: 0x40
04010402 VFD_FETCH[0x1].SIZE: 67175426
00000000 VFD_FETCH[0x1].STRIDE: 0
40080120 VFD_FETCH[0x2].BASE: 0x40080120
- 00004000 VFD_FETCH[0x2].BASE+0x1: 0x4000
+ 00004000 VFD_FETCH[0x2].BASE_HI: 0x4000
00140100 VFD_FETCH[0x2].SIZE: 1310976
00000002 VFD_FETCH[0x2].STRIDE: 2
00001090 VFD_FETCH[0x3].BASE: 0x1090
- 00000200 VFD_FETCH[0x3].BASE+0x1: 0x200
+ 00000200 VFD_FETCH[0x3].BASE_HI: 0x200
11040100 VFD_FETCH[0x3].SIZE: 285475072
00000000 VFD_FETCH[0x3].STRIDE: 0
04000900 VFD_FETCH[0x4].BASE: 0x4000900
- 00000451 VFD_FETCH[0x4].BASE+0x1: 0x451
+ 00000451 VFD_FETCH[0x4].BASE_HI: 0x451
01000806 VFD_FETCH[0x4].SIZE: 16779270
00000201 VFD_FETCH[0x4].STRIDE: 513
00004004 VFD_FETCH[0x5].BASE: 0x4004
- 00000000 VFD_FETCH[0x5].BASE+0x1: 0
+ 00000000 VFD_FETCH[0x5].BASE_HI: 0
00000080 VFD_FETCH[0x5].SIZE: 128
00000000 VFD_FETCH[0x5].STRIDE: 0
14008030 VFD_FETCH[0x6].BASE: 0x14008030
- 0000e303 VFD_FETCH[0x6].BASE+0x1: 0xe303
+ 0000e303 VFD_FETCH[0x6].BASE_HI: 0xe303
10020400 VFD_FETCH[0x6].SIZE: 268567552
00000088 VFD_FETCH[0x6].STRIDE: 136
02000030 VFD_FETCH[0x7].BASE: 0x2000030
- 00001140 VFD_FETCH[0x7].BASE+0x1: 0x1140
+ 00001140 VFD_FETCH[0x7].BASE_HI: 0x1140
40400000 VFD_FETCH[0x7].SIZE: 1077936128
00000041 VFD_FETCH[0x7].STRIDE: 65
c0100100 VFD_FETCH[0x8].BASE: 0xc0100100
- 00001244 VFD_FETCH[0x8].BASE+0x1: 0x1244
+ 00001244 VFD_FETCH[0x8].BASE_HI: 0x1244
00050004 VFD_FETCH[0x8].SIZE: 327684
00000040 VFD_FETCH[0x8].STRIDE: 64
00044000 VFD_FETCH[0x9].BASE: 0x44000
- 00000000 VFD_FETCH[0x9].BASE+0x1: 0
+ 00000000 VFD_FETCH[0x9].BASE_HI: 0
80000020 VFD_FETCH[0x9].SIZE: 2147483680
00000008 VFD_FETCH[0x9].STRIDE: 8
10006004 VFD_FETCH[0xa].BASE: 0x10006004
- 0000222a VFD_FETCH[0xa].BASE+0x1: 0x222a
+ 0000222a VFD_FETCH[0xa].BASE_HI: 0x222a
02042020 VFD_FETCH[0xa].SIZE: 33824800
00000681 VFD_FETCH[0xa].STRIDE: 1665
02101020 VFD_FETCH[0xb].BASE: 0x2101020
- 00000080 VFD_FETCH[0xb].BASE+0x1: 0x80
+ 00000080 VFD_FETCH[0xb].BASE_HI: 0x80
00040020 VFD_FETCH[0xb].SIZE: 262176
00000050 VFD_FETCH[0xb].STRIDE: 80
0a436062 VFD_FETCH[0xc].BASE: 0xa436062
- 00003041 VFD_FETCH[0xc].BASE+0x1: 0x3041
+ 00003041 VFD_FETCH[0xc].BASE_HI: 0x3041
06102040 VFD_FETCH[0xc].SIZE: 101720128
00000200 VFD_FETCH[0xc].STRIDE: 512
00800864 VFD_FETCH[0xd].BASE: 0x800864
- 00000000 VFD_FETCH[0xd].BASE+0x1: 0
+ 00000000 VFD_FETCH[0xd].BASE_HI: 0
10400044 VFD_FETCH[0xd].SIZE: 272629828
00000010 VFD_FETCH[0xd].STRIDE: 16
061b8c2a VFD_FETCH[0xe].BASE: 0x61b8c2a
- 00000004 VFD_FETCH[0xe].BASE+0x1: 0x4
+ 00000004 VFD_FETCH[0xe].BASE_HI: 0x4
01004391 VFD_FETCH[0xe].SIZE: 16794513
00000440 VFD_FETCH[0xe].STRIDE: 1088
02000000 VFD_FETCH[0xf].BASE: 0x2000000
- 00000200 VFD_FETCH[0xf].BASE+0x1: 0x200
+ 00000200 VFD_FETCH[0xf].BASE_HI: 0x200
41250000 VFD_FETCH[0xf].SIZE: 1092943872
00000010 VFD_FETCH[0xf].STRIDE: 16
01443027 VFD_FETCH[0x10].BASE: 0x1443027
- 00001000 VFD_FETCH[0x10].BASE+0x1: 0x1000
+ 00001000 VFD_FETCH[0x10].BASE_HI: 0x1000
c1100240 VFD_FETCH[0x10].SIZE: 3239051840
00000002 VFD_FETCH[0x10].STRIDE: 2
0000b404 VFD_FETCH[0x11].BASE: 0xb404
- 00000080 VFD_FETCH[0x11].BASE+0x1: 0x80
+ 00000080 VFD_FETCH[0x11].BASE_HI: 0x80
12404000 VFD_FETCH[0x11].SIZE: 306200576
00000280 VFD_FETCH[0x11].STRIDE: 640
8100011c VFD_FETCH[0x12].BASE: 0x8100011c
- 00000218 VFD_FETCH[0x12].BASE+0x1: 0x218
+ 00000218 VFD_FETCH[0x12].BASE_HI: 0x218
0050b000 VFD_FETCH[0x12].SIZE: 5287936
00000462 VFD_FETCH[0x12].STRIDE: 1122
00004001 VFD_FETCH[0x13].BASE: 0x4001
- 0000000c VFD_FETCH[0x13].BASE+0x1: 0xc
+ 0000000c VFD_FETCH[0x13].BASE_HI: 0xc
00810880 VFD_FETCH[0x13].SIZE: 8456320
00000000 VFD_FETCH[0x13].STRIDE: 0
00025022 VFD_FETCH[0x14].BASE: 0x25022
- 00000040 VFD_FETCH[0x14].BASE+0x1: 0x40
+ 00000040 VFD_FETCH[0x14].BASE_HI: 0x40
015c1040 VFD_FETCH[0x14].SIZE: 22810688
00000000 VFD_FETCH[0x14].STRIDE: 0
7a540120 VFD_FETCH[0x15].BASE: 0x7a540120
- 00000000 VFD_FETCH[0x15].BASE+0x1: 0
+ 00000000 VFD_FETCH[0x15].BASE_HI: 0
02800306 VFD_FETCH[0x15].SIZE: 41943814
00000024 VFD_FETCH[0x15].STRIDE: 36
00040f13 VFD_FETCH[0x16].BASE: 0x40f13
- 00000850 VFD_FETCH[0x16].BASE+0x1: 0x850
+ 00000850 VFD_FETCH[0x16].BASE_HI: 0x850
00425010 VFD_FETCH[0x16].SIZE: 4345872
00000408 VFD_FETCH[0x16].STRIDE: 1032
04012000 VFD_FETCH[0x17].BASE: 0x4012000
- 00004111 VFD_FETCH[0x17].BASE+0x1: 0x4111
+ 00004111 VFD_FETCH[0x17].BASE_HI: 0x4111
08012800 VFD_FETCH[0x17].SIZE: 134293504
00000000 VFD_FETCH[0x17].STRIDE: 0
00022003 VFD_FETCH[0x18].BASE: 0x22003
- 00000000 VFD_FETCH[0x18].BASE+0x1: 0
+ 00000000 VFD_FETCH[0x18].BASE_HI: 0
504228ac VFD_FETCH[0x18].SIZE: 1346513068
00000300 VFD_FETCH[0x18].STRIDE: 768
40a40080 VFD_FETCH[0x19].BASE: 0x40a40080
- 0000c010 VFD_FETCH[0x19].BASE+0x1: 0xc010
+ 0000c010 VFD_FETCH[0x19].BASE_HI: 0xc010
00002000 VFD_FETCH[0x19].SIZE: 8192
00000101 VFD_FETCH[0x19].STRIDE: 257
88248411 VFD_FETCH[0x1a].BASE: 0x88248411
- 00000400 VFD_FETCH[0x1a].BASE+0x1: 0x400
+ 00000400 VFD_FETCH[0x1a].BASE_HI: 0x400
2604c030 VFD_FETCH[0x1a].SIZE: 637845552
00000020 VFD_FETCH[0x1a].STRIDE: 32
00000000 VFD_FETCH[0x1b].BASE: 0
- 00000924 VFD_FETCH[0x1b].BASE+0x1: 0x924
+ 00000924 VFD_FETCH[0x1b].BASE_HI: 0x924
00100000 VFD_FETCH[0x1b].SIZE: 1048576
00000000 VFD_FETCH[0x1b].STRIDE: 0
048c1100 VFD_FETCH[0x1c].BASE: 0x48c1100
- 00000b06 VFD_FETCH[0x1c].BASE+0x1: 0xb06
+ 00000b06 VFD_FETCH[0x1c].BASE_HI: 0xb06
00007264 VFD_FETCH[0x1c].SIZE: 29284
00000c11 VFD_FETCH[0x1c].STRIDE: 3089
00000120 VFD_FETCH[0x1d].BASE: 0x120
- 00004547 VFD_FETCH[0x1d].BASE+0x1: 0x4547
+ 00004547 VFD_FETCH[0x1d].BASE_HI: 0x4547
46000080 VFD_FETCH[0x1d].SIZE: 1174405248
00000100 VFD_FETCH[0x1d].STRIDE: 256
001a026c VFD_FETCH[0x1e].BASE: 0x1a026c
- 00000545 VFD_FETCH[0x1e].BASE+0x1: 0x545
+ 00000545 VFD_FETCH[0x1e].BASE_HI: 0x545
22500060 VFD_FETCH[0x1e].SIZE: 575668320
00000002 VFD_FETCH[0x1e].STRIDE: 2
00041100 VFD_FETCH[0x1f].BASE: 0x41100
- 00001100 VFD_FETCH[0x1f].BASE+0x1: 0x1100
+ 00001100 VFD_FETCH[0x1f].BASE_HI: 0x1100
01810080 VFD_FETCH[0x1f].SIZE: 25231488
00000020 VFD_FETCH[0x1f].STRIDE: 32
00002320 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0x119 | FORMAT = 0 | SWAP = WZYX }
00000000 VFD_INDEX_OFFSET: 0
00000000 VFD_INSTANCE_START_OFFSET: 0
1618e045 VFD_FETCH[0].BASE: 0x1618e045
- 00005505 VFD_FETCH[0].BASE+0x1: 0x5505
+ 00005505 VFD_FETCH[0].BASE_HI: 0x5505
00840800 VFD_FETCH[0].SIZE: 8652800
00000051 VFD_FETCH[0].STRIDE: 81
01100401 VFD_FETCH[0x1].BASE: 0x1100401
- 00000040 VFD_FETCH[0x1].BASE+0x1: 0x40
+ 00000040 VFD_FETCH[0x1].BASE_HI: 0x40
04010402 VFD_FETCH[0x1].SIZE: 67175426
00000000 VFD_FETCH[0x1].STRIDE: 0
40080120 VFD_FETCH[0x2].BASE: 0x40080120
- 00004000 VFD_FETCH[0x2].BASE+0x1: 0x4000
+ 00004000 VFD_FETCH[0x2].BASE_HI: 0x4000
00140100 VFD_FETCH[0x2].SIZE: 1310976
00000002 VFD_FETCH[0x2].STRIDE: 2
00001090 VFD_FETCH[0x3].BASE: 0x1090
- 00000200 VFD_FETCH[0x3].BASE+0x1: 0x200
+ 00000200 VFD_FETCH[0x3].BASE_HI: 0x200
11040100 VFD_FETCH[0x3].SIZE: 285475072
00000000 VFD_FETCH[0x3].STRIDE: 0
04000900 VFD_FETCH[0x4].BASE: 0x4000900
- 00000451 VFD_FETCH[0x4].BASE+0x1: 0x451
+ 00000451 VFD_FETCH[0x4].BASE_HI: 0x451
01000806 VFD_FETCH[0x4].SIZE: 16779270
00000201 VFD_FETCH[0x4].STRIDE: 513
00004004 VFD_FETCH[0x5].BASE: 0x4004
- 00000000 VFD_FETCH[0x5].BASE+0x1: 0
+ 00000000 VFD_FETCH[0x5].BASE_HI: 0
00000080 VFD_FETCH[0x5].SIZE: 128
00000000 VFD_FETCH[0x5].STRIDE: 0
14008030 VFD_FETCH[0x6].BASE: 0x14008030
- 0000e303 VFD_FETCH[0x6].BASE+0x1: 0xe303
+ 0000e303 VFD_FETCH[0x6].BASE_HI: 0xe303
10020400 VFD_FETCH[0x6].SIZE: 268567552
00000088 VFD_FETCH[0x6].STRIDE: 136
02000030 VFD_FETCH[0x7].BASE: 0x2000030
- 00001140 VFD_FETCH[0x7].BASE+0x1: 0x1140
+ 00001140 VFD_FETCH[0x7].BASE_HI: 0x1140
40400000 VFD_FETCH[0x7].SIZE: 1077936128
00000041 VFD_FETCH[0x7].STRIDE: 65
c0100100 VFD_FETCH[0x8].BASE: 0xc0100100
- 00001244 VFD_FETCH[0x8].BASE+0x1: 0x1244
+ 00001244 VFD_FETCH[0x8].BASE_HI: 0x1244
00050004 VFD_FETCH[0x8].SIZE: 327684
00000040 VFD_FETCH[0x8].STRIDE: 64
00044000 VFD_FETCH[0x9].BASE: 0x44000
- 00000000 VFD_FETCH[0x9].BASE+0x1: 0
+ 00000000 VFD_FETCH[0x9].BASE_HI: 0
80000020 VFD_FETCH[0x9].SIZE: 2147483680
00000008 VFD_FETCH[0x9].STRIDE: 8
10006004 VFD_FETCH[0xa].BASE: 0x10006004
- 0000222a VFD_FETCH[0xa].BASE+0x1: 0x222a
+ 0000222a VFD_FETCH[0xa].BASE_HI: 0x222a
02042020 VFD_FETCH[0xa].SIZE: 33824800
00000681 VFD_FETCH[0xa].STRIDE: 1665
02101020 VFD_FETCH[0xb].BASE: 0x2101020
- 00000080 VFD_FETCH[0xb].BASE+0x1: 0x80
+ 00000080 VFD_FETCH[0xb].BASE_HI: 0x80
00040020 VFD_FETCH[0xb].SIZE: 262176
00000050 VFD_FETCH[0xb].STRIDE: 80
0a436062 VFD_FETCH[0xc].BASE: 0xa436062
- 00003041 VFD_FETCH[0xc].BASE+0x1: 0x3041
+ 00003041 VFD_FETCH[0xc].BASE_HI: 0x3041
06102040 VFD_FETCH[0xc].SIZE: 101720128
00000200 VFD_FETCH[0xc].STRIDE: 512
00800864 VFD_FETCH[0xd].BASE: 0x800864
- 00000000 VFD_FETCH[0xd].BASE+0x1: 0
+ 00000000 VFD_FETCH[0xd].BASE_HI: 0
10400044 VFD_FETCH[0xd].SIZE: 272629828
00000010 VFD_FETCH[0xd].STRIDE: 16
061b8c2a VFD_FETCH[0xe].BASE: 0x61b8c2a
- 00000004 VFD_FETCH[0xe].BASE+0x1: 0x4
+ 00000004 VFD_FETCH[0xe].BASE_HI: 0x4
01004391 VFD_FETCH[0xe].SIZE: 16794513
00000440 VFD_FETCH[0xe].STRIDE: 1088
02000000 VFD_FETCH[0xf].BASE: 0x2000000
- 00000200 VFD_FETCH[0xf].BASE+0x1: 0x200
+ 00000200 VFD_FETCH[0xf].BASE_HI: 0x200
41250000 VFD_FETCH[0xf].SIZE: 1092943872
00000010 VFD_FETCH[0xf].STRIDE: 16
01443027 VFD_FETCH[0x10].BASE: 0x1443027
- 00001000 VFD_FETCH[0x10].BASE+0x1: 0x1000
+ 00001000 VFD_FETCH[0x10].BASE_HI: 0x1000
c1100240 VFD_FETCH[0x10].SIZE: 3239051840
00000002 VFD_FETCH[0x10].STRIDE: 2
0000b404 VFD_FETCH[0x11].BASE: 0xb404
- 00000080 VFD_FETCH[0x11].BASE+0x1: 0x80
+ 00000080 VFD_FETCH[0x11].BASE_HI: 0x80
12404000 VFD_FETCH[0x11].SIZE: 306200576
00000280 VFD_FETCH[0x11].STRIDE: 640
8100011c VFD_FETCH[0x12].BASE: 0x8100011c
- 00000218 VFD_FETCH[0x12].BASE+0x1: 0x218
+ 00000218 VFD_FETCH[0x12].BASE_HI: 0x218
0050b000 VFD_FETCH[0x12].SIZE: 5287936
00000462 VFD_FETCH[0x12].STRIDE: 1122
00004001 VFD_FETCH[0x13].BASE: 0x4001
- 0000000c VFD_FETCH[0x13].BASE+0x1: 0xc
+ 0000000c VFD_FETCH[0x13].BASE_HI: 0xc
00810880 VFD_FETCH[0x13].SIZE: 8456320
00000000 VFD_FETCH[0x13].STRIDE: 0
00025022 VFD_FETCH[0x14].BASE: 0x25022
- 00000040 VFD_FETCH[0x14].BASE+0x1: 0x40
+ 00000040 VFD_FETCH[0x14].BASE_HI: 0x40
015c1040 VFD_FETCH[0x14].SIZE: 22810688
00000000 VFD_FETCH[0x14].STRIDE: 0
7a540120 VFD_FETCH[0x15].BASE: 0x7a540120
- 00000000 VFD_FETCH[0x15].BASE+0x1: 0
+ 00000000 VFD_FETCH[0x15].BASE_HI: 0
02800306 VFD_FETCH[0x15].SIZE: 41943814
00000024 VFD_FETCH[0x15].STRIDE: 36
00040f13 VFD_FETCH[0x16].BASE: 0x40f13
- 00000850 VFD_FETCH[0x16].BASE+0x1: 0x850
+ 00000850 VFD_FETCH[0x16].BASE_HI: 0x850
00425010 VFD_FETCH[0x16].SIZE: 4345872
00000408 VFD_FETCH[0x16].STRIDE: 1032
04012000 VFD_FETCH[0x17].BASE: 0x4012000
- 00004111 VFD_FETCH[0x17].BASE+0x1: 0x4111
+ 00004111 VFD_FETCH[0x17].BASE_HI: 0x4111
08012800 VFD_FETCH[0x17].SIZE: 134293504
00000000 VFD_FETCH[0x17].STRIDE: 0
00022003 VFD_FETCH[0x18].BASE: 0x22003
- 00000000 VFD_FETCH[0x18].BASE+0x1: 0
+ 00000000 VFD_FETCH[0x18].BASE_HI: 0
504228ac VFD_FETCH[0x18].SIZE: 1346513068
00000300 VFD_FETCH[0x18].STRIDE: 768
40a40080 VFD_FETCH[0x19].BASE: 0x40a40080
- 0000c010 VFD_FETCH[0x19].BASE+0x1: 0xc010
+ 0000c010 VFD_FETCH[0x19].BASE_HI: 0xc010
00002000 VFD_FETCH[0x19].SIZE: 8192
00000101 VFD_FETCH[0x19].STRIDE: 257
88248411 VFD_FETCH[0x1a].BASE: 0x88248411
- 00000400 VFD_FETCH[0x1a].BASE+0x1: 0x400
+ 00000400 VFD_FETCH[0x1a].BASE_HI: 0x400
2604c030 VFD_FETCH[0x1a].SIZE: 637845552
00000020 VFD_FETCH[0x1a].STRIDE: 32
00000000 VFD_FETCH[0x1b].BASE: 0
- 00000924 VFD_FETCH[0x1b].BASE+0x1: 0x924
+ 00000924 VFD_FETCH[0x1b].BASE_HI: 0x924
00100000 VFD_FETCH[0x1b].SIZE: 1048576
00000000 VFD_FETCH[0x1b].STRIDE: 0
048c1100 VFD_FETCH[0x1c].BASE: 0x48c1100
- 00000b06 VFD_FETCH[0x1c].BASE+0x1: 0xb06
+ 00000b06 VFD_FETCH[0x1c].BASE_HI: 0xb06
00007264 VFD_FETCH[0x1c].SIZE: 29284
00000c11 VFD_FETCH[0x1c].STRIDE: 3089
00000120 VFD_FETCH[0x1d].BASE: 0x120
- 00004547 VFD_FETCH[0x1d].BASE+0x1: 0x4547
+ 00004547 VFD_FETCH[0x1d].BASE_HI: 0x4547
46000080 VFD_FETCH[0x1d].SIZE: 1174405248
00000100 VFD_FETCH[0x1d].STRIDE: 256
001a026c VFD_FETCH[0x1e].BASE: 0x1a026c
- 00000545 VFD_FETCH[0x1e].BASE+0x1: 0x545
+ 00000545 VFD_FETCH[0x1e].BASE_HI: 0x545
22500060 VFD_FETCH[0x1e].SIZE: 575668320
00000002 VFD_FETCH[0x1e].STRIDE: 2
00041100 VFD_FETCH[0x1f].BASE: 0x41100
- 00001100 VFD_FETCH[0x1f].BASE+0x1: 0x1100
+ 00001100 VFD_FETCH[0x1f].BASE_HI: 0x1100
01810080 VFD_FETCH[0x1f].SIZE: 25231488
00000020 VFD_FETCH[0x1f].STRIDE: 32
00002320 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0x119 | FORMAT = 0 | SWAP = WZYX }
00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
00000000 SP_VS_OBJ_FIRST_EXEC_OFFSET: 0
- 8e5d7d37 SP_VS_OBJ_START_LO: 0x8e5d7d37
+ 8e5d7d37 SP_VS_OBJ_START: 0x8e5d7d37
0001fcd5 SP_VS_OBJ_START_HI: 0x1fcd5
00000000 SP_VS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 }
00000000 SP_VS_PVT_MEM_ADDR: 0
- 00000000 SP_VS_PVT_MEM_ADDR+0x1: 0
+ 00000000 SP_VS_PVT_MEM_ADDR_HI: 0
00000000 SP_VS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_VS_TEX_COUNT: 128
00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_HS_WAVE_INPUT_SIZE: 0
00000000 0xa832: 00000000
00000000 SP_HS_OBJ_FIRST_EXEC_OFFSET: 0
- 780a8ca5 SP_HS_OBJ_START_LO: 0x780a8ca5
+ 780a8ca5 SP_HS_OBJ_START: 0x780a8ca5
0001aad2 SP_HS_OBJ_START_HI: 0x1aad2
00000000 SP_HS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 }
00000000 SP_HS_PVT_MEM_ADDR: 0
- 00000000 SP_HS_PVT_MEM_ADDR+0x1: 0
+ 00000000 SP_HS_PVT_MEM_ADDR_HI: 0
00000000 SP_HS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_HS_TEX_COUNT: 128
00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_DS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
00000000 SP_DS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
00000000 SP_DS_OBJ_FIRST_EXEC_OFFSET: 0
- 7abf500d SP_DS_OBJ_START_LO: 0x7abf500d
+ 7abf500d SP_DS_OBJ_START: 0x7abf500d
00017e52 SP_DS_OBJ_START_HI: 0x17e52
00000000 SP_DS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 }
00000000 SP_DS_PVT_MEM_ADDR: 0
- 00000000 SP_DS_PVT_MEM_ADDR+0x1: 0
+ 00000000 SP_DS_PVT_MEM_ADDR_HI: 0
00000000 SP_DS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_DS_TEX_COUNT: 128
00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_GS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
00000000 SP_GS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
00000000 SP_GS_OBJ_FIRST_EXEC_OFFSET: 0
- 14e2046b SP_GS_OBJ_START_LO: 0x14e2046b
+ 14e2046b SP_GS_OBJ_START: 0x14e2046b
00004c8f SP_GS_OBJ_START_HI: 0x4c8f
00000000 SP_GS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 }
00000000 SP_GS_PVT_MEM_ADDR: 0
- 00000000 SP_GS_PVT_MEM_ADDR+0x1: 0
+ 00000000 SP_GS_PVT_MEM_ADDR_HI: 0
00000000 SP_GS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_GS_TEX_COUNT: 128
00000100 SP_GS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_GS_INSTRLEN: 0
- e0c4d9c6 SP_VS_TEX_SAMP_LO: 0xe0c4d9c6
+ e0c4d9c6 SP_VS_TEX_SAMP: 0xe0c4d9c6
0000ed21 SP_VS_TEX_SAMP_HI: 0xed21
- 73a9bba1 SP_HS_TEX_SAMP_LO: 0x73a9bba1
+ 73a9bba1 SP_HS_TEX_SAMP: 0x73a9bba1
00001a05 SP_HS_TEX_SAMP_HI: 0x1a05
- b21263a4 SP_DS_TEX_SAMP_LO: 0xb21263a4
+ b21263a4 SP_DS_TEX_SAMP: 0xb21263a4
0001a6b5 SP_DS_TEX_SAMP_HI: 0x1a6b5
- ee7b37d3 SP_GS_TEX_SAMP_LO: 0xee7b37d3
+ ee7b37d3 SP_GS_TEX_SAMP: 0xee7b37d3
000047fc SP_GS_TEX_SAMP_HI: 0x47fc
- 5eb05388 SP_VS_TEX_CONST_LO: 0x5eb05388
+ 5eb05388 SP_VS_TEX_CONST: 0x5eb05388
0001f31d SP_VS_TEX_CONST_HI: 0x1f31d
- 90f84815 SP_HS_TEX_CONST_LO: 0x90f84815
+ 90f84815 SP_HS_TEX_CONST: 0x90f84815
00018461 SP_HS_TEX_CONST_HI: 0x18461
- 96f329d4 SP_DS_TEX_CONST_LO: 0x96f329d4
+ 96f329d4 SP_DS_TEX_CONST: 0x96f329d4
00015905 SP_DS_TEX_CONST_HI: 0x15905
- e6ce68a3 SP_GS_TEX_CONST_LO: 0xe6ce68a3
+ e6ce68a3 SP_GS_TEX_CONST: 0xe6ce68a3
00007a12 SP_GS_TEX_CONST_HI: 0x7a12
00000000 0xa8c0: 00000000
00000000 0xa8c1: 00000000
00000000 SP_VS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
00000000 SP_VS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
00000000 SP_VS_OBJ_FIRST_EXEC_OFFSET: 0
- 8e5d7d37 SP_VS_OBJ_START_LO: 0x8e5d7d37
+ 8e5d7d37 SP_VS_OBJ_START: 0x8e5d7d37
0001fcd5 SP_VS_OBJ_START_HI: 0x1fcd5
00000000 SP_VS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 }
00000000 SP_VS_PVT_MEM_ADDR: 0
- 00000000 SP_VS_PVT_MEM_ADDR+0x1: 0
+ 00000000 SP_VS_PVT_MEM_ADDR_HI: 0
00000000 SP_VS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_VS_TEX_COUNT: 128
00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_HS_WAVE_INPUT_SIZE: 0
00000000 0xa832: 00000000
00000000 SP_HS_OBJ_FIRST_EXEC_OFFSET: 0
- 780a8ca5 SP_HS_OBJ_START_LO: 0x780a8ca5
+ 780a8ca5 SP_HS_OBJ_START: 0x780a8ca5
0001aad2 SP_HS_OBJ_START_HI: 0x1aad2
00000000 SP_HS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 }
00000000 SP_HS_PVT_MEM_ADDR: 0
- 00000000 SP_HS_PVT_MEM_ADDR+0x1: 0
+ 00000000 SP_HS_PVT_MEM_ADDR_HI: 0
00000000 SP_HS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_HS_TEX_COUNT: 128
00000000 SP_HS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_DS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
00000000 SP_DS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
00000000 SP_DS_OBJ_FIRST_EXEC_OFFSET: 0
- 7abf500d SP_DS_OBJ_START_LO: 0x7abf500d
+ 7abf500d SP_DS_OBJ_START: 0x7abf500d
00017e52 SP_DS_OBJ_START_HI: 0x17e52
00000000 SP_DS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 }
00000000 SP_DS_PVT_MEM_ADDR: 0
- 00000000 SP_DS_PVT_MEM_ADDR+0x1: 0
+ 00000000 SP_DS_PVT_MEM_ADDR_HI: 0
00000000 SP_DS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_DS_TEX_COUNT: 128
00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_GS_VPC_DST[0x6].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
00000000 SP_GS_VPC_DST[0x7].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
00000000 SP_GS_OBJ_FIRST_EXEC_OFFSET: 0
- 14e2046b SP_GS_OBJ_START_LO: 0x14e2046b
+ 14e2046b SP_GS_OBJ_START: 0x14e2046b
00004c8f SP_GS_OBJ_START_HI: 0x4c8f
00000000 SP_GS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 }
00000000 SP_GS_PVT_MEM_ADDR: 0
- 00000000 SP_GS_PVT_MEM_ADDR+0x1: 0
+ 00000000 SP_GS_PVT_MEM_ADDR_HI: 0
00000000 SP_GS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000080 SP_GS_TEX_COUNT: 128
00000100 SP_GS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_GS_INSTRLEN: 0
- e0c4d9c6 SP_VS_TEX_SAMP_LO: 0xe0c4d9c6
+ e0c4d9c6 SP_VS_TEX_SAMP: 0xe0c4d9c6
0000ed21 SP_VS_TEX_SAMP_HI: 0xed21
- 73a9bba1 SP_HS_TEX_SAMP_LO: 0x73a9bba1
+ 73a9bba1 SP_HS_TEX_SAMP: 0x73a9bba1
00001a05 SP_HS_TEX_SAMP_HI: 0x1a05
- b21263a4 SP_DS_TEX_SAMP_LO: 0xb21263a4
+ b21263a4 SP_DS_TEX_SAMP: 0xb21263a4
0001a6b5 SP_DS_TEX_SAMP_HI: 0x1a6b5
- ee7b37d3 SP_GS_TEX_SAMP_LO: 0xee7b37d3
+ ee7b37d3 SP_GS_TEX_SAMP: 0xee7b37d3
000047fc SP_GS_TEX_SAMP_HI: 0x47fc
- 5eb05388 SP_VS_TEX_CONST_LO: 0x5eb05388
+ 5eb05388 SP_VS_TEX_CONST: 0x5eb05388
0001f31d SP_VS_TEX_CONST_HI: 0x1f31d
- 90f84815 SP_HS_TEX_CONST_LO: 0x90f84815
+ 90f84815 SP_HS_TEX_CONST: 0x90f84815
00018461 SP_HS_TEX_CONST_HI: 0x18461
- 96f329d4 SP_DS_TEX_CONST_LO: 0x96f329d4
+ 96f329d4 SP_DS_TEX_CONST: 0x96f329d4
00015905 SP_DS_TEX_CONST_HI: 0x15905
- e6ce68a3 SP_GS_TEX_CONST_LO: 0xe6ce68a3
+ e6ce68a3 SP_GS_TEX_CONST: 0xe6ce68a3
00007a12 SP_GS_TEX_CONST_HI: 0x7a12
00000000 0xa8c0: 00000000
00000000 0xa8c1: 00000000
00000140 HLSQ_FS_CNTL: { CONSTLEN = 256 | ENABLED }
00000000 HLSQ_SHARED_CONSTS: { 0 }
00000000 HLSQ_BINDLESS_BASE[0].ADDR: 0
- 00000000 HLSQ_BINDLESS_BASE[0].ADDR+0x1: 0
+ 00000000 HLSQ_BINDLESS_BASE[0].ADDR_HI: 0
00000000 HLSQ_BINDLESS_BASE[0x1].ADDR: 0
- 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR+0x1: 0
+ 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR_HI: 0
00000000 HLSQ_BINDLESS_BASE[0x2].ADDR: 0
- 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR+0x1: 0
+ 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR_HI: 0
00000000 HLSQ_BINDLESS_BASE[0x3].ADDR: 0
- 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR+0x1: 0
+ 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR_HI: 0
00000000 HLSQ_BINDLESS_BASE[0x4].ADDR: 0
- 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR+0x1: 0
+ 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR_HI: 0
- context: 1
00000140 HLSQ_FS_CNTL: { CONSTLEN = 256 | ENABLED }
00000000 HLSQ_SHARED_CONSTS: { 0 }
00000000 HLSQ_BINDLESS_BASE[0].ADDR: 0
- 00000000 HLSQ_BINDLESS_BASE[0].ADDR+0x1: 0
+ 00000000 HLSQ_BINDLESS_BASE[0].ADDR_HI: 0
00000000 HLSQ_BINDLESS_BASE[0x1].ADDR: 0
- 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR+0x1: 0
+ 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR_HI: 0
00000000 HLSQ_BINDLESS_BASE[0x2].ADDR: 0
- 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR+0x1: 0
+ 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR_HI: 0
00000000 HLSQ_BINDLESS_BASE[0x3].ADDR: 0
- 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR+0x1: 0
+ 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR_HI: 0
00000000 HLSQ_BINDLESS_BASE[0x4].ADDR: 0
- 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR+0x1: 0
+ 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR_HI: 0
- cluster-name: CLUSTER_SP_VS
- context: 0
deadbeef HLSQ_2D_EVENT_CMD: { STATE_ID = 0xbe | EVENT = 0x6f | 0xdead0080 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_FS_INSTRLEN: 0
2764a40a SP_BINDLESS_BASE[0].ADDR: 0x2764a40a
- 0000cd30 SP_BINDLESS_BASE[0].ADDR+0x1: 0xcd30
+ 0000cd30 SP_BINDLESS_BASE[0].ADDR_HI: 0xcd30
93870830 SP_BINDLESS_BASE[0x1].ADDR: 0x93870830
- 00017dc4 SP_BINDLESS_BASE[0x1].ADDR+0x1: 0x17dc4
+ 00017dc4 SP_BINDLESS_BASE[0x1].ADDR_HI: 0x17dc4
d3064206 SP_BINDLESS_BASE[0x2].ADDR: 0xd3064206
- 00014b45 SP_BINDLESS_BASE[0x2].ADDR+0x1: 0x14b45
+ 00014b45 SP_BINDLESS_BASE[0x2].ADDR_HI: 0x14b45
bfafe9ba SP_BINDLESS_BASE[0x3].ADDR: 0xbfafe9ba
- 0001ddc9 SP_BINDLESS_BASE[0x3].ADDR+0x1: 0x1ddc9
+ 0001ddc9 SP_BINDLESS_BASE[0x3].ADDR_HI: 0x1ddc9
efda4292 SP_BINDLESS_BASE[0x4].ADDR: 0xefda4292
- 0000bd3b SP_BINDLESS_BASE[0x4].ADDR+0x1: 0xbd3b
- 0c0e0691 SP_IBO_LO: 0xc0e0691
+ 0000bd3b SP_BINDLESS_BASE[0x4].ADDR_HI: 0xbd3b
+ 0c0e0691 SP_IBO: 0xc0e0691
00013c40 SP_IBO_HI: 0x13c40
00000040 SP_IBO_COUNT: 64
- context: 1
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_FS_INSTRLEN: 0
2764a40a SP_BINDLESS_BASE[0].ADDR: 0x2764a40a
- 0000cd30 SP_BINDLESS_BASE[0].ADDR+0x1: 0xcd30
+ 0000cd30 SP_BINDLESS_BASE[0].ADDR_HI: 0xcd30
93870830 SP_BINDLESS_BASE[0x1].ADDR: 0x93870830
- 00017dc4 SP_BINDLESS_BASE[0x1].ADDR+0x1: 0x17dc4
+ 00017dc4 SP_BINDLESS_BASE[0x1].ADDR_HI: 0x17dc4
d3064206 SP_BINDLESS_BASE[0x2].ADDR: 0xd3064206
- 00014b45 SP_BINDLESS_BASE[0x2].ADDR+0x1: 0x14b45
+ 00014b45 SP_BINDLESS_BASE[0x2].ADDR_HI: 0x14b45
bfafe9ba SP_BINDLESS_BASE[0x3].ADDR: 0xbfafe9ba
- 0001ddc9 SP_BINDLESS_BASE[0x3].ADDR+0x1: 0x1ddc9
+ 0001ddc9 SP_BINDLESS_BASE[0x3].ADDR_HI: 0x1ddc9
efda4292 SP_BINDLESS_BASE[0x4].ADDR: 0xefda4292
- 0000bd3b SP_BINDLESS_BASE[0x4].ADDR+0x1: 0xbd3b
- 0c0e0691 SP_IBO_LO: 0xc0e0691
+ 0000bd3b SP_BINDLESS_BASE[0x4].ADDR_HI: 0xbd3b
+ 0c0e0691 SP_IBO: 0xc0e0691
00013c40 SP_IBO_HI: 0x13c40
00000040 SP_IBO_COUNT: 64
- cluster-name: CLUSTER_SP_VS
00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
00000000 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE }
00000000 SP_TP_BORDER_COLOR_BASE_ADDR: 0
- 00000000 SP_TP_BORDER_COLOR_BASE_ADDR+0x1: 0
+ 00000000 SP_TP_BORDER_COLOR_BASE_ADDR_HI: 0
00000000 SP_TP_SAMPLE_CONFIG: { 0 }
00000000 SP_TP_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
00000000 SP_TP_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
00000000 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE }
00000000 SP_TP_BORDER_COLOR_BASE_ADDR: 0
- 00000000 SP_TP_BORDER_COLOR_BASE_ADDR+0x1: 0
+ 00000000 SP_TP_BORDER_COLOR_BASE_ADDR_HI: 0
00000000 SP_TP_SAMPLE_CONFIG: { 0 }
00000000 SP_TP_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
00000000 SP_TP_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
8c415430 HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR: 0x8c415430
00000000 HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR+0x1: 0
00000000 HLSQ_CS_BINDLESS_BASE[0].ADDR: 0
- 00000000 HLSQ_CS_BINDLESS_BASE[0].ADDR+0x1: 0
+ 00000000 HLSQ_CS_BINDLESS_BASE[0].ADDR_HI: 0
00000000 HLSQ_CS_BINDLESS_BASE[0x1].ADDR: 0
- 00000000 HLSQ_CS_BINDLESS_BASE[0x1].ADDR+0x1: 0
+ 00000000 HLSQ_CS_BINDLESS_BASE[0x1].ADDR_HI: 0
00000000 HLSQ_CS_BINDLESS_BASE[0x2].ADDR: 0
- 00000000 HLSQ_CS_BINDLESS_BASE[0x2].ADDR+0x1: 0
+ 00000000 HLSQ_CS_BINDLESS_BASE[0x2].ADDR_HI: 0
00000000 HLSQ_CS_BINDLESS_BASE[0x3].ADDR: 0
- 00000000 HLSQ_CS_BINDLESS_BASE[0x3].ADDR+0x1: 0
+ 00000000 HLSQ_CS_BINDLESS_BASE[0x3].ADDR_HI: 0
00000000 HLSQ_CS_BINDLESS_BASE[0x4].ADDR: 0
- 00000000 HLSQ_CS_BINDLESS_BASE[0x4].ADDR+0x1: 0
+ 00000000 HLSQ_CS_BINDLESS_BASE[0x4].ADDR_HI: 0
- context: 1
00000001 HLSQ_FS_CNTL_0: { THREADSIZE = THREAD128 }
00000007 HLSQ_CONTROL_1_REG: 0x7
8c415430 HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR: 0x8c415430
00000000 HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR+0x1: 0
00000000 HLSQ_CS_BINDLESS_BASE[0].ADDR: 0
- 00000000 HLSQ_CS_BINDLESS_BASE[0].ADDR+0x1: 0
+ 00000000 HLSQ_CS_BINDLESS_BASE[0].ADDR_HI: 0
00000000 HLSQ_CS_BINDLESS_BASE[0x1].ADDR: 0
- 00000000 HLSQ_CS_BINDLESS_BASE[0x1].ADDR+0x1: 0
+ 00000000 HLSQ_CS_BINDLESS_BASE[0x1].ADDR_HI: 0
00000000 HLSQ_CS_BINDLESS_BASE[0x2].ADDR: 0
- 00000000 HLSQ_CS_BINDLESS_BASE[0x2].ADDR+0x1: 0
+ 00000000 HLSQ_CS_BINDLESS_BASE[0x2].ADDR_HI: 0
00000000 HLSQ_CS_BINDLESS_BASE[0x3].ADDR: 0
- 00000000 HLSQ_CS_BINDLESS_BASE[0x3].ADDR+0x1: 0
+ 00000000 HLSQ_CS_BINDLESS_BASE[0x3].ADDR_HI: 0
00000000 HLSQ_CS_BINDLESS_BASE[0x4].ADDR: 0
- 00000000 HLSQ_CS_BINDLESS_BASE[0x4].ADDR+0x1: 0
+ 00000000 HLSQ_CS_BINDLESS_BASE[0x4].ADDR_HI: 0
- cluster-name: CLUSTER_SP_PS
- context: 0
deadbeef HLSQ_2D_EVENT_CMD: { STATE_ID = 0xbe | EVENT = 0x6f | 0xdead0080 }
05100000 SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | PIXLODENABLE | 0x1000000 }
00000000 SP_FS_BRANCH_COND: 0
00000000 SP_FS_OBJ_FIRST_EXEC_OFFSET: 0
- 4bdb43d8 SP_FS_OBJ_START_LO: 0x4bdb43d8
+ 4bdb43d8 SP_FS_OBJ_START: 0x4bdb43d8
0001af86 SP_FS_OBJ_START_HI: 0x1af86
00000000 SP_FS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 }
00000000 SP_FS_PVT_MEM_ADDR: 0
- 00000000 SP_FS_PVT_MEM_ADDR+0x1: 0
+ 00000000 SP_FS_PVT_MEM_ADDR_HI: 0
00000000 SP_FS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000100 SP_BLEND_CNTL: { UNK8 }
00000000 SP_SRGB_CNTL: { 0 }
0000001f SP_CS_UNKNOWN_A9B1: 31
00000000 0xa9b2: 00000000
00000000 SP_CS_OBJ_FIRST_EXEC_OFFSET: 0
- 8c415420 SP_CS_OBJ_START_LO: 0x8c415420
+ 8c415420 SP_CS_OBJ_START: 0x8c415420
00000000 SP_CS_OBJ_START_HI: 0
00000000 SP_CS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 }
00000000 SP_CS_PVT_MEM_ADDR: 0
00000000 0xa9d1: 00000000
00000000 0xa9d2: 00000000
00000000 0xa9d3: 00000000
- efea5306 SP_FS_TEX_SAMP_LO: 0xefea5306
+ efea5306 SP_FS_TEX_SAMP: 0xefea5306
00005e1c SP_FS_TEX_SAMP_HI: 0x5e1c
- bf8b2a24 SP_CS_TEX_SAMP_LO: 0xbf8b2a24
+ bf8b2a24 SP_CS_TEX_SAMP: 0xbf8b2a24
0001ef50 SP_CS_TEX_SAMP_HI: 0x1ef50
- 693f2108 SP_FS_TEX_CONST_LO: 0x693f2108
+ 693f2108 SP_FS_TEX_CONST: 0x693f2108
00001998 SP_FS_TEX_CONST_HI: 0x1998
- be19e77a SP_CS_TEX_CONST_LO: 0xbe19e77a
+ be19e77a SP_CS_TEX_CONST: 0xbe19e77a
0001b500 SP_CS_TEX_CONST_HI: 0x1b500
7dd2a41c SP_CS_BINDLESS_BASE[0].ADDR: 0x7dd2a41c
- 00012191 SP_CS_BINDLESS_BASE[0].ADDR+0x1: 0x12191
+ 00012191 SP_CS_BINDLESS_BASE[0].ADDR_HI: 0x12191
7d568030 SP_CS_BINDLESS_BASE[0x1].ADDR: 0x7d568030
- 0000f408 SP_CS_BINDLESS_BASE[0x1].ADDR+0x1: 0xf408
+ 0000f408 SP_CS_BINDLESS_BASE[0x1].ADDR_HI: 0xf408
6915b33d SP_CS_BINDLESS_BASE[0x2].ADDR: 0x6915b33d
- 000076cd SP_CS_BINDLESS_BASE[0x2].ADDR+0x1: 0x76cd
+ 000076cd SP_CS_BINDLESS_BASE[0x2].ADDR_HI: 0x76cd
3cfd0197 SP_CS_BINDLESS_BASE[0x3].ADDR: 0x3cfd0197
- 0001f233 SP_CS_BINDLESS_BASE[0x3].ADDR+0x1: 0x1f233
+ 0001f233 SP_CS_BINDLESS_BASE[0x3].ADDR_HI: 0x1f233
a6b745da SP_CS_BINDLESS_BASE[0x4].ADDR: 0xa6b745da
- 00016204 SP_CS_BINDLESS_BASE[0x4].ADDR+0x1: 0x16204
- fdfdd365 SP_CS_IBO_LO: 0xfdfdd365
+ 00016204 SP_CS_BINDLESS_BASE[0x4].ADDR_HI: 0x16204
+ fdfdd365 SP_CS_IBO: 0xfdfdd365
0001d693 SP_CS_IBO_HI: 0x1d693
00000040 SP_CS_IBO_COUNT: 64
00000000 0xaa30: 00000000
05100000 SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 0 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | PIXLODENABLE | 0x1000000 }
00000000 SP_FS_BRANCH_COND: 0
00000000 SP_FS_OBJ_FIRST_EXEC_OFFSET: 0
- 4bdb43d8 SP_FS_OBJ_START_LO: 0x4bdb43d8
+ 4bdb43d8 SP_FS_OBJ_START: 0x4bdb43d8
0001af86 SP_FS_OBJ_START_HI: 0x1af86
00000000 SP_FS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 }
00000000 SP_FS_PVT_MEM_ADDR: 0
- 00000000 SP_FS_PVT_MEM_ADDR+0x1: 0
+ 00000000 SP_FS_PVT_MEM_ADDR_HI: 0
00000000 SP_FS_PVT_MEM_SIZE: { TOTALPVTMEMSIZE = 0 }
00000100 SP_BLEND_CNTL: { UNK8 }
00000000 SP_SRGB_CNTL: { 0 }
0000001f SP_CS_UNKNOWN_A9B1: 31
00000000 0xa9b2: 00000000
00000000 SP_CS_OBJ_FIRST_EXEC_OFFSET: 0
- 8c415420 SP_CS_OBJ_START_LO: 0x8c415420
+ 8c415420 SP_CS_OBJ_START: 0x8c415420
00000000 SP_CS_OBJ_START_HI: 0
00000000 SP_CS_PVT_MEM_PARAM: { MEMSIZEPERITEM = 0 | HWSTACKSIZEPERTHREAD = 0 }
00000000 SP_CS_PVT_MEM_ADDR: 0
00000000 0xa9d1: 00000000
00000000 0xa9d2: 00000000
00000000 0xa9d3: 00000000
- efea5306 SP_FS_TEX_SAMP_LO: 0xefea5306
+ efea5306 SP_FS_TEX_SAMP: 0xefea5306
00005e1c SP_FS_TEX_SAMP_HI: 0x5e1c
- bf8b2a24 SP_CS_TEX_SAMP_LO: 0xbf8b2a24
+ bf8b2a24 SP_CS_TEX_SAMP: 0xbf8b2a24
0001ef50 SP_CS_TEX_SAMP_HI: 0x1ef50
- 693f2108 SP_FS_TEX_CONST_LO: 0x693f2108
+ 693f2108 SP_FS_TEX_CONST: 0x693f2108
00001998 SP_FS_TEX_CONST_HI: 0x1998
- be19e77a SP_CS_TEX_CONST_LO: 0xbe19e77a
+ be19e77a SP_CS_TEX_CONST: 0xbe19e77a
0001b500 SP_CS_TEX_CONST_HI: 0x1b500
7dd2a41c SP_CS_BINDLESS_BASE[0].ADDR: 0x7dd2a41c
- 00012191 SP_CS_BINDLESS_BASE[0].ADDR+0x1: 0x12191
+ 00012191 SP_CS_BINDLESS_BASE[0].ADDR_HI: 0x12191
7d568030 SP_CS_BINDLESS_BASE[0x1].ADDR: 0x7d568030
- 0000f408 SP_CS_BINDLESS_BASE[0x1].ADDR+0x1: 0xf408
+ 0000f408 SP_CS_BINDLESS_BASE[0x1].ADDR_HI: 0xf408
6915b33d SP_CS_BINDLESS_BASE[0x2].ADDR: 0x6915b33d
- 000076cd SP_CS_BINDLESS_BASE[0x2].ADDR+0x1: 0x76cd
+ 000076cd SP_CS_BINDLESS_BASE[0x2].ADDR_HI: 0x76cd
3cfd0197 SP_CS_BINDLESS_BASE[0x3].ADDR: 0x3cfd0197
- 0001f233 SP_CS_BINDLESS_BASE[0x3].ADDR+0x1: 0x1f233
+ 0001f233 SP_CS_BINDLESS_BASE[0x3].ADDR_HI: 0x1f233
a6b745da SP_CS_BINDLESS_BASE[0x4].ADDR: 0xa6b745da
- 00016204 SP_CS_BINDLESS_BASE[0x4].ADDR+0x1: 0x16204
- fdfdd365 SP_CS_IBO_LO: 0xfdfdd365
+ 00016204 SP_CS_BINDLESS_BASE[0x4].ADDR_HI: 0x16204
+ fdfdd365 SP_CS_IBO: 0xfdfdd365
0001d693 SP_CS_IBO_HI: 0x1d693
00000040 SP_CS_IBO_COUNT: 64
00000000 0xaa30: 00000000
- cluster-name: CLUSTER_SP_PS
- context: 0
00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0
- 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR+0x1: 0
+ 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR_HI: 0
00000000 SP_UNKNOWN_B182: 0
00000000 SP_UNKNOWN_B183: 0
00000000 0xb190: 00000000
00000000 0xb191: 00000000
- context: 1
00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0
- 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR+0x1: 0
+ 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR_HI: 0
00000000 SP_UNKNOWN_B182: 0
00000000 SP_UNKNOWN_B183: 0
00000000 0xb190: 00000000
- context: 0
00000000 SP_PS_2D_SRC_INFO: { COLOR_FORMAT = 0 | TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX | SAMPLES = MSAA_ONE }
00000000 SP_PS_2D_SRC_SIZE: { WIDTH = 0 | HEIGHT = 0 }
- 00000000 SP_PS_2D_SRC_LO: 0
+ 00000000 SP_PS_2D_SRC: 0
00000000 SP_PS_2D_SRC_HI: 0
00000000 SP_PS_2D_SRC_PITCH: { PITCH = 0 }
00000000 0xb4c5: 00000000
00000000 0xb4c7: 00000000
00000000 0xb4c8: 00000000
00000000 0xb4c9: 00000000
- 00000000 SP_PS_2D_SRC_FLAGS_LO: 0
+ 00000000 SP_PS_2D_SRC_FLAGS: 0
00000000 SP_PS_2D_SRC_FLAGS_HI: 0
00000000 SP_PS_2D_SRC_FLAGS_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
00000000 0xb4cd: 00000000
- context: 1
00000000 SP_PS_2D_SRC_INFO: { COLOR_FORMAT = 0 | TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WZYX | SAMPLES = MSAA_ONE }
00000000 SP_PS_2D_SRC_SIZE: { WIDTH = 0 | HEIGHT = 0 }
- 00000000 SP_PS_2D_SRC_LO: 0
+ 00000000 SP_PS_2D_SRC: 0
00000000 SP_PS_2D_SRC_HI: 0
00000000 SP_PS_2D_SRC_PITCH: { PITCH = 0 }
00000000 0xb4c5: 00000000
00000000 0xb4c7: 00000000
00000000 0xb4c8: 00000000
00000000 0xb4c9: 00000000
- 00000000 SP_PS_2D_SRC_FLAGS_LO: 0
+ 00000000 SP_PS_2D_SRC_FLAGS: 0
00000000 SP_PS_2D_SRC_FLAGS_HI: 0
00000000 SP_PS_2D_SRC_FLAGS_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
00000000 0xb4cd: 00000000
00000140 HLSQ_FS_CNTL: { CONSTLEN = 256 | ENABLED }
00000000 HLSQ_SHARED_CONSTS: { 0 }
00000000 HLSQ_BINDLESS_BASE[0].ADDR: 0
- 00000000 HLSQ_BINDLESS_BASE[0].ADDR+0x1: 0
+ 00000000 HLSQ_BINDLESS_BASE[0].ADDR_HI: 0
00000000 HLSQ_BINDLESS_BASE[0x1].ADDR: 0
- 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR+0x1: 0
+ 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR_HI: 0
00000000 HLSQ_BINDLESS_BASE[0x2].ADDR: 0
- 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR+0x1: 0
+ 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR_HI: 0
00000000 HLSQ_BINDLESS_BASE[0x3].ADDR: 0
- 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR+0x1: 0
+ 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR_HI: 0
00000000 HLSQ_BINDLESS_BASE[0x4].ADDR: 0
- 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR+0x1: 0
+ 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR_HI: 0
- context: 1
00000140 HLSQ_FS_CNTL: { CONSTLEN = 256 | ENABLED }
00000000 HLSQ_SHARED_CONSTS: { 0 }
00000000 HLSQ_BINDLESS_BASE[0].ADDR: 0
- 00000000 HLSQ_BINDLESS_BASE[0].ADDR+0x1: 0
+ 00000000 HLSQ_BINDLESS_BASE[0].ADDR_HI: 0
00000000 HLSQ_BINDLESS_BASE[0x1].ADDR: 0
- 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR+0x1: 0
+ 00000000 HLSQ_BINDLESS_BASE[0x1].ADDR_HI: 0
00000000 HLSQ_BINDLESS_BASE[0x2].ADDR: 0
- 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR+0x1: 0
+ 00000000 HLSQ_BINDLESS_BASE[0x2].ADDR_HI: 0
00000000 HLSQ_BINDLESS_BASE[0x3].ADDR: 0
- 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR+0x1: 0
+ 00000000 HLSQ_BINDLESS_BASE[0x3].ADDR_HI: 0
00000000 HLSQ_BINDLESS_BASE[0x4].ADDR: 0
- 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR+0x1: 0
+ 00000000 HLSQ_BINDLESS_BASE[0x4].ADDR_HI: 0
- cluster-name: CLUSTER_SP_PS
- context: 0
00000000 SP_MODE_CONTROL: { 0 }
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_FS_INSTRLEN: 0
cdb94116 SP_BINDLESS_BASE[0].ADDR: 0xcdb94116
- 000007b4 SP_BINDLESS_BASE[0].ADDR+0x1: 0x7b4
+ 000007b4 SP_BINDLESS_BASE[0].ADDR_HI: 0x7b4
6e5e07c3 SP_BINDLESS_BASE[0x1].ADDR: 0x6e5e07c3
- 0001f54b SP_BINDLESS_BASE[0x1].ADDR+0x1: 0x1f54b
+ 0001f54b SP_BINDLESS_BASE[0x1].ADDR_HI: 0x1f54b
5f979543 SP_BINDLESS_BASE[0x2].ADDR: 0x5f979543
- 0001b455 SP_BINDLESS_BASE[0x2].ADDR+0x1: 0x1b455
+ 0001b455 SP_BINDLESS_BASE[0x2].ADDR_HI: 0x1b455
a4d3a8cc SP_BINDLESS_BASE[0x3].ADDR: 0xa4d3a8cc
- 00013f8c SP_BINDLESS_BASE[0x3].ADDR+0x1: 0x13f8c
+ 00013f8c SP_BINDLESS_BASE[0x3].ADDR_HI: 0x13f8c
1d337e76 SP_BINDLESS_BASE[0x4].ADDR: 0x1d337e76
- 0001ff60 SP_BINDLESS_BASE[0x4].ADDR+0x1: 0x1ff60
- e0e8bc18 SP_IBO_LO: 0xe0e8bc18
+ 0001ff60 SP_BINDLESS_BASE[0x4].ADDR_HI: 0x1ff60
+ e0e8bc18 SP_IBO: 0xe0e8bc18
00010202 SP_IBO_HI: 0x10202
00000040 SP_IBO_COUNT: 64
- context: 1
00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
00000000 SP_FS_INSTRLEN: 0
cdb94116 SP_BINDLESS_BASE[0].ADDR: 0xcdb94116
- 000007b4 SP_BINDLESS_BASE[0].ADDR+0x1: 0x7b4
+ 000007b4 SP_BINDLESS_BASE[0].ADDR_HI: 0x7b4
6e5e07c3 SP_BINDLESS_BASE[0x1].ADDR: 0x6e5e07c3
- 0001f54b SP_BINDLESS_BASE[0x1].ADDR+0x1: 0x1f54b
+ 0001f54b SP_BINDLESS_BASE[0x1].ADDR_HI: 0x1f54b
5f979543 SP_BINDLESS_BASE[0x2].ADDR: 0x5f979543
- 0001b455 SP_BINDLESS_BASE[0x2].ADDR+0x1: 0x1b455
+ 0001b455 SP_BINDLESS_BASE[0x2].ADDR_HI: 0x1b455
a4d3a8cc SP_BINDLESS_BASE[0x3].ADDR: 0xa4d3a8cc
- 00013f8c SP_BINDLESS_BASE[0x3].ADDR+0x1: 0x13f8c
+ 00013f8c SP_BINDLESS_BASE[0x3].ADDR_HI: 0x13f8c
1d337e76 SP_BINDLESS_BASE[0x4].ADDR: 0x1d337e76
- 0001ff60 SP_BINDLESS_BASE[0x4].ADDR+0x1: 0x1ff60
- e0e8bc18 SP_IBO_LO: 0xe0e8bc18
+ 0001ff60 SP_BINDLESS_BASE[0x4].ADDR_HI: 0x1ff60
+ e0e8bc18 SP_IBO: 0xe0e8bc18
00010202 SP_IBO_HI: 0x10202
00000040 SP_IBO_COUNT: 64
- cluster-name: CLUSTER_SP_PS
00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
00000000 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE }
00000000 SP_TP_BORDER_COLOR_BASE_ADDR: 0
- 00000000 SP_TP_BORDER_COLOR_BASE_ADDR+0x1: 0
+ 00000000 SP_TP_BORDER_COLOR_BASE_ADDR_HI: 0
00000000 SP_TP_SAMPLE_CONFIG: { 0 }
00000000 SP_TP_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
00000000 SP_TP_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
00000000 SP_TP_RAS_MSAA_CNTL: { SAMPLES = MSAA_ONE }
00000000 SP_TP_DEST_MSAA_CNTL: { SAMPLES = MSAA_ONE }
00000000 SP_TP_BORDER_COLOR_BASE_ADDR: 0
- 00000000 SP_TP_BORDER_COLOR_BASE_ADDR+0x1: 0
+ 00000000 SP_TP_BORDER_COLOR_BASE_ADDR_HI: 0
00000000 SP_TP_SAMPLE_CONFIG: { 0 }
00000000 SP_TP_SAMPLE_LOCATION_0: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
00000000 SP_TP_SAMPLE_LOCATION_1: { SAMPLE_0_X = 0.000000 | SAMPLE_0_Y = 0.000000 | SAMPLE_1_X = 0.000000 | SAMPLE_1_Y = 0.000000 | SAMPLE_2_X = 0.000000 | SAMPLE_2_Y = 0.000000 | SAMPLE_3_X = 0.000000 | SAMPLE_3_Y = 0.000000 }
0000000001058214: 0000: 40889801 00000000
t4 write SP_TP_BORDER_COLOR_BASE_ADDR (b302)
SP_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
- SP_TP_BORDER_COLOR_BASE_ADDR+0x1: 0
+ SP_TP_BORDER_COLOR_BASE_ADDR_HI: 0
000000000105821c: 0000: 48b30202 01011000 00000000
t4 write SP_PS_TP_BORDER_COLOR_BASE_ADDR (b180)
SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
- SP_PS_TP_BORDER_COLOR_BASE_ADDR+0x1: 0
+ SP_PS_TP_BORDER_COLOR_BASE_ADDR_HI: 0
0000000001058228: 0000: 40b18002 01011000 00000000
-t4 write VSC_DRAW_STRM_SIZE_ADDRESS_LO (0c03)
- VSC_DRAW_STRM_SIZE_ADDRESS_LO: 0x10fd000
+t4 write VSC_DRAW_STRM_SIZE_ADDRESS (0c03)
+ VSC_DRAW_STRM_SIZE_ADDRESS: 0x10fd000
VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0
0000000001058234: 0000: 480c0302 010fd000 00000000
-t4 write VSC_PRIM_STRM_ADDRESS_LO (0c30)
- VSC_PRIM_STRM_ADDRESS_LO: 0x105c000
+t4 write VSC_PRIM_STRM_ADDRESS (0c30)
+ VSC_PRIM_STRM_ADDRESS: 0x105c000
VSC_PRIM_STRM_ADDRESS_HI: 0
0000000001058240: 0000: 480c3002 0105c000 00000000
-t4 write VSC_DRAW_STRM_ADDRESS_LO (0c34)
- VSC_DRAW_STRM_ADDRESS_LO: 0x10dc800
+t4 write VSC_DRAW_STRM_ADDRESS (0c34)
+ VSC_DRAW_STRM_ADDRESS: 0x10dc800
VSC_DRAW_STRM_ADDRESS_HI: 0
000000000105824c: 0000: 400c3402 010dc800 00000000
t7 opcode: CP_EVENT_WRITE (46) (5 dwords)
00000000010582ac: 0000: 48840502 00000000 00ff00ff
t4 write RB_2D_DST_INFO (8c17)
RB_2D_DST_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX | FLAGS | SAMPLES = MSAA_ONE }
- RB_2D_DST_LO: 0x1013000
+ RB_2D_DST: 0x1013000
RB_2D_DST_HI: 0
RB_2D_DST_PITCH: 1024
00000000010582b8: 0000: 408c1704 00001330 01013000 00000000 00000010
-t4 write RB_2D_DST_FLAGS_LO (8c20)
- RB_2D_DST_FLAGS_LO: 0x1012000
+t4 write RB_2D_DST_FLAGS (8c20)
+ RB_2D_DST_FLAGS: 0x1012000
RB_2D_DST_FLAGS_HI: 0
RB_2D_DST_FLAGS_PITCH: 64 | 0x4000
00000000010582cc: 0000: 488c2083 01012000 00000000 00004001
mode: (null)
skip_ib2: g=0, l=0
draw[0] register values
-!+ 010fd000 VSC_DRAW_STRM_SIZE_ADDRESS_LO: 0x10fd000
+!+ 010fd000 VSC_DRAW_STRM_SIZE_ADDRESS: 0x10fd000
+ 00000000 VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0
-!+ 0105c000 VSC_PRIM_STRM_ADDRESS_LO: 0x105c000
+!+ 0105c000 VSC_PRIM_STRM_ADDRESS: 0x105c000
+ 00000000 VSC_PRIM_STRM_ADDRESS_HI: 0
-!+ 010dc800 VSC_DRAW_STRM_ADDRESS_LO: 0x10dc800
+!+ 010dc800 VSC_DRAW_STRM_ADDRESS: 0x10dc800
+ 00000000 VSC_DRAW_STRM_ADDRESS_HI: 0
!+ 03200000 UCHE_UNKNOWN_0E12: 0x3200000
!+ 00000004 UCHE_CLIENT_PF: { PERFSEL = 0x4 }
!+ 10f03080 RB_2D_BLIT_CNTL: { ROTATE = ROTATE_0 | SOLID_COLOR | COLOR_FORMAT = FMT6_8_8_8_8_UNORM | MASK = 0xf | IFMT = R2D_UNORM8 }
+ 00000000 RB_2D_UNKNOWN_8C01: 0
!+ 00001330 RB_2D_DST_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX | FLAGS | SAMPLES = MSAA_ONE }
-!+ 01013000 RB_2D_DST_LO: 0x1013000
+!+ 01013000 RB_2D_DST: 0x1013000
+ 00000000 RB_2D_DST_HI: 0
!+ 00000010 RB_2D_DST_PITCH: 1024
-!+ 01012000 RB_2D_DST_FLAGS_LO: 0x1012000
+!+ 01012000 RB_2D_DST_FLAGS: 0x1012000
+ 00000000 RB_2D_DST_FLAGS_HI: 0
!+ 00004001 RB_2D_DST_FLAGS_PITCH: 64 | 0x4000
+ 00000000 RB_2D_SRC_SOLID_C0: 0
!+ 00000008 SP_UNKNOWN_AE04: 0x8
!+ 0000003f SP_PERFCTR_ENABLE: { VS | HS | DS | GS | FS | CS }
!+ 01011000 SP_PS_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
- + 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR+0x1: 0
+ + 00000000 SP_PS_TP_BORDER_COLOR_BASE_ADDR_HI: 0
+ 00000000 SP_UNKNOWN_B182: 0
+ 00000000 SP_UNKNOWN_B183: 0
!+ 01011000 SP_TP_BORDER_COLOR_BASE_ADDR: 0x1011000
- + 00000000 SP_TP_BORDER_COLOR_BASE_ADDR+0x1: 0
+ + 00000000 SP_TP_BORDER_COLOR_BASE_ADDR_HI: 0
!+ 000000a2 SP_TP_UNKNOWN_B309: 0xa2
!+ 00100000 SP_UNKNOWN_B600: 0x100000
!+ 00000044 SP_UNKNOWN_B605: 0x44
t4 write RB_BLIT_DST_INFO (88d7)
RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
RB_BLIT_DST: 0x1013000
- RB_BLIT_DST+0x1: 0
+ RB_BLIT_DST_HI: 0
RB_BLIT_DST_PITCH: 1024
000000000115e028: 0000: 4888d704 00001807 01013000 00000000 00000010
t4 write RB_BLIT_FLAG_DST (88dc)
RB_BLIT_FLAG_DST: 0x1012000
- RB_BLIT_FLAG_DST+0x1: 0
+ RB_BLIT_FLAG_DST_HI: 0
RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
000000000115e03c: 0000: 4088dc83 01012000 00000000 00004001
t4 write RB_BLIT_BASE_GMEM (88d6)
+ 00000000 RB_BLIT_BASE_GMEM: 0
!+ 00001807 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
!+ 01013000 RB_BLIT_DST: 0x1013000
- + 00000000 RB_BLIT_DST+0x1: 0
+ + 00000000 RB_BLIT_DST_HI: 0
!+ 00000010 RB_BLIT_DST_PITCH: 1024
!+ 01012000 RB_BLIT_FLAG_DST: 0x1012000
- + 00000000 RB_BLIT_FLAG_DST+0x1: 0
+ + 00000000 RB_BLIT_FLAG_DST_HI: 0
!+ 00004001 RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
!+ 00000003 RB_BLIT_INFO: { UNK0 | GMEM | CLEAR_MASK = 0 }
!+ 7c400000 RB_CCU_CNTL: { OFFSET = 0xf8000 | GMEM }
RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
RB_DEPTH_BUFFER_PITCH: 0
RB_DEPTH_BUFFER_ARRAY_PITCH: 0
- RB_DEPTH_BUFFER_BASE_LO: 0
+ RB_DEPTH_BUFFER_BASE: 0
RB_DEPTH_BUFFER_BASE_HI: 0
RB_DEPTH_BUFFER_BASE_GMEM: 0
000000000115e074: 0000: 48887286 00000000 00000000 00000000 00000000 00000000 00000000
t4 write GRAS_SU_DEPTH_BUFFER_INFO (8098)
GRAS_SU_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
000000000115e090: 0000: 48809801 00000000
-t4 write GRAS_LRZ_BUFFER_BASE_LO (8103)
- GRAS_LRZ_BUFFER_BASE_LO: 0
+t4 write GRAS_LRZ_BUFFER_BASE (8103)
+ GRAS_LRZ_BUFFER_BASE: 0
GRAS_LRZ_BUFFER_BASE_HI: 0
GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO: 0
+ GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0
GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0
000000000115e098: 0000: 48810385 00000000 00000000 00000000 00000000 00000000
t4 write RB_STENCIL_INFO (8881)
RB_MRT[0].BUF_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | COLOR_TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX }
RB_MRT[0].PITCH: 1024
RB_MRT[0].ARRAY_PITCH: 262144
- RB_MRT[0].BASE_LO: 0x1013000
+ RB_MRT[0].BASE: 0x1013000
RB_MRT[0].BASE_HI: 0
RB_MRT[0].BASE_GMEM: 0
000000000115e0b8: 0000: 48882286 00000330 00000010 00001000 01013000 00000000 00000000
t4 write SP_FS_MRT[0].REG (a996)
SP_FS_MRT[0].REG: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
000000000115e0d4: 0000: 48a99601 00000030
-t4 write RB_MRT_FLAG_BUFFER[0].ADDR_LO (8903)
- RB_MRT_FLAG_BUFFER[0].ADDR_LO: 0x1012000
+t4 write RB_MRT_FLAG_BUFFER[0].ADDR (8903)
+ RB_MRT_FLAG_BUFFER[0].ADDR: 0x1012000
RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0
RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
000000000115e0dc: 0000: 40890383 01012000 00000000 00004001
t4 write HLSQ_VS_CNTL (b800)
HLSQ_VS_CNTL: { CONSTLEN = 4 | ENABLED }
000000000105419c: 0000: 48b80001 00000101
-t4 write SP_VS_OBJ_START_LO (a81c)
- SP_VS_OBJ_START_LO: 0x1054000 base=1054000, offset=0, size=12288
- SP_VS_OBJ_START_HI: 0 base=1054000, offset=0, size=12288
+t4 write SP_VS_OBJ_START (a81c)
+ SP_VS_OBJ_START: 0x1054000 base=1054000, offset=0, size=12288
0000000001054000: 0000: 00080009 42bc080b 10040004 64858008 10050005 64858009 10050006 6485800a
0000000001054020: 0020: 10040007 6485800b 00000000 03000000 00000000 00000000 00000000 00000000
*
- shaderdb: 0 last-baryf, 0 half, 3 full, 2 constlen
- shaderdb: 8 cat0, 0 cat1, 1 cat2, 4 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
+ SP_VS_OBJ_START_HI: 0
00000000010541a4: 0000: 48a81c02 01054000 00000000
t7 opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords)
{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 }
t4 write HLSQ_FS_CNTL (bb10)
HLSQ_FS_CNTL: { CONSTLEN = 0 | ENABLED }
0000000001054224: 0000: 40bb1001 00000100
-t4 write SP_FS_OBJ_START_LO (a983)
- SP_FS_OBJ_START_LO: 0x1054080 base=1054000, offset=128, size=12288
- SP_FS_OBJ_START_HI: 0 base=1054000, offset=128, size=12288
+t4 write SP_FS_OBJ_START (a983)
+ SP_FS_OBJ_START: 0x1054080 base=1054000, offset=128, size=12288
0000000001054080: 0000: 00002000 47300002 00002001 47300003 00002002 47300004 00002003 47308005
00000000010540a0: 0020: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000
*
- shaderdb: 3 last-baryf, 0 half, 2 full, 0 constlen
- shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
+ SP_FS_OBJ_START_HI: 0
000000000105422c: 0000: 40a98302 01054080 00000000
t7 opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords)
{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_FS_SHADER | NUM_UNIT = 1 }
000000000115c070: 0000: 40a01083 01053000 00000000 00000318
t4 write VFD_FETCH[0].BASE (a010)
VFD_FETCH[0].BASE: 0x1053000
- VFD_FETCH[0].BASE+0x1: 0
+ VFD_FETCH[0].BASE_HI: 0
VFD_FETCH[0].SIZE: 792
000000000115c070: 0000: 40a01083 01053000 00000000 00000318
group_id: 4
+ 00000000 GRAS_SC_VIEWPORT_SCISSOR[0].TL: { X = 0 | Y = 0 }
!+ 00ff00ff GRAS_SC_VIEWPORT_SCISSOR[0].BR: { X = 255 | Y = 255 }
+ 00000000 GRAS_UNKNOWN_8101: 0
- + 00000000 GRAS_LRZ_BUFFER_BASE_LO: 0
+ + 00000000 GRAS_LRZ_BUFFER_BASE: 0
+ 00000000 GRAS_LRZ_BUFFER_BASE_HI: 0
+ 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- + 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO: 0
+ + 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0
+ 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0
+ 00000000 GRAS_SAMPLE_CNTL: { 0 }
!+ 00010010 RB_RENDER_CNTL: { UNK4 | FLAG_MRTS = 0x1 }
!+ 00000330 RB_MRT[0].BUF_INFO: { COLOR_FORMAT = FMT6_8_8_8_8_UNORM | COLOR_TILE_MODE = TILE6_3 | COLOR_SWAP = WZYX }
!+ 00000010 RB_MRT[0].PITCH: 1024
!+ 00001000 RB_MRT[0].ARRAY_PITCH: 262144
-!+ 01013000 RB_MRT[0].BASE_LO: 0x1013000
+!+ 01013000 RB_MRT[0].BASE: 0x1013000
+ 00000000 RB_MRT[0].BASE_HI: 0
+ 00000000 RB_MRT[0].BASE_GMEM: 0
!+ dffe8440 RB_BLEND_RED_F32: -36679707902607360000.000000
+ 00000000 RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
+ 00000000 RB_DEPTH_BUFFER_PITCH: 0
+ 00000000 RB_DEPTH_BUFFER_ARRAY_PITCH: 0
- + 00000000 RB_DEPTH_BUFFER_BASE_LO: 0
+ + 00000000 RB_DEPTH_BUFFER_BASE: 0
+ 00000000 RB_DEPTH_BUFFER_BASE_HI: 0
+ 00000000 RB_DEPTH_BUFFER_BASE_GMEM: 0
+ 00000000 RB_Z_BOUNDS_MIN: 0.000000
+ 00000000 RB_BLIT_SCISSOR_TL: { X = 0 | Y = 0 }
+ 00ff00ff RB_BLIT_SCISSOR_BR: { X = 255 | Y = 255 }
+ 00000000 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE }
-!+ 01012000 RB_MRT_FLAG_BUFFER[0].ADDR_LO: 0x1012000
+!+ 01012000 RB_MRT_FLAG_BUFFER[0].ADDR: 0x1012000
+ 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0
!+ 00004001 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
!+ 00ffff00 VPC_VS_CLIP_CNTL: { CLIP_MASK = 0 | CLIP_DIST_03_LOC = 255 | CLIP_DIST_47_LOC = 255 }
!+ 0000fcfc VFD_CONTROL_5: { REGID_GSHEADER = r63.x | 0xfc00 }
+ 00000000 VFD_CONTROL_6: { 0 }
!+ 01053000 VFD_FETCH[0].BASE: 0x1053000
- + 00000000 VFD_FETCH[0].BASE+0x1: 0
+ + 00000000 VFD_FETCH[0].BASE_HI: 0
!+ 00000318 VFD_FETCH[0].SIZE: 792
!+ 00000024 VFD_FETCH[0].STRIDE: 36
!+ c8200000 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT }
!+ 00000002 SP_VS_PRIMITIVE_CNTL: { OUT = 2 }
!+ 0f000f08 SP_VS_OUT[0].REG: { A_REGID = r2.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0xf }
!+ 00000400 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 4 | OUTLOC2 = 0 | OUTLOC3 = 0 }
-!+ 01054000 SP_VS_OBJ_START_LO: 0x1054000 base=1054000, offset=0, size=12288
- + 00000000 SP_VS_OBJ_START_HI: 0 base=1054000, offset=0, size=12288
+!+ 01054000 SP_VS_OBJ_START: 0x1054000 base=1054000, offset=0, size=12288
0000000001054000: 0000: 00080009 42bc080b 10040004 64858008 10050005 64858009 10050006 6485800a
0000000001054020: 0020: 10040007 6485800b 00000000 03000000 00000000 00000000 00000000 00000000
*
- shaderdb: 0 last-baryf, 0 half, 3 full, 2 constlen
- shaderdb: 8 cat0, 0 cat1, 1 cat2, 4 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
+ + 00000000 SP_VS_OBJ_START_HI: 0
!+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 00000001 SP_VS_INSTRLEN: 1
+ 00000000 SP_HS_WAVE_INPUT_SIZE: 0
+ 00000000 SP_DS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 81500100 SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 2 | BRANCHSTACK = 0 | THREADSIZE = THREAD128 | VARYING | MERGEDREGS | 0x1000000 }
-!+ 01054080 SP_FS_OBJ_START_LO: 0x1054080 base=1054000, offset=128, size=12288
- + 00000000 SP_FS_OBJ_START_HI: 0 base=1054000, offset=128, size=12288
+!+ 01054080 SP_FS_OBJ_START: 0x1054080 base=1054000, offset=128, size=12288
0000000001054080: 0000: 00002000 47300002 00002001 47300003 00002002 47300004 00002003 47308005
00000000010540a0: 0020: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000
*
- shaderdb: 3 last-baryf, 0 half, 2 full, 0 constlen
- shaderdb: 5 cat0, 0 cat1, 4 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
+ + 00000000 SP_FS_OBJ_START_HI: 0
!+ 00000100 SP_BLEND_CNTL: { UNK8 }
+ 00000000 SP_SRGB_CNTL: { 0 }
!+ 0000000f SP_FS_RENDER_COMPONENTS: { RT0 = 0xf | RT1 = 0 | RT2 = 0 | RT3 = 0 | RT4 = 0 | RT5 = 0 | RT6 = 0 | RT7 = 0 }
t4 write RB_BLIT_DST_INFO (88d7)
RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
RB_BLIT_DST: 0x1013000
- RB_BLIT_DST+0x1: 0
+ RB_BLIT_DST_HI: 0
RB_BLIT_DST_PITCH: 1024
000000000115c03c: 0000: 4888d704 00001807 01013000 00000000 00000010
t4 write RB_BLIT_FLAG_DST (88dc)
RB_BLIT_FLAG_DST: 0x1012000
- RB_BLIT_FLAG_DST+0x1: 0
+ RB_BLIT_FLAG_DST_HI: 0
RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
000000000115c050: 0000: 4088dc83 01012000 00000000 00004001
t4 write RB_BLIT_BASE_GMEM (88d6)
+ 00000000 RB_BLIT_BASE_GMEM: 0
+ 00001807 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_3 | FLAGS | SAMPLES = MSAA_ONE | COLOR_SWAP = WZYX | COLOR_FORMAT = FMT6_8_8_8_8_UNORM }
+ 01013000 RB_BLIT_DST: 0x1013000
- + 00000000 RB_BLIT_DST+0x1: 0
+ + 00000000 RB_BLIT_DST_HI: 0
+ 00000010 RB_BLIT_DST_PITCH: 1024
+ 01012000 RB_BLIT_FLAG_DST: 0x1012000
- + 00000000 RB_BLIT_FLAG_DST+0x1: 0
+ + 00000000 RB_BLIT_FLAG_DST_HI: 0
+ 00004001 RB_BLIT_FLAG_DST_PITCH: { PITCH = 64 | ARRAY_PITCH = 1024 }
!+ 00000000 RB_BLIT_INFO: { CLEAR_MASK = 0 }
000000000115c068: 0000: 70460001 0000001e
RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
RB_DEPTH_BUFFER_PITCH: 0
RB_DEPTH_BUFFER_ARRAY_PITCH: 0
- RB_DEPTH_BUFFER_BASE_LO: 0
+ RB_DEPTH_BUFFER_BASE: 0
RB_DEPTH_BUFFER_BASE_HI: 0
RB_DEPTH_BUFFER_BASE_GMEM: 0
0000000001d91284: 0000: 48887286 00000000 00000000 00000000 00000000 00000000 00000000
t4 write GRAS_SU_DEPTH_BUFFER_INFO (8098)
GRAS_SU_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
0000000001d912a0: 0000: 48809801 00000000
-t4 write GRAS_LRZ_BUFFER_BASE_LO (8103)
- GRAS_LRZ_BUFFER_BASE_LO: 0
+t4 write GRAS_LRZ_BUFFER_BASE (8103)
+ GRAS_LRZ_BUFFER_BASE: 0
GRAS_LRZ_BUFFER_BASE_HI: 0
GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO: 0
+ GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0
GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0
0000000001d912a8: 0000: 48810385 00000000 00000000 00000000 00000000 00000000
t4 write RB_STENCIL_INFO (8881)
RB_MRT[0].BUF_INFO: { COLOR_FORMAT = FMT6_8_8_8_X8_UNORM | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WXYZ }
RB_MRT[0].PITCH: 8704
RB_MRT[0].ARRAY_PITCH: 12533760
- RB_MRT[0].BASE_LO: 0x1125000
+ RB_MRT[0].BASE: 0x1125000
RB_MRT[0].BASE_HI: 0
RB_MRT[0].BASE_GMEM: 0
0000000001d912c8: 0000: 48882286 00002031 00000088 0002fd00 01125000 00000000 00000000
t4 write SP_FS_MRT[0].REG (a996)
SP_FS_MRT[0].REG: { COLOR_FORMAT = FMT6_8_8_8_X8_UNORM }
0000000001d912e4: 0000: 48a99601 00000031
-t4 write RB_MRT_FLAG_BUFFER[0].ADDR_LO (8903)
- RB_MRT_FLAG_BUFFER[0].ADDR_LO: 0
+t4 write RB_MRT_FLAG_BUFFER[0].ADDR (8903)
+ RB_MRT_FLAG_BUFFER[0].ADDR: 0
RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0
RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
0000000001d912ec: 0000: 40890383 00000000 00000000 00000000
0000000001d913cc: 0000: 40a00701 00000001
t4 write VSC_BIN_SIZE (0c02)
VSC_BIN_SIZE: { WIDTH = 544 | HEIGHT = 480 }
- VSC_DRAW_STRM_SIZE_ADDRESS_LO: 0x1d65800
+ VSC_DRAW_STRM_SIZE_ADDRESS: 0x1d65800
VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0
0000000001d913d4: 0000: 400c0283 00001e11 01d65800 00000000
t4 write VSC_BIN_COUNT (0c06)
0000000001d913ec: 0000: 400c1020 04100000 04100001 04100002 04100003 04100400 04100401 04100402
0000000001d9140c: 0020: 04100403 04100800 04100801 04100802 04100803 00000000 00000000 00000000
*
-t4 write VSC_PRIM_STRM_ADDRESS_LO (0c30)
- VSC_PRIM_STRM_ADDRESS_LO: 0x1d67000
+t4 write VSC_PRIM_STRM_ADDRESS (0c30)
+ VSC_PRIM_STRM_ADDRESS: 0x1d67000
VSC_PRIM_STRM_ADDRESS_HI: 0
VSC_PRIM_STRM_PITCH: 0x1040
VSC_PRIM_STRM_LIMIT: 0x28000
0000000001d91470: 0000: 480c3004 01d67000 00000000 00001040 00028000
-t4 write VSC_DRAW_STRM_ADDRESS_LO (0c34)
- VSC_DRAW_STRM_ADDRESS_LO: 0x1d5d000
+t4 write VSC_DRAW_STRM_ADDRESS (0c34)
+ VSC_DRAW_STRM_ADDRESS: 0x1d5d000
VSC_DRAW_STRM_ADDRESS_HI: 0
VSC_DRAW_STRM_PITCH: 0x440
VSC_DRAW_STRM_LIMIT: 0xa000
t4 write SP_VS_INSTRLEN (a824)
SP_VS_INSTRLEN: 1
0000000001121030: 0000: 40a82401 00000001
-t4 write SP_VS_OBJ_START_LO (a81c)
- SP_VS_OBJ_START_LO: 0x1011000 base=1011000, offset=0, size=128
- SP_VS_OBJ_START_HI: 0 base=1011000, offset=0, size=128
+t4 write SP_VS_OBJ_START (a81c)
+ SP_VS_OBJ_START: 0x1011000 base=1011000, offset=0, size=128
0000000001011000: 0000: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000
*
:0:0000:0000[03000000x_00000000x] end
- shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen
- shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
+ SP_VS_OBJ_START_HI: 0
0000000001121038: 0000: 48a81c02 01011000 00000000
t7 opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords)
{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 }
0000000001116020: 0020: 40a0d001 0000000f 48a00001 00000101
t4 write VFD_FETCH[0].BASE (a010)
VFD_FETCH[0].BASE: 0x1016000
- VFD_FETCH[0].BASE+0x1: 0
+ VFD_FETCH[0].BASE_HI: 0
VFD_FETCH[0].SIZE: 1048576
VFD_FETCH[0].STRIDE: 12
0000000001116000: 0000: 40a01004 01016000 00000000 00100000 0000000c
!+ 00000002 CP_SCRATCH[0x7].REG: 2
:0,1,11,2
!+ 00001e11 VSC_BIN_SIZE: { WIDTH = 544 | HEIGHT = 480 }
-!+ 01d65800 VSC_DRAW_STRM_SIZE_ADDRESS_LO: 0x1d65800
+!+ 01d65800 VSC_DRAW_STRM_SIZE_ADDRESS: 0x1d65800
+ 00000000 VSC_DRAW_STRM_SIZE_ADDRESS_HI: 0
!+ 00001808 VSC_BIN_COUNT: { NX = 4 | NY = 3 }
!+ 04100000 VSC_PIPE_CONFIG[0].REG: { X = 0 | Y = 0 | W = 1 | H = 1 }
+ 00000000 VSC_PIPE_CONFIG[0x1d].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
+ 00000000 VSC_PIPE_CONFIG[0x1e].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
+ 00000000 VSC_PIPE_CONFIG[0x1f].REG: { X = 0 | Y = 0 | W = 0 | H = 0 }
-!+ 01d67000 VSC_PRIM_STRM_ADDRESS_LO: 0x1d67000
+!+ 01d67000 VSC_PRIM_STRM_ADDRESS: 0x1d67000
+ 00000000 VSC_PRIM_STRM_ADDRESS_HI: 0
!+ 00001040 VSC_PRIM_STRM_PITCH: 0x1040
!+ 00028000 VSC_PRIM_STRM_LIMIT: 0x28000
-!+ 01d5d000 VSC_DRAW_STRM_ADDRESS_LO: 0x1d5d000
+!+ 01d5d000 VSC_DRAW_STRM_ADDRESS: 0x1d5d000
+ 00000000 VSC_DRAW_STRM_ADDRESS_HI: 0
!+ 00000440 VSC_DRAW_STRM_PITCH: 0x440
!+ 0000a000 VSC_DRAW_STRM_LIMIT: 0xa000
!+ 059f086f GRAS_SC_WINDOW_SCISSOR_BR: { X = 2159 | Y = 1439 }
+ 00000000 GRAS_LRZ_CNTL: { 0 }
+ 00000000 GRAS_UNKNOWN_8101: 0
- + 00000000 GRAS_LRZ_BUFFER_BASE_LO: 0
+ + 00000000 GRAS_LRZ_BUFFER_BASE: 0
+ 00000000 GRAS_LRZ_BUFFER_BASE_HI: 0
+ 00000000 GRAS_LRZ_BUFFER_PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
- + 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO: 0
+ + 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE: 0
+ 00000000 GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI: 0
+ 00000000 GRAS_SAMPLE_CNTL: { 0 }
!+ 00000002 GRAS_UNKNOWN_8110: 0x2
!+ 00002031 RB_MRT[0].BUF_INFO: { COLOR_FORMAT = FMT6_8_8_8_X8_UNORM | COLOR_TILE_MODE = TILE6_LINEAR | COLOR_SWAP = WXYZ }
!+ 00000088 RB_MRT[0].PITCH: 8704
!+ 0002fd00 RB_MRT[0].ARRAY_PITCH: 12533760
-!+ 01125000 RB_MRT[0].BASE_LO: 0x1125000
+!+ 01125000 RB_MRT[0].BASE: 0x1125000
+ 00000000 RB_MRT[0].BASE_HI: 0
+ 00000000 RB_MRT[0].BASE_GMEM: 0
+ 00000000 RB_BLEND_RED_F32: 0.000000
+ 00000000 RB_DEPTH_BUFFER_INFO: { DEPTH_FORMAT = DEPTH6_NONE }
+ 00000000 RB_DEPTH_BUFFER_PITCH: 0
+ 00000000 RB_DEPTH_BUFFER_ARRAY_PITCH: 0
- + 00000000 RB_DEPTH_BUFFER_BASE_LO: 0
+ + 00000000 RB_DEPTH_BUFFER_BASE: 0
+ 00000000 RB_DEPTH_BUFFER_BASE_HI: 0
+ 00000000 RB_DEPTH_BUFFER_BASE_GMEM: 0
+ 00000000 RB_Z_BOUNDS_MIN: 0.000000
!+ 00001e11 RB_BIN_CONTROL2: { BINW = 544 | BINH = 480 }
+ 00000000 RB_MSAA_CNTL: { SAMPLES = MSAA_ONE }
+ 00000000 RB_UNKNOWN_88F0: 0
- + 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_LO: 0
+ + 00000000 RB_MRT_FLAG_BUFFER[0].ADDR: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0].ADDR_HI: 0
+ 00000000 RB_MRT_FLAG_BUFFER[0].PITCH: { PITCH = 0 | ARRAY_PITCH = 0 }
!+ 00000001 RB_UNKNOWN_8E01: 0x1
+ 00000000 VFD_INDEX_OFFSET: 0
+ 00000000 VFD_INSTANCE_START_OFFSET: 0
!+ 01016000 VFD_FETCH[0].BASE: 0x1016000
- + 00000000 VFD_FETCH[0].BASE+0x1: 0
+ + 00000000 VFD_FETCH[0].BASE_HI: 0
!+ 00100000 VFD_FETCH[0].SIZE: 1048576
!+ 0000000c VFD_FETCH[0].STRIDE: 12
!+ c7400000 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT }
!+ 00000f00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
+ 00000000 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
+ 00000000 SP_VS_OBJ_FIRST_EXEC_OFFSET: 0
-!+ 01011000 SP_VS_OBJ_START_LO: 0x1011000 base=1011000, offset=0, size=128
- + 00000000 SP_VS_OBJ_START_HI: 0 base=1011000, offset=0, size=128
+!+ 01011000 SP_VS_OBJ_START: 0x1011000 base=1011000, offset=0, size=128
0000000001011000: 0000: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000
*
:0:0000:0000[03000000x_00000000x] end
- shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen
- shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
+ + 00000000 SP_VS_OBJ_START_HI: 0
!+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 00000001 SP_VS_INSTRLEN: 1
+ 00000000 SP_HS_WAVE_INPUT_SIZE: 0
t4 write SP_VS_INSTRLEN (a824)
SP_VS_INSTRLEN: 1
0000000001120030: 0000: 40a82401 00000001
-t4 write SP_VS_OBJ_START_LO (a81c)
- SP_VS_OBJ_START_LO: 0x1012000 base=1012000, offset=0, size=128
- SP_VS_OBJ_START_HI: 0 base=1012000, offset=0, size=128
+t4 write SP_VS_OBJ_START (a81c)
+ SP_VS_OBJ_START: 0x1012000 base=1012000, offset=0, size=128
0000000001012000: 0000: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000
*
:0:0000:0000[03000000x_00000000x] end
- shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen
- shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
+ SP_VS_OBJ_START_HI: 0
0000000001120038: 0000: 48a81c02 01012000 00000000
t7 opcode: CP_LOAD_STATE6_GEOM (32) (4 dwords)
{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_VS_SHADER | NUM_UNIT = 1 }
t4 write SP_FS_INSTRLEN (ab05)
SP_FS_INSTRLEN: 88
0000000001120150: 0000: 40ab0501 00000058
-t4 write SP_FS_OBJ_START_LO (a983)
- SP_FS_OBJ_START_LO: 0x1013000 base=1013000, offset=0, size=11264
- SP_FS_OBJ_START_HI: 0 base=1013000, offset=0, size=11264
+t4 write SP_FS_OBJ_START (a983)
+ SP_FS_OBJ_START: 0x1013000 base=1013000, offset=0, size=11264
0000000001013000: 0000: 40400000 204cc000 00000000 204cc006 3e99999a 204cc004 20080014 42700008
0000000001013020: 0020: 10331003 6380000c 00000006 200cc00d 00041003 40700004 00000000 20244014
0000000001013040: 0040: 1036000c 4070000e 0000000d 200cc005 1034000c 4070000f 10251024 63820004
- shaderdb: 0 last-baryf, 0 half, 19 full, 29 constlen
- shaderdb: 1120 cat0, 48 cat1, 551 cat2, 512 cat3, 183 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 1326 sstall, 140 (ss), 0 (sy)
+ SP_FS_OBJ_START_HI: 0
0000000001120158: 0000: 40a98302 01013000 00000000
t7 opcode: CP_LOAD_STATE6_FRAG (34) (4 dwords)
{ DST_OFF = 0 | STATE_TYPE = ST6_SHADER | STATE_SRC = SS6_INDIRECT | STATE_BLOCK = SB6_FS_SHADER | NUM_UNIT = 88 }
0000000001116020: 0020: 40a0d001 0000000f 48a00001 00000101
t4 write VFD_FETCH[0].BASE (a010)
VFD_FETCH[0].BASE: 0x1016000
- VFD_FETCH[0].BASE+0x1: 0
+ VFD_FETCH[0].BASE_HI: 0
VFD_FETCH[0].SIZE: 1048576
VFD_FETCH[0].STRIDE: 12
0000000001116000: 0000: 40a01004 01016000 00000000 00100000 0000000c
{ EXT_SRC_ADDR = 0x11160a0 }
{ EXT_SRC_ADDR_HI = 0 }
00000000011160a0: 0000: 70b68003 003a0000 011160a0 00000000
-t4 write SP_IBO_LO (ab1a)
- SP_IBO_LO: 0x11160a0 base=1116000, offset=160, size=388
- SP_IBO_HI: 0 base=1116000, offset=160, size=388
+t4 write SP_IBO (ab1a)
+ SP_IBO: 0x11160a0 base=1116000, offset=160, size=388
+ SP_IBO_HI: 0
00000000011160b0: 0000: 48ab1a02 011160a0 00000000
t4 write SP_IBO_COUNT (ab20)
SP_IBO_COUNT: 0
+ 00000000 VFD_INDEX_OFFSET: 0
+ 00000000 VFD_INSTANCE_START_OFFSET: 0
+ 01016000 VFD_FETCH[0].BASE: 0x1016000
- + 00000000 VFD_FETCH[0].BASE+0x1: 0
+ + 00000000 VFD_FETCH[0].BASE_HI: 0
+ 00100000 VFD_FETCH[0].SIZE: 1048576
+ 0000000c VFD_FETCH[0].STRIDE: 12
+ c7400000 VFD_DECODE[0].INSTR: { IDX = 0 | OFFSET = 0 | FORMAT = FMT6_32_32_32_FLOAT | SWAP = WZYX | UNK30 | FLOAT }
+ 00000001 SP_VS_PRIMITIVE_CNTL: { OUT = 1 }
+ 00000f00 SP_VS_OUT[0].REG: { A_REGID = r0.x | A_COMPMASK = 0xf | B_REGID = r0.x | B_COMPMASK = 0 }
+ 00000000 SP_VS_VPC_DST[0].REG: { OUTLOC0 = 0 | OUTLOC1 = 0 | OUTLOC2 = 0 | OUTLOC3 = 0 }
-!+ 01012000 SP_VS_OBJ_START_LO: 0x1012000 base=1012000, offset=0, size=128
- + 00000000 SP_VS_OBJ_START_HI: 0 base=1012000, offset=0, size=128
+!+ 01012000 SP_VS_OBJ_START: 0x1012000 base=1012000, offset=0, size=128
0000000001012000: 0000: 00000000 03000000 00000000 00000000 00000000 00000000 00000000 00000000
*
:0:0000:0000[03000000x_00000000x] end
- shaderdb: 0 last-baryf, 0 half, 0 full, 0 constlen
- shaderdb: 5 cat0, 0 cat1, 0 cat2, 0 cat3, 0 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 0 sstall, 0 (ss), 0 (sy)
+ + 00000000 SP_VS_OBJ_START_HI: 0
+ 00000100 SP_VS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
+ 00000001 SP_VS_INSTRLEN: 1
+ 00000000 SP_HS_WAVE_INPUT_SIZE: 0
+ 00000000 SP_GS_CONFIG: { NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 81508980 SP_FS_CTRL_REG0: { HALFREGFOOTPRINT = 0 | FULLREGFOOTPRINT = 19 | BRANCHSTACK = 2 | THREADSIZE = THREAD128 | VARYING | MERGEDREGS | 0x1000000 }
+ 00000000 SP_FS_OBJ_FIRST_EXEC_OFFSET: 0
-!+ 01013000 SP_FS_OBJ_START_LO: 0x1013000 base=1013000, offset=0, size=11264
- + 00000000 SP_FS_OBJ_START_HI: 0 base=1013000, offset=0, size=11264
+!+ 01013000 SP_FS_OBJ_START: 0x1013000 base=1013000, offset=0, size=11264
0000000001013000: 0000: 40400000 204cc000 00000000 204cc006 3e99999a 204cc004 20080014 42700008
0000000001013020: 0020: 10331003 6380000c 00000006 200cc00d 00041003 40700004 00000000 20244014
0000000001013040: 0040: 1036000c 4070000e 0000000d 200cc005 1034000c 4070000f 10251024 63820004
- shaderdb: 0 last-baryf, 0 half, 19 full, 29 constlen
- shaderdb: 1120 cat0, 48 cat1, 551 cat2, 512 cat3, 183 cat4, 0 cat5, 0 cat6, 0 cat7
- shaderdb: 1326 sstall, 140 (ss), 0 (sy)
+ + 00000000 SP_FS_OBJ_START_HI: 0
!+ 00000100 SP_BLEND_CNTL: { UNK8 }
+ fcfcfc00 SP_FS_OUTPUT_CNTL0: { DEPTH_REGID = r63.x | SAMPMASK_REGID = r63.x | STENCILREF_REGID = r63.x }
!+ 00000001 SP_FS_OUTPUT_CNTL1: { MRT = 1 }
+ 00000005 SP_MODE_CONTROL: { CONSTANT_DEMOTION_ENABLE | 0x4 }
+ 00000100 SP_FS_CONFIG: { ENABLED | NTEX = 0 | NSAMP = 0 | NIBO = 0 }
!+ 00000058 SP_FS_INSTRLEN: 88
-!+ 011160a0 SP_IBO_LO: 0x11160a0 base=1116000, offset=160, size=388
- + 00000000 SP_IBO_HI: 0 base=1116000, offset=160, size=388
+!+ 011160a0 SP_IBO: 0x11160a0 base=1116000, offset=160, size=388
+ + 00000000 SP_IBO_HI: 0
+ 00000000 SP_IBO_COUNT: 0
+ 00000100 HLSQ_VS_CNTL: { CONSTLEN = 0 | ENABLED }
+ 00000000 HLSQ_HS_CNTL: { CONSTLEN = 0 }
t4 write RB_BLIT_DST_INFO (88d7)
RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WXYZ | COLOR_FORMAT = FMT6_8_8_8_X8_UNORM }
RB_BLIT_DST: 0x1125000
- RB_BLIT_DST+0x1: 0
+ RB_BLIT_DST_HI: 0
RB_BLIT_DST_PITCH: 8704
RB_BLIT_DST_ARRAY_PITCH: 12533760
0000000001116144: 0000: 4888d785 000018a0 01125000 00000000 00000088 0002fd00
+ 00000000 RB_BLIT_BASE_GMEM: 0
!+ 000018a0 RB_BLIT_DST_INFO: { TILE_MODE = TILE6_LINEAR | SAMPLES = MSAA_ONE | COLOR_SWAP = WXYZ | COLOR_FORMAT = FMT6_8_8_8_X8_UNORM }
!+ 01125000 RB_BLIT_DST: 0x1125000
- + 00000000 RB_BLIT_DST+0x1: 0
+ + 00000000 RB_BLIT_DST_HI: 0
!+ 00000088 RB_BLIT_DST_PITCH: 8704
!+ 0002fd00 RB_BLIT_DST_ARRAY_PITCH: 12533760
!+ 00000000 RB_BLIT_INFO: { CLEAR_MASK = 0 }
OUT_RING(ring, A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
A6XX_HLSQ_CS_CNTL_1_THREADSIZE(THREAD128));
- OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START_LO, 2);
+ OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START, 2);
OUT_RELOC(ring, v->bo, 0, 0, 0); /* SP_CS_OBJ_START_LO/HI */
OUT_PKT4(ring, REG_A6XX_SP_CS_INSTRLEN, 1);
OUT_RING(ring, v->instrlen);
- OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START_LO, 2);
+ OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START, 2);
OUT_RELOC(ring, v->bo, 0, 0, 0);
OUT_PKT7(ring, CP_LOAD_STATE6_FRAG, 3);
CP_LOAD_STATE6_0_NUM_UNIT(kernel->num_bufs));
OUT_RB(ring, state);
- OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_LO, 2);
+ OUT_PKT4(ring, REG_A6XX_SP_CS_IBO, 2);
OUT_RB(ring, state);
OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_COUNT, 1);
dump_gpuaddr(gpuaddr_lo | (((uint64_t)dword) << 32), level);
}
+static void
+reg_dump_gpuaddr64(const char *name, uint64_t qword, int level)
+{
+ dump_gpuaddr(qword, level);
+}
static void
dump_shader(const char *ext, void *buf, int bufsz)
disasm_gpuaddr(name, gpuaddr_lo | (((uint64_t)dword) << 32), level);
}
+static void
+reg_disasm_gpuaddr64(const char *name, uint64_t qword, int level)
+{
+ disasm_gpuaddr(name, qword, level);
+}
+
/* Find the value of the TEX_COUNT register that corresponds to the named
* TEX_SAMP/TEX_CONST reg.
*
* Registers with special handling (rnndec_decode() handles rest):
*/
#define REG(x, fxn) { #x, fxn }
+#define REG64(x, fxn) { #x, .fxn64 = fxn, .is_reg64 = true }
static struct {
const char *regname;
void (*fxn)(const char *name, uint32_t dword, int level);
+ void (*fxn64)(const char *name, uint64_t qword, int level);
uint32_t regbase;
+ bool is_reg64;
} reg_a2xx[] = {
REG(CP_SCRATCH_REG0, reg_dump_scratch),
REG(CP_SCRATCH_REG1, reg_dump_scratch),
REG(CP_SCRATCH[0x6].REG, reg_dump_scratch),
REG(CP_SCRATCH[0x7].REG, reg_dump_scratch),
- REG(SP_VS_OBJ_START_LO, reg_gpuaddr_lo),
- REG(SP_VS_OBJ_START_HI, reg_disasm_gpuaddr_hi),
- REG(SP_HS_OBJ_START_LO, reg_gpuaddr_lo),
- REG(SP_HS_OBJ_START_HI, reg_disasm_gpuaddr_hi),
- REG(SP_DS_OBJ_START_LO, reg_gpuaddr_lo),
- REG(SP_DS_OBJ_START_HI, reg_disasm_gpuaddr_hi),
- REG(SP_GS_OBJ_START_LO, reg_gpuaddr_lo),
- REG(SP_GS_OBJ_START_HI, reg_disasm_gpuaddr_hi),
- REG(SP_FS_OBJ_START_LO, reg_gpuaddr_lo),
- REG(SP_FS_OBJ_START_HI, reg_disasm_gpuaddr_hi),
- REG(SP_CS_OBJ_START_LO, reg_gpuaddr_lo),
- REG(SP_CS_OBJ_START_HI, reg_disasm_gpuaddr_hi),
-
- REG(SP_VS_TEX_CONST_LO, reg_gpuaddr_lo),
- REG(SP_VS_TEX_CONST_HI, reg_dump_tex_const_hi),
- REG(SP_VS_TEX_SAMP_LO, reg_gpuaddr_lo),
- REG(SP_VS_TEX_SAMP_HI, reg_dump_tex_samp_hi),
- REG(SP_HS_TEX_CONST_LO, reg_gpuaddr_lo),
- REG(SP_HS_TEX_CONST_HI, reg_dump_tex_const_hi),
- REG(SP_HS_TEX_SAMP_LO, reg_gpuaddr_lo),
- REG(SP_HS_TEX_SAMP_HI, reg_dump_tex_samp_hi),
- REG(SP_DS_TEX_CONST_LO, reg_gpuaddr_lo),
- REG(SP_DS_TEX_CONST_HI, reg_dump_tex_const_hi),
- REG(SP_DS_TEX_SAMP_LO, reg_gpuaddr_lo),
- REG(SP_DS_TEX_SAMP_HI, reg_dump_tex_samp_hi),
- REG(SP_GS_TEX_CONST_LO, reg_gpuaddr_lo),
- REG(SP_GS_TEX_CONST_HI, reg_dump_tex_const_hi),
- REG(SP_GS_TEX_SAMP_LO, reg_gpuaddr_lo),
- REG(SP_GS_TEX_SAMP_HI, reg_dump_tex_samp_hi),
- REG(SP_FS_TEX_CONST_LO, reg_gpuaddr_lo),
- REG(SP_FS_TEX_CONST_HI, reg_dump_tex_const_hi),
- REG(SP_FS_TEX_SAMP_LO, reg_gpuaddr_lo),
- REG(SP_FS_TEX_SAMP_HI, reg_dump_tex_samp_hi),
- REG(SP_CS_TEX_CONST_LO, reg_gpuaddr_lo),
- REG(SP_CS_TEX_CONST_HI, reg_dump_tex_const_hi),
- REG(SP_CS_TEX_SAMP_LO, reg_gpuaddr_lo),
- REG(SP_CS_TEX_SAMP_HI, reg_dump_tex_samp_hi),
+ REG64(SP_VS_OBJ_START, reg_disasm_gpuaddr64),
+ REG64(SP_HS_OBJ_START, reg_disasm_gpuaddr64),
+ REG64(SP_DS_OBJ_START, reg_disasm_gpuaddr64),
+ REG64(SP_GS_OBJ_START, reg_disasm_gpuaddr64),
+ REG64(SP_FS_OBJ_START, reg_disasm_gpuaddr64),
+ REG64(SP_CS_OBJ_START, reg_disasm_gpuaddr64),
+
+ REG64(SP_VS_TEX_CONST, reg_dump_gpuaddr64),
+ REG64(SP_VS_TEX_SAMP, reg_dump_gpuaddr64),
+ REG64(SP_HS_TEX_CONST, reg_dump_gpuaddr64),
+ REG64(SP_HS_TEX_SAMP, reg_dump_gpuaddr64),
+ REG64(SP_DS_TEX_CONST, reg_dump_gpuaddr64),
+ REG64(SP_DS_TEX_SAMP, reg_dump_gpuaddr64),
+ REG64(SP_GS_TEX_CONST, reg_dump_gpuaddr64),
+ REG64(SP_GS_TEX_SAMP, reg_dump_gpuaddr64),
+ REG64(SP_FS_TEX_CONST, reg_dump_gpuaddr64),
+ REG64(SP_FS_TEX_SAMP, reg_dump_gpuaddr64),
+ REG64(SP_CS_TEX_CONST, reg_dump_gpuaddr64),
+ REG64(SP_CS_TEX_SAMP, reg_dump_gpuaddr64),
{NULL},
}, *type0_reg;
* might be useful for other gen's too, but at least a5xx has
* the _HI/_LO suffix we can look for. Maybe a better approach
* would be some special annotation in the xml..
+ * for a6xx use "address" and "waddress" types
+ *
*/
- if (options->gpu_id >= 500) {
+ if (options->gpu_id >= 600) {
+ if (!strcmp(info->typeinfo->name, "address") ||
+ !strcmp(info->typeinfo->name, "waddress")) {
+ gpuaddr = (((uint64_t)reg_val(regbase+1)) << 32) | dword;
+ }
+ } else if (options->gpu_id >= 500) {
if (endswith(regbase, "_HI") && endswith(regbase-1, "_LO")) {
gpuaddr = (((uint64_t)dword) << 32) | reg_val(regbase-1);
} else if (endswith(regbase, "_LO") && endswith(regbase+1, "_HI")) {
for (unsigned idx = 0; type0_reg[idx].regname; idx++) {
if (type0_reg[idx].regbase == regbase) {
- type0_reg[idx].fxn(type0_reg[idx].regname, dword, level);
+ if (type0_reg[idx].is_reg64) {
+ uint64_t qword = (((uint64_t)reg_val(regbase+1)) << 32) | dword;
+ type0_reg[idx].fxn64(type0_reg[idx].regname, qword, level);
+ } else {
+ type0_reg[idx].fxn(type0_reg[idx].regname, dword, level);
+ }
break;
}
}
-- to avoid relying on RB_BLIT_DST also getting written:
for n = 0,r.RB_FS_OUTPUT_CNTL1.MRT-1 do
if r.RB_MRT[n].BASE_GMEM == r.RB_BLIT_BASE_GMEM then
- sysmem = r.RB_MRT[n].BASE_LO | (r.RB_MRT[n].BASE_HI << 32)
- flag = r.RB_MRT_FLAG_BUFFER[n].ADDR_LO | (r.RB_MRT_FLAG_BUFFER[n].ADDR_HI << 32)
+ sysmem = r.RB_MRT[n].BASE
+ flag = r.RB_MRT_FLAG_BUFFER[n].ADDR
break
end
end
if sysmem == 0 and r.RB_BLIT_BASE_GMEM == r.RB_DEPTH_BUFFER_BASE_GMEM then
- sysmem = r.RB_DEPTH_BUFFER_BASE_LO | (r.RB_DEPTH_BUFFER_BASE_HI << 32)
- flag = r.RB_DEPTH_FLAG_BUFFER_BASE_LO | (r.RB_DEPTH_FLAG_BUFFER_BASE_HI << 32)
+ sysmem = r.RB_DEPTH_BUFFER_BASE
+ flag = r.RB_DEPTH_FLAG_BUFFER_BASE
end
--NOTE this can get confused by previous blits:
--if sysmem == 0 then
-- -- fallback:
- -- sysmem = r.RB_BLIT_DST_LO | (r.RB_BLIT_DST_HI << 32)
- -- flag = r.RB_BLIT_FLAG_DST_LO | (r.RB_BLIT_FLAG_DST_HI << 32)
+ -- sysmem = r.RB_BLIT_DST
+ -- flag = r.RB_BLIT_FLAG_DST
--end
if not r.RB_BLIT_DST_INFO.FLAGS then
flag = 0
end
- -- TODO maybe just emit RB_BLIT_DST_LO/HI for clears.. otherwise
+ -- TODO maybe just emit RB_BLIT_DST/HI for clears.. otherwise
-- we get confused by stale values in registers.. not sure
-- if this is a problem w/ blob
push_mrt(r.RB_BLIT_DST_INFO.COLOR_FORMAT,
-- blob sometimes uses CP_BLIT for resolves, so filter those out:
-- TODO it would be nice to not hard-code GMEM addr:
-- TODO I guess the src can be an offset from GMEM addr..
- if r.SP_PS_2D_SRC_LO == 0x100000 and not r.RB_2D_BLIT_CNTL.SOLID_COLOR then
+ if r.SP_PS_2D_SRC == 0x100000 and not r.RB_2D_BLIT_CNTL.SOLID_COLOR then
resolved[0] = 1
return
end
r.GRAS_2D_DST_BR.X + 1,
r.GRAS_2D_DST_BR.Y + 1,
"MSAA_ONE",
- r.RB_2D_DST_LO | (r.RB_2D_DST_HI << 32),
- r.RB_2D_DST_FLAGS_LO | (r.RB_2D_DST_FLAGS_HI << 32),
+ r.RB_2D_DST,
+ r.RB_2D_DST_FLAGS,
-1)
if r.RB_2D_BLIT_CNTL.SOLID_COLOR then
- dbg("CLEAR=%x\n", r.RB_2D_DST_LO | (r.RB_2D_DST_HI << 32))
- cleared[r.RB_2D_DST_LO | (r.RB_2D_DST_HI << 32)] = 1
+ dbg("CLEAR=%x\n", r.RB_2D_DST)
+ cleared[r.RB_2D_DST] = 1
else
push_source(r.SP_2D_SRC_FORMAT.COLOR_FORMAT,
r.GRAS_2D_SRC_BR_X.X + 1,
r.GRAS_2D_SRC_BR_Y.Y + 1,
"MSAA_ONE",
- r.SP_PS_2D_SRC_LO | (r.SP_PS_2D_SRC_HI << 32),
- r.SP_PS_2D_SRC_FLAGS_LO | (r.SP_PS_2D_SRC_FLAGS_HI << 32))
+ r.SP_PS_2D_SRC,
+ r.SP_PS_2D_SRC_FLAGS)
end
blits = blits + 1
finish()
r.GRAS_SC_SCREEN_SCISSOR[0].BR.X + 1,
r.GRAS_SC_SCREEN_SCISSOR[0].BR.Y + 1,
r.RB_MSAA_CNTL.SAMPLES,
- r.RB_MRT[n].BASE_LO | (r.RB_MRT[n].BASE_HI << 32),
- r.RB_MRT_FLAG_BUFFER[n].ADDR_LO | (r.RB_MRT_FLAG_BUFFER[n].ADDR_HI << 32),
+ r.RB_MRT[n].BASE,
+ r.RB_MRT_FLAG_BUFFER[n].ADDR,
r.RB_MRT[n].BASE_GMEM)
end
end
- local depthbase = r.RB_DEPTH_BUFFER_BASE_LO |
- (r.RB_DEPTH_BUFFER_BASE_HI << 32)
+ local depthbase = r.RB_DEPTH_BUFFER_BASE
if depthbase ~= 0 then
push_mrt(r.RB_DEPTH_BUFFER_INFO.DEPTH_FORMAT,
r.GRAS_SC_SCREEN_SCISSOR[0].BR.Y + 1,
r.RB_MSAA_CNTL.SAMPLES,
depthbase,
- r.RB_DEPTH_FLAG_BUFFER_BASE_LO | (r.RB_DEPTH_FLAG_BUFFER_BASE_HI << 32),
+ r.RB_DEPTH_FLAG_BUFFER_BASE,
r.RB_DEPTH_BUFFER_BASE_GMEM)
end
<bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
<bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
</reg32>
- <reg32 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS_LO"/>
- <reg32 offset="0x0c04" name="VSC_DRAW_STRM_SIZE_ADDRESS_HI"/>
<reg64 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS" type="waddress"/>
<reg32 offset="0x0c06" name="VSC_BIN_COUNT">
<bitfield name="NX" low="1" high="10" type="uint"/>
LIMIT is set to PITCH - 64, to make room for a bit of overflow
-->
- <reg32 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS_LO"/>
- <reg32 offset="0x0c31" name="VSC_PRIM_STRM_ADDRESS_HI"/>
<reg64 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS" type="waddress"/>
<reg32 offset="0x0c32" name="VSC_PRIM_STRM_PITCH"/>
<reg32 offset="0x0c33" name="VSC_PRIM_STRM_LIMIT"/>
- <reg32 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS_LO"/>
- <reg32 offset="0x0c35" name="VSC_DRAW_STRM_ADDRESS_HI"/>
<reg64 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS" type="waddress"/>
<reg32 offset="0x0c36" name="VSC_DRAW_STRM_PITCH"/>
<reg32 offset="0x0c37" name="VSC_DRAW_STRM_LIMIT"/>
<reg32 offset="0x8102" name="GRAS_2D_BLIT_INFO">
<bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
</reg32>
- <reg32 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE_LO"/>
- <reg32 offset="0x8104" name="GRAS_LRZ_BUFFER_BASE_HI"/>
<reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress"/>
<reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH">
<!-- TODO: fix the shr fields -->
increases beyond 1 page. Not sure if that is an actual limit or
not.
-->
- <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
- <reg32 offset="0x8107" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>
- <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress"/>
+ <reg64 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress"/>
<!-- 0x8108 invalid -->
<reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL">
<bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
restore for context switch, or just to simplify state setup to
not have to care about GMEM vs BYPASS mode.
-->
- <reg32 offset="0x5" name="BASE_LO"/>
- <reg32 offset="0x6" name="BASE_HI"/>
-
<!-- maybe something in low bits since alignment of 1 doesn't make sense? -->
<reg64 offset="0x5" name="BASE" type="waddress" align="1"/>
</reg32>
<reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" low="0" high="13" shr="6" type="uint"/>
<reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" low="0" high="27" shr="6" type="uint"/>
- <reg32 offset="0x8875" name="RB_DEPTH_BUFFER_BASE_LO"/>
- <reg32 offset="0x8876" name="RB_DEPTH_BUFFER_BASE_HI"/>
<reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress" align="64"/>
<reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM" low="12" high="31" shr="12"/>
</reg32>
<reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" low="0" high="11" shr="6" type="uint"/>
<reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" low="0" high="23" shr="6" type="uint"/>
- <reg32 offset="0x8884" name="RB_STENCIL_BUFFER_BASE_LO"/>
- <reg32 offset="0x8885" name="RB_STENCIL_BUFFER_BASE_HI"/>
<reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress" align="64"/>
<reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM" low="12" high="31" shr="12"/>
<reg32 offset="0x8887" name="RB_STENCILREF">
<bitfield name="UNK15" pos="15" type="boolean"/>
</reg32>
<reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress" align="64"/>
- <reg32 offset="0x88d8" name="RB_BLIT_DST_LO"/>
- <reg32 offset="0x88d9" name="RB_BLIT_DST_HI"/>
<reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" low="0" high="15" shr="6" type="uint"/>
<!-- array-pitch is size of layer -->
<reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint"/>
<reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress" align="64"/>
- <reg32 offset="0x88dc" name="RB_BLIT_FLAG_DST_LO"/>
- <reg32 offset="0x88dd" name="RB_BLIT_FLAG_DST_HI"/>
<reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH">
<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
<bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
</reg32>
<reg32 offset="0x88f4" name="RB_UNKNOWN_88F4" low="0" high="2"/>
<!-- 0x88f5-0x88ff invalid -->
- <reg32 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/>
- <reg32 offset="0x8901" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/>
<reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64"/>
<reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH">
<bitfield name="PITCH" low="0" high="6" shr="6" type="uint"/>
<bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
</reg32>
<array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8">
- <reg32 offset="0" name="ADDR_LO"/>
- <reg32 offset="1" name="ADDR_HI"/>
<reg64 offset="0" name="ADDR" type="waddress" align="64"/>
<reg32 offset="2" name="PITCH">
<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
</reg32>
</array>
<!-- 0x891b-0x8926 invalid -->
- <reg32 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR_LO"/>
- <reg32 offset="0x8928" name="RB_SAMPLE_COUNT_ADDR_HI"/>
<reg64 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR" type="waddress" align="16"/>
<!-- 0x8929-0x89ff invalid -->
<!-- 0x8c02-0x8c16 invalid -->
<!-- TODO: RB_2D_DST_INFO has 17 valid bits (doesn't match a6xx_2d_surf_info) -->
<reg32 offset="0x8c17" name="RB_2D_DST_INFO" type="a6xx_2d_surf_info"/>
- <reg32 offset="0x8c18" name="RB_2D_DST_LO"/>
- <reg32 offset="0x8c19" name="RB_2D_DST_HI"/>
<reg64 offset="0x8c18" name="RB_2D_DST" type="waddress" align="64"/>
<reg32 offset="0x8c1a" name="RB_2D_DST_PITCH" low="0" high="15" shr="6" type="uint"/>
<!-- this is a guess but seems likely (for NV12/IYUV): -->
<reg32 offset="0x8c1d" name="RB_2D_DST_PLANE_PITCH" low="0" high="15" shr="6" type="uint"/>
<reg64 offset="0x8c1e" name="RB_2D_DST_PLANE2" type="waddress" align="64"/>
- <reg32 offset="0x8c20" name="RB_2D_DST_FLAGS_LO"/>
- <reg32 offset="0x8c21" name="RB_2D_DST_FLAGS_HI"/>
<reg64 offset="0x8c20" name="RB_2D_DST_FLAGS" type="waddress" align="64"/>
<reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH" low="0" high="7" shr="6" type="uint"/>
<!-- this is a guess but seems likely (for NV12 with UBWC): -->
<bitfield name="B_EN" pos="23" type="boolean"/>
</reg32>
- <reg32 offset="0x9218" name="VPC_SO_STREAM_COUNTS_LO"/>
- <reg32 offset="0x9219" name="VPC_SO_STREAM_COUNTS_HI"/>
- <reg32 offset="0x9218" name="VPC_SO_STREAM_COUNTS" type="waddress" align="32"/>
+ <reg64 offset="0x9218" name="VPC_SO_STREAM_COUNTS" type="waddress" align="32"/>
<array offset="0x921a" name="VPC_SO" stride="7" length="4">
<reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/>
- <reg32 offset="0" name="BUFFER_BASE_LO"/>
- <reg32 offset="1" name="BUFFER_BASE_HI"/>
<reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/>
<reg32 offset="3" name="NCOMP" low="0" high="9"/> <!-- component count -->
<reg32 offset="4" name="BUFFER_OFFSET" low="2" high="31" shr="2"/>
<reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/>
- <reg32 offset="5" name="FLUSH_BASE_LO"/>
- <reg32 offset="6" name="FLUSH_BASE_HI"/>
</array>
<reg32 offset="0x9236" name="VPC_POINT_COORD_INVERT">
<!-- TODO: 0x9e00-0xa000 range incomplete -->
<reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/>
<reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
- <reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR_LO"/>
- <reg32 offset="0x9e09" name="PC_TESSFACTOR_ADDR_HI"/>
- <reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR" type="waddress" align="32"/>
+ <reg64 offset="0x9e08" name="PC_TESSFACTOR_ADDR" type="waddress" align="32"/>
<!-- These match the contents of CP_SET_BIN_DATA (not written directly) -->
<reg32 offset="0x9e11" name="PC_VSTREAM_CONTROL">
<reg32 offset="0xa00e" name="VFD_INDEX_OFFSET"/>
<reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET"/>
<array offset="0xa010" name="VFD_FETCH" stride="4" length="32">
- <reg64 offset="0x0" name="BASE" type="address"/>
- <reg32 offset="0x0" name="BASE_LO"/>
- <reg32 offset="0x1" name="BASE_HI"/>
+ <reg64 offset="0x0" name="BASE" type="address" align="1"/>
<reg32 offset="0x2" name="SIZE" type="uint"/>
<reg32 offset="0x3" name="STRIDE" type="uint"/>
</array>
</bitset>
<reg32 offset="0xa81b" name="SP_VS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
- <reg32 offset="0xa81c" name="SP_VS_OBJ_START_LO"/>
- <reg32 offset="0xa81d" name="SP_VS_OBJ_START_HI"/>
+ <reg64 offset="0xa81c" name="SP_VS_OBJ_START" type="address" align="32"/>
<reg32 offset="0xa81e" name="SP_VS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
<reg64 offset="0xa81f" name="SP_VS_PVT_MEM_ADDR" type="waddress" align="32"/>
<reg32 offset="0xa821" name="SP_VS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
<reg32 offset="0xa831" name="SP_HS_WAVE_INPUT_SIZE" low="0" high="7" type="uint"/>
<reg32 offset="0xa833" name="SP_HS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
- <reg32 offset="0xa834" name="SP_HS_OBJ_START_LO"/>
- <reg32 offset="0xa835" name="SP_HS_OBJ_START_HI"/>
+ <reg64 offset="0xa834" name="SP_HS_OBJ_START" type="address" align="32"/>
<reg32 offset="0xa836" name="SP_HS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
<reg64 offset="0xa837" name="SP_HS_PVT_MEM_ADDR" type="waddress" align="32"/>
<reg32 offset="0xa839" name="SP_HS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
</array>
<reg32 offset="0xa85b" name="SP_DS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
- <reg32 offset="0xa85c" name="SP_DS_OBJ_START_LO"/>
- <reg32 offset="0xa85d" name="SP_DS_OBJ_START_HI"/>
+ <reg64 offset="0xa85c" name="SP_DS_OBJ_START" type="address" align="32"/>
<reg32 offset="0xa85e" name="SP_DS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
<reg64 offset="0xa85f" name="SP_DS_PVT_MEM_ADDR" type="waddress" align="32"/>
<reg32 offset="0xa861" name="SP_DS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
</array>
<reg32 offset="0xa88c" name="SP_GS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
- <reg32 offset="0xa88d" name="SP_GS_OBJ_START_LO"/>
- <reg32 offset="0xa88e" name="SP_GS_OBJ_START_HI"/>
+ <reg64 offset="0xa88d" name="SP_GS_OBJ_START" type="address" align="32"/>
<reg32 offset="0xa88f" name="SP_GS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
<reg64 offset="0xa890" name="SP_GS_PVT_MEM_ADDR" type="waddress" align="32"/>
<reg32 offset="0xa892" name="SP_GS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
<reg32 offset="0xa895" name="SP_GS_INSTRLEN" type="uint"/>
<reg32 offset="0xa896" name="SP_GS_PVT_MEM_HW_STACK_OFFSET" low="0" high="18" shr="11"/>
- <reg32 offset="0xa8a0" name="SP_VS_TEX_SAMP_LO"/>
- <reg32 offset="0xa8a1" name="SP_VS_TEX_SAMP_HI"/>
- <reg32 offset="0xa8a2" name="SP_HS_TEX_SAMP_LO"/>
- <reg32 offset="0xa8a3" name="SP_HS_TEX_SAMP_HI"/>
- <reg32 offset="0xa8a4" name="SP_DS_TEX_SAMP_LO"/>
- <reg32 offset="0xa8a5" name="SP_DS_TEX_SAMP_HI"/>
- <reg32 offset="0xa8a6" name="SP_GS_TEX_SAMP_LO"/>
- <reg32 offset="0xa8a7" name="SP_GS_TEX_SAMP_HI"/>
- <reg32 offset="0xa8a8" name="SP_VS_TEX_CONST_LO"/>
- <reg32 offset="0xa8a9" name="SP_VS_TEX_CONST_HI"/>
- <reg32 offset="0xa8aa" name="SP_HS_TEX_CONST_LO"/>
- <reg32 offset="0xa8ab" name="SP_HS_TEX_CONST_HI"/>
- <reg32 offset="0xa8ac" name="SP_DS_TEX_CONST_LO"/>
- <reg32 offset="0xa8ad" name="SP_DS_TEX_CONST_HI"/>
- <reg32 offset="0xa8ae" name="SP_GS_TEX_CONST_LO"/>
- <reg32 offset="0xa8af" name="SP_GS_TEX_CONST_HI"/>
+ <reg64 offset="0xa8a0" name="SP_VS_TEX_SAMP" type="address" align="16"/>
+ <reg64 offset="0xa8a2" name="SP_HS_TEX_SAMP" type="address" align="16"/>
+ <reg64 offset="0xa8a4" name="SP_DS_TEX_SAMP" type="address" align="16"/>
+ <reg64 offset="0xa8a6" name="SP_GS_TEX_SAMP" type="address" align="16"/>
+ <reg64 offset="0xa8a8" name="SP_VS_TEX_CONST" type="address" align="64"/>
+ <reg64 offset="0xa8aa" name="SP_HS_TEX_CONST" type="address" align="64"/>
+ <reg64 offset="0xa8ac" name="SP_DS_TEX_CONST" type="address" align="64"/>
+ <reg64 offset="0xa8ae" name="SP_GS_TEX_CONST" type="address" align="64"/>
<reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
<reg32 offset="0xa981" name="SP_FS_BRANCH_COND" type="hex">
</reg32>
<reg32 offset="0xa982" name="SP_FS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
- <reg32 offset="0xa983" name="SP_FS_OBJ_START_LO"/>
- <reg32 offset="0xa984" name="SP_FS_OBJ_START_HI"/>
+ <reg64 offset="0xa983" name="SP_FS_OBJ_START" type="address" align="32"/>
<reg32 offset="0xa985" name="SP_FS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
<reg64 offset="0xa986" name="SP_FS_PVT_MEM_ADDR" type="waddress" align="32"/>
<reg32 offset="0xa988" name="SP_FS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
<reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" type="uint"/>
- <reg32 offset="0xa9e0" name="SP_FS_TEX_SAMP_LO"/>
- <reg32 offset="0xa9e1" name="SP_FS_TEX_SAMP_HI"/>
- <reg32 offset="0xa9e2" name="SP_CS_TEX_SAMP_LO"/>
- <reg32 offset="0xa9e3" name="SP_CS_TEX_SAMP_HI"/>
- <reg32 offset="0xa9e4" name="SP_FS_TEX_CONST_LO"/>
- <reg32 offset="0xa9e5" name="SP_FS_TEX_CONST_HI"/>
- <reg32 offset="0xa9e6" name="SP_CS_TEX_CONST_LO"/>
- <reg32 offset="0xa9e7" name="SP_CS_TEX_CONST_HI"/>
-
<array offset="0xa9e8" name="SP_CS_BINDLESS_BASE" stride="2" length="5">
<reg64 offset="0" name="ADDR" type="waddress"/>
</array>
<reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
<reg32 offset="0xa9b3" name="SP_CS_OBJ_FIRST_EXEC_OFFSET" type="uint"/>
- <reg32 offset="0xa9b4" name="SP_CS_OBJ_START_LO"/>
- <reg32 offset="0xa9b5" name="SP_CS_OBJ_START_HI"/>
+ <reg64 offset="0xa9b4" name="SP_CS_OBJ_START" type="address" align="32"/>
<reg32 offset="0xa9b6" name="SP_CS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param"/>
<reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_ADDR" align="32"/>
<reg32 offset="0xa9b9" name="SP_CS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size"/>
</doc>
</reg32>
+ <reg64 offset="0xa9e0" name="SP_FS_TEX_SAMP" type="address" align="16"/>
+ <reg64 offset="0xa9e2" name="SP_CS_TEX_SAMP" type="address" align="16"/>
+ <reg64 offset="0xa9e4" name="SP_FS_TEX_CONST" type="address" align="64"/>
+ <reg64 offset="0xa9e6" name="SP_CS_TEX_CONST" type="address" align="64"/>
<!--
IBO state for compute shader:
-->
- <reg32 offset="0xa9f2" name="SP_CS_IBO_LO"/>
- <reg32 offset="0xa9f3" name="SP_CS_IBO_HI"/>
+ <reg64 offset="0xa9f2" name="SP_CS_IBO" type="address" align="16"/>
<reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" type="uint"/>
<!-- always 0x5 ? -->
Combined IBO state for 3d pipe, used for Image and SSBO write/atomic
instructions VS/HS/DS/GS/FS. See SP_CS_IBO_* for compute shaders.
-->
- <reg32 offset="0xab1a" name="SP_IBO_LO"/>
- <reg32 offset="0xab1b" name="SP_IBO_HI"/>
+ <reg64 offset="0xab1a" name="SP_IBO" type="address" align="16"/>
<reg32 offset="0xab20" name="SP_IBO_COUNT" type="uint"/>
<reg32 offset="0xacc0" name="SP_2D_DST_FORMAT">
"a6xx_sp_ps_tp_cluster" but this actually specifies the border
color base for compute shaders.
-->
- <reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
+ <reg64 offset="0xb180" name="SP_PS_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128"/>
<!-- always 0x0 ? -->
<reg32 offset="0xb182" name="SP_UNKNOWN_B182"/>
<reg32 offset="0xb183" name="SP_UNKNOWN_B183"/>
</reg32>
<!-- looks to work in the same way as a5xx: -->
- <reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address"/>
- <reg32 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR_LO"/>
- <reg32 offset="0xb303" name="SP_TP_BORDER_COLOR_BASE_ADDR_HI"/>
+ <reg64 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR" type="address" align="128"/>
<reg32 offset="0xb304" name="SP_TP_SAMPLE_CONFIG" type="a6xx_sample_config"/>
<reg32 offset="0xb305" name="SP_TP_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
<reg32 offset="0xb306" name="SP_TP_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
<bitfield name="WIDTH" low="0" high="14" type="uint"/>
<bitfield name="HEIGHT" low="15" high="29" type="uint"/>
</reg32>
- <reg32 offset="0xb4c2" name="SP_PS_2D_SRC_LO"/>
- <reg32 offset="0xb4c3" name="SP_PS_2D_SRC_HI"/>
<reg64 offset="0xb4c2" name="SP_PS_2D_SRC" type="waddress"/>
<reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH">
<bitfield name="PITCH" low="9" high="24" shr="6" type="uint"/>
</reg32>
- <reg32 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS_LO"/>
- <reg32 offset="0xb4cb" name="SP_PS_2D_SRC_FLAGS_HI"/>
<reg64 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS" type="waddress"/>
<reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH">
<bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
else:
self.fields = []
- def dump_pack_struct(self, prefix=None, array=None):
+ def dump_pack_struct(self, prefix=None, array=None, bit_size=32):
def field_name(prefix, name):
if f.name:
name = f.name.lower()
value_name = "dword"
print("struct %s {" % prefix)
for f in self.fields:
- if f.type == "waddress":
- value_name = "qword"
if f.type in [ "address", "waddress" ]:
tab_to(" __bo_type", "bo;")
tab_to(" uint32_t", "bo_offset;")
+ if bit_size == 64:
+ value_name = "qword"
continue
name = field_name(prefix, f.name)
def dump_pack_struct(self):
if self.bitset.inline:
- self.bitset.dump_pack_struct(self.full_name, not self.array == None)
+ self.bitset.dump_pack_struct(self.full_name, not self.array == None, self.bit_size)
def parse_variants(attrs):
if (elems[i]->length != 1)
res->name = appendidx(ctx, res->name, idx, elems[i]->index);
if (offset) {
- asprintf (&tmp, "%s+%s%#"PRIx64"%s", res->name, ctx->colors->err, offset, ctx->colors->reset);
+ /* use _HI suffix for addresses */
+ if (offset == 1 &&
+ (!strcmp(res->typeinfo->name, "address") ||
+ !strcmp(res->typeinfo->name, "waddress"))) {
+ asprintf (&tmp, "%s_HI", res->name);
+ } else {
+ asprintf (&tmp, "%s+%s%#"PRIx64"%s", res->name, ctx->colors->err, offset, ctx->colors->reset);
+ }
free(res->name);
res->name = tmp;
}
tu_cs_emit(cs, iview->SP_PS_2D_SRC_SIZE);
tu_cs_image_ref_2d(cs, iview, layer, true);
- tu_cs_emit_pkt4(cs, REG_A6XX_SP_PS_2D_SRC_FLAGS_LO, 3);
+ tu_cs_emit_pkt4(cs, REG_A6XX_SP_PS_2D_SRC_FLAGS, 3);
tu_cs_image_flag_ref(cs, iview, layer);
}
.unk20 = 1,
.unk22 = 1),
A6XX_SP_PS_2D_SRC_SIZE(.width = width, .height = height),
- A6XX_SP_PS_2D_SRC_LO((uint32_t) va),
- A6XX_SP_PS_2D_SRC_HI(va >> 32),
+ A6XX_SP_PS_2D_SRC(.qword = va),
A6XX_SP_PS_2D_SRC_PITCH(.pitch = pitch));
}
tu_cs_emit(cs, iview->RB_2D_DST_INFO);
tu_cs_image_ref_2d(cs, iview, layer, false);
- tu_cs_emit_pkt4(cs, REG_A6XX_RB_2D_DST_FLAGS_LO, 3);
+ tu_cs_emit_pkt4(cs, REG_A6XX_RB_2D_DST_FLAGS, 3);
tu_cs_image_flag_ref(cs, iview, layer);
}
.color_format = format.fmt,
.color_swap = format.swap,
.srgb = vk_format_is_srgb(vk_format)),
- A6XX_RB_2D_DST_LO((uint32_t) va),
- A6XX_RB_2D_DST_HI(va >> 32),
+ A6XX_RB_2D_DST(.qword = va),
A6XX_RB_2D_DST_PITCH(pitch));
}
CP_LOAD_STATE6_0_NUM_UNIT(1));
tu_cs_emit_qw(cs, texture.iova + A6XX_TEX_CONST_DWORDS * 4);
- tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_TEX_SAMP_LO, 2);
- tu_cs_emit_qw(cs, texture.iova + A6XX_TEX_CONST_DWORDS * 4);
+ tu_cs_emit_regs(cs, A6XX_SP_FS_TEX_SAMP(.qword = texture.iova + A6XX_TEX_CONST_DWORDS * 4));
tu_cs_emit_pkt7(cs, CP_LOAD_STATE6_FRAG, 3);
tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
CP_LOAD_STATE6_0_NUM_UNIT(1));
tu_cs_emit_qw(cs, texture.iova);
- tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_TEX_CONST_LO, 2);
- tu_cs_emit_qw(cs, texture.iova);
-
+ tu_cs_emit_regs(cs, A6XX_SP_FS_TEX_CONST(.qword = texture.iova));
tu_cs_emit_regs(cs, A6XX_SP_FS_TEX_COUNT(1));
}
A6XX_RB_MRT_BUF_INFO(0, .color_format = format.fmt, .color_swap = format.swap),
A6XX_RB_MRT_PITCH(0, pitch),
A6XX_RB_MRT_ARRAY_PITCH(0, 0),
- A6XX_RB_MRT_BASE_LO(0, (uint32_t) va),
- A6XX_RB_MRT_BASE_HI(0, va >> 32),
+ A6XX_RB_MRT_BASE(0, .qword = va),
A6XX_RB_MRT_BASE_GMEM(0, 0));
tu_cs_emit_regs(cs, A6XX_RB_RENDER_CNTL());
tu_cs_emit(cs, iview->RB_BLIT_DST_INFO);
tu_cs_image_ref_2d(cs, iview, 0, false);
- tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
+ tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST, 3);
tu_cs_image_flag_ref(cs, iview, 0);
tu_cs_emit_regs(cs,
.unk22 = 1),
/* note: src size does not matter when not scaling */
A6XX_SP_PS_2D_SRC_SIZE( .width = 0x3fff, .height = 0x3fff),
- A6XX_SP_PS_2D_SRC_LO(cmd->device->physical_device->gmem_base + gmem_offset),
- A6XX_SP_PS_2D_SRC_HI(),
+ A6XX_SP_PS_2D_SRC(.qword = cmd->device->physical_device->gmem_base + gmem_offset),
A6XX_SP_PS_2D_SRC_PITCH(.pitch = cmd->state.framebuffer->tile0.width * cpp));
/* sync GMEM writes with CACHE. */
tu_cs_emit_regs(cs,
A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
- tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
+ tu_cs_emit_pkt4(cs, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE, 3);
tu_cs_image_flag_ref(cs, iview, 0);
tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_BUFFER_BASE(.bo = iview->image->bo,
.bo_offset = iview->image->bo_offset + iview->image->lrz_offset),
A6XX_GRAS_LRZ_BUFFER_PITCH(.pitch = iview->image->lrz_pitch),
- A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO(0),
- A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI(0));
+ A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE());
if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT ||
attachment->format == VK_FORMAT_S8_UINT) {
tu_cs_emit_regs(cs,
A6XX_SP_FS_MRT_REG(i, .dword = iview->SP_FS_MRT_REG));
- tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(i), 3);
+ tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(i), 3);
tu_cs_image_flag_ref(cs, iview, 0);
}
CP_LOAD_STATE6_0_NUM_UNIT(subpass->input_count * 2));
tu_cs_emit_qw(&cs, texture.iova);
- tu_cs_emit_pkt4(&cs, REG_A6XX_SP_FS_TEX_CONST_LO, 2);
- tu_cs_emit_qw(&cs, texture.iova);
+ tu_cs_emit_regs(&cs, A6XX_SP_FS_TEX_CONST(.qword = texture.iova));
tu_cs_emit_regs(&cs, A6XX_SP_FS_TEX_COUNT(subpass->input_count * 2));
for (uint32_t i = 0; i < MAX_VBS; i++) {
tu_cs_emit_regs(&cs,
- A6XX_VFD_FETCH_BASE_LO(i, cmd->state.vb[i].base),
- A6XX_VFD_FETCH_BASE_HI(i, cmd->state.vb[i].base >> 32),
+ A6XX_VFD_FETCH_BASE(i, .qword = cmd->state.vb[i].base),
A6XX_VFD_FETCH_SIZE(i, cmd->state.vb[i].size));
}
*/
tu_cs_emit_wfi(cs);
- tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESSFACTOR_ADDR_LO, 2);
- tu_cs_emit_qw(cs, tess_factor_iova);
+ tu_cs_emit_regs(cs, A6XX_PC_TESSFACTOR_ADDR(.qword = tess_factor_iova));
tu_cs_emit_pkt7(cs, CP_SET_SUBDRAW_SIZE, 1);
tu_cs_emit(cs, draw_count);
OUT_RING(ring, 0x00000000);
if (ubwc_enabled) {
- OUT_PKT4(ring, REG_A6XX_RB_2D_DST_FLAGS_LO, 6);
+ OUT_PKT4(ring, REG_A6XX_RB_2D_DST_FLAGS, 6);
fd6_emit_flag_reference(ring, dst, level, layer);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
if (subwc_enabled) {
- OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_FLAGS_LO, 6);
+ OUT_PKT4(ring, REG_A6XX_SP_PS_2D_SRC_FLAGS, 6);
fd6_emit_flag_reference(ring, src, info->src.level, layer);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
A6XX_HLSQ_CS_CNTL_1_THREADSIZE(THREAD128));
- OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START_LO, 2);
+ OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START, 2);
OUT_RELOC(ring, v->bo, 0, 0, 0); /* SP_CS_OBJ_START_LO/HI */
if (v->instrlen > 0)
setup_border_colors(&ctx->tex[PIPE_SHADER_FRAGMENT],
&entries[ctx->tex[PIPE_SHADER_VERTEX].num_samplers]);
- OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO, 2);
+ OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR, 2);
OUT_RELOC(ring, fd_resource(fd6_ctx->border_color_buf)->bo, off, 0, 0);
u_upload_unmap(fd6_ctx->border_color_uploader);
case PIPE_SHADER_VERTEX:
sb = SB6_VS_TEX;
opcode = CP_LOAD_STATE6_GEOM;
- tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP_LO;
- tex_const_reg = REG_A6XX_SP_VS_TEX_CONST_LO;
+ tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP;
+ tex_const_reg = REG_A6XX_SP_VS_TEX_CONST;
tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
break;
case PIPE_SHADER_TESS_CTRL:
sb = SB6_HS_TEX;
opcode = CP_LOAD_STATE6_GEOM;
- tex_samp_reg = REG_A6XX_SP_HS_TEX_SAMP_LO;
- tex_const_reg = REG_A6XX_SP_HS_TEX_CONST_LO;
+ tex_samp_reg = REG_A6XX_SP_HS_TEX_SAMP;
+ tex_const_reg = REG_A6XX_SP_HS_TEX_CONST;
tex_count_reg = REG_A6XX_SP_HS_TEX_COUNT;
break;
case PIPE_SHADER_TESS_EVAL:
sb = SB6_DS_TEX;
opcode = CP_LOAD_STATE6_GEOM;
- tex_samp_reg = REG_A6XX_SP_DS_TEX_SAMP_LO;
- tex_const_reg = REG_A6XX_SP_DS_TEX_CONST_LO;
+ tex_samp_reg = REG_A6XX_SP_DS_TEX_SAMP;
+ tex_const_reg = REG_A6XX_SP_DS_TEX_CONST;
tex_count_reg = REG_A6XX_SP_DS_TEX_COUNT;
break;
case PIPE_SHADER_GEOMETRY:
sb = SB6_GS_TEX;
opcode = CP_LOAD_STATE6_GEOM;
- tex_samp_reg = REG_A6XX_SP_GS_TEX_SAMP_LO;
- tex_const_reg = REG_A6XX_SP_GS_TEX_CONST_LO;
+ tex_samp_reg = REG_A6XX_SP_GS_TEX_SAMP;
+ tex_const_reg = REG_A6XX_SP_GS_TEX_CONST;
tex_count_reg = REG_A6XX_SP_GS_TEX_COUNT;
break;
case PIPE_SHADER_FRAGMENT:
sb = SB6_FS_TEX;
opcode = CP_LOAD_STATE6_FRAG;
- tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP_LO;
- tex_const_reg = REG_A6XX_SP_FS_TEX_CONST_LO;
+ tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP;
+ tex_const_reg = REG_A6XX_SP_FS_TEX_CONST;
tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
break;
case PIPE_SHADER_COMPUTE:
sb = SB6_CS_TEX;
opcode = CP_LOAD_STATE6_FRAG;
- tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP_LO;
- tex_const_reg = REG_A6XX_SP_CS_TEX_CONST_LO;
+ tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP;
+ tex_const_reg = REG_A6XX_SP_CS_TEX_CONST;
tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
break;
default:
target->stride = info->stride[i];
- OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE_LO(i), 3);
+ OUT_PKT4(ring, REG_A6XX_VPC_SO_BUFFER_BASE(i), 3);
/* VPC_SO[i].BUFFER_BASE_LO: */
OUT_RELOC(ring, fd_resource(target->base.buffer)->bo, 0, 0, 0);
OUT_RING(ring, target->base.buffer_size + target->base.buffer_offset);
}
// After a draw HW would write the new offset to offset_bo
- OUT_PKT4(ring, REG_A6XX_VPC_SO_FLUSH_BASE_LO(i), 2);
+ OUT_PKT4(ring, REG_A6XX_VPC_SO_FLUSH_BASE(i), 2);
OUT_RELOC(ring, offset_bo, 0, 0, 0);
so->reset &= ~(1 << i);
CP_LOAD_STATE6_0_NUM_UNIT(ir3_shader_nibo(fs)));
OUT_RB(obj, state);
- OUT_PKT4(obj, REG_A6XX_SP_IBO_LO, 2);
+ OUT_PKT4(obj, REG_A6XX_SP_IBO, 2);
OUT_RB(obj, state);
/* TODO if we used CP_SET_DRAW_STATE for compute shaders, we could
CP_LOAD_STATE6_0_NUM_UNIT(ir3_shader_nibo(cp)));
OUT_RB(ring, state);
- OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_LO, 2);
+ OUT_PKT4(ring, REG_A6XX_SP_CS_IBO, 2);
OUT_RB(ring, state);
OUT_PKT4(ring, REG_A6XX_SP_CS_IBO_COUNT, 1);
OUT_REG(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
- OUT_PKT4(ring, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
+ OUT_PKT4(ring, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE, 3);
fd6_emit_flag_reference(ring, rsc,
zsbuf->u.tex.level, zsbuf->u.tex.first_layer);
A6XX_GRAS_LRZ_BUFFER_BASE(.bo = rsc->lrz),
A6XX_GRAS_LRZ_BUFFER_PITCH(.pitch = rsc->lrz_pitch),
// XXX a6xx seems to use a different buffer here.. not sure what for..
- A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO(0),
- A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI(0));
+ A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE());
} else {
- OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
+ OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE, 5);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
OUT_REG(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
- OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
+ OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE, 5);
OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
OUT_REG(ring, A6XX_RB_BLIT_BASE_GMEM(.dword = base));
if (ubwc_enabled) {
- OUT_PKT4(ring, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
+ OUT_PKT4(ring, REG_A6XX_RB_BLIT_FLAG_DST, 3);
fd6_emit_flag_reference(ring, rsc,
psurf->u.tex.level, psurf->u.tex.first_layer);
}
batch->tessparam_size,
DRM_FREEDRENO_GEM_TYPE_KMEM, "tessparam");
- OUT_PKT4(ring, REG_A6XX_PC_TESSFACTOR_ADDR_LO, 2);
+ OUT_PKT4(ring, REG_A6XX_PC_TESSFACTOR_ADDR, 2);
OUT_RELOC(ring, batch->tessfactor_bo, 0, 0, 0);
batch->tess_addrs_constobj->cur = batch->tess_addrs_constobj->start;
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_CONTROL, 1);
OUT_RING(ring, A6XX_RB_SAMPLE_COUNT_CONTROL_COPY);
- OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO, 2);
+ OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_ADDR, 2);
OUT_RELOC(ring, query_sample(aq, start));
fd6_event_write(batch, ring, ZPASS_DONE, false);
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_CONTROL, 1);
OUT_RING(ring, A6XX_RB_SAMPLE_COUNT_CONTROL_COPY);
- OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_ADDR_LO, 2);
+ OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_ADDR, 2);
OUT_RELOC(ring, query_sample(aq, stop));
fd6_event_write(batch, ring, ZPASS_DONE, false);
struct fd_ringbuffer *ring = batch->draw;
fd_wfi(batch, ring);
- OUT_PKT4(ring, REG_A6XX_VPC_SO_STREAM_COUNTS_LO, 2);
+ OUT_PKT4(ring, REG_A6XX_VPC_SO_STREAM_COUNTS, 2);
primitives_relocw(ring, aq, start[0]);
fd6_event_write(batch, ring, WRITE_PRIMITIVE_COUNTS, false);
fd_wfi(batch, ring);
- OUT_PKT4(ring, REG_A6XX_VPC_SO_STREAM_COUNTS_LO, 2);
+ OUT_PKT4(ring, REG_A6XX_VPC_SO_STREAM_COUNTS, 2);
primitives_relocw(ring, aq, stop[0]);
fd6_event_write(batch, ring, WRITE_PRIMITIVE_COUNTS, false);
projects / platform / upstream / mesa.git / commitdiff