armv8: ls1046a: add PCIe dts node

Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index 359a9d13bf8e6397d462b84a40240204fbfb6271..aaf0ae90fdbb45da202d681bda80a3cae40614c2 100644 (file)
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -216,5 +216,54 @@
                        big-endian;
                        status = "disabled";
                };
+
+               pcie@3400000 {
+                       compatible = "fsl,ls-pcie", "snps,dw-pcie";
+                       reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
+                              0x00 0x03480000 0x0 0x40000   /* lut registers */
+                              0x00 0x034c0000 0x0 0x40000   /* pf controls registers */
+                              0x40 0x00000000 0x0 0x20000>; /* configuration space */
+                       reg-names = "dbi", "lut", "ctrl", "config";
+                       big-endian;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000   /* downstream I/O */
+                                 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+               };
+
+               pcie@3500000 {
+                       compatible = "fsl,ls-pcie", "snps,dw-pcie";
+                       reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
+                              0x00 0x03580000 0x0 0x40000   /* lut registers */
+                              0x00 0x035c0000 0x0 0x40000   /* pf controls registers */
+                              0x48 0x00000000 0x0 0x20000>; /* configuration space */
+                       reg-names = "dbi", "lut", "ctrl", "config";
+                       big-endian;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       num-lanes = <2>;
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000   /* downstream I/O */
+                                 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+               };
+
+               pcie@3600000 {
+                       compatible = "fsl,ls-pcie", "snps,dw-pcie";
+                       reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
+                              0x00 0x03680000 0x0 0x40000   /* lut registers */
+                              0x00 0x036c0000 0x0 0x40000   /* pf controls registers */
+                              0x50 0x00000000 0x0 0x20000>; /* configuration space */
+                       reg-names = "dbi", "lut", "ctrl", "config";
+                       big-endian;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       device_type = "pci";
+                       bus-range = <0x0 0xff>;
+                       ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000   /* downstream I/O */
+                                 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+               };
        };
 };