R600/SI: Create e64 versions of and/or/xor in SILowerI1Copies

This fixes moving boolean constants into registers before operating
on them. They get permuted and shrunk down to e32 anyway later. This
is a temporary fix until the patch that removes these pseudos is
committed.

llvm-svn: 222844

diff --git a/llvm/lib/Target/R600/SILowerI1Copies.cpp b/llvm/lib/Target/R600/SILowerI1Copies.cpp
index 65b892cf122d8cba0422d9163501eb5569272858..226a672b343ef7ed2c083a4683d202ef659816e2 100644 (file)
--- a/llvm/lib/Target/R600/SILowerI1Copies.cpp
+++ b/llvm/lib/Target/R600/SILowerI1Copies.cpp
@@ -93,19 +93,19 @@ bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) {
 
       if (MI.getOpcode() == AMDGPU::V_AND_I1) {
         I1Defs.push_back(MI.getOperand(0).getReg());
-        MI.setDesc(TII->get(AMDGPU::V_AND_B32_e32));
+        MI.setDesc(TII->get(AMDGPU::V_AND_B32_e64));
         continue;
       }
 
       if (MI.getOpcode() == AMDGPU::V_OR_I1) {
         I1Defs.push_back(MI.getOperand(0).getReg());
-        MI.setDesc(TII->get(AMDGPU::V_OR_B32_e32));
+        MI.setDesc(TII->get(AMDGPU::V_OR_B32_e64));
         continue;
       }
 
       if (MI.getOpcode() == AMDGPU::V_XOR_I1) {
         I1Defs.push_back(MI.getOperand(0).getReg());
-        MI.setDesc(TII->get(AMDGPU::V_XOR_B32_e32));
+        MI.setDesc(TII->get(AMDGPU::V_XOR_B32_e64));
         continue;
       }