KVM: x86/pmu: Avoid exposing Intel BTS feature

The BTS feature (including the ability to set the BTS and BTINT
bits in the DEBUGCTL MSR) is currently unsupported on KVM.

But we may try using the BTS facility on a PEBS enabled guest like this:
    perf record -e branches:u -c 1 -d ls
and then we would encounter the following call trace:

 [] unchecked MSR access error: WRMSR to 0x1d9 (tried to write 0x00000000000003c0)
        at rIP: 0xffffffff810745e4 (native_write_msr+0x4/0x20)
 [] Call Trace:
 []  intel_pmu_enable_bts+0x5d/0x70
 []  bts_event_add+0x54/0x70
 []  event_sched_in+0xee/0x290

As it lacks any CPUID indicator or perf_capabilities valid bit
fields to prompt for this information, the platform would hint
the Intel BTS feature unavailable to guest by setting the
BTS_UNAVAIL bit in the IA32_MISC_ENABLE.

Signed-off-by: Like Xu <likexu@tencent.com>
Message-Id: <20220601031925.59693-3-likexu@tencent.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h
index d59e1cb3b5dc32a65bcaaee40caaa8d8ddc314e9..2c5b3c9f55310b5aea94f6a290553cf776fecc00 100644 (file)
--- a/arch/x86/kvm/pmu.h
+++ b/arch/x86/kvm/pmu.h
@@ -8,6 +8,9 @@
 #define pmu_to_vcpu(pmu)  (container_of((pmu), struct kvm_vcpu, arch.pmu))
 #define pmc_to_pmu(pmc)   (&(pmc)->vcpu->arch.pmu)
 
+#define MSR_IA32_MISC_ENABLE_PMU_RO_MASK (MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |  \
+                                         MSR_IA32_MISC_ENABLE_BTS_UNAVAIL)
+
 /* retrieve the 4 bits for EN and PMI out of IA32_FIXED_CTR_CTRL */
 #define fixed_ctrl_field(ctrl_reg, idx) (((ctrl_reg) >> ((idx)*4)) & 0xf)
 

diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index 5b85320fc9f1fd128cfdc44853c9c810058fbc28..422f0a6562ac4e4259c423eb34c1084ba5511aa8 100644 (file)
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
@@ -536,6 +536,8 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
        pmu->pebs_enable_mask = ~0ull;
        pmu->pebs_data_cfg_mask = ~0ull;
 
+       vcpu->arch.ia32_misc_enable_msr |= MSR_IA32_MISC_ENABLE_PMU_RO_MASK;
+
        entry = kvm_find_cpuid_entry(vcpu, 0xa, 0);
        if (!entry || !vcpu->kvm->arch.enable_pmu)
                return;
@@ -623,7 +625,6 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
                                ~((1ull << pmu->nr_arch_gp_counters) - 1);
                }
        } else {
-               vcpu->arch.ia32_misc_enable_msr |= MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
                vcpu->arch.perf_capabilities &= ~PERF_CAP_PEBS_MASK;
        }
 }

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index a8014233fd57840f71ba967ea213f5f5ed16d5ad..79efdc19b4c83287524aba22a554a3d5da0e3106 100644 (file)
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -3548,12 +3548,12 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
                break;
        case MSR_IA32_MISC_ENABLE: {
                u64 old_val = vcpu->arch.ia32_misc_enable_msr;
-               u64 pmu_mask = MSR_IA32_MISC_ENABLE_EMON |
-                       MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL;
+               u64 pmu_mask = MSR_IA32_MISC_ENABLE_PMU_RO_MASK |
+                       MSR_IA32_MISC_ENABLE_EMON;
 
                /* RO bits */
                if (!msr_info->host_initiated &&
-                   ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL))
+                   ((old_val ^ data) & MSR_IA32_MISC_ENABLE_PMU_RO_MASK))
                        return 1;
 
                /*