setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
- if (Subtarget.is64Bit()) {
- if (!Subtarget.useSoftFloat() && Subtarget.hasAVX512()) {
- // FP_TO_UINT-i32/i64 is legal for f32/f64, but custom for f80.
- setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom);
- setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Custom);
- } else {
- setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
- setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand);
- }
- } else if (!Subtarget.useSoftFloat()) {
+ if (!Subtarget.useSoftFloat()) {
setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
}
bool UseSSEReg = isScalarFPTypeInSSEReg(SrcVT);
- if (!IsSigned && Subtarget.hasAVX512()) {
- // Conversions from f32/f64 should be legal.
- if (UseSSEReg)
+ if (!IsSigned && UseSSEReg) {
+ // Conversions from f32/f64 with AVX512 should be legal.
+ if (Subtarget.hasAVX512())
return Op;
- // Use default expansion.
+ // Use default expansion for i64.
if (VT == MVT::i64)
return SDValue();
+
+ assert(VT == MVT::i32 && "Unexpected VT!");
+
+ // Promote i32 to i64 and use a signed operation on 64-bit targets.
+ if (Subtarget.is64Bit()) {
+ SDValue Res = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i64, Src);
+ return DAG.getNode(ISD::TRUNCATE, dl, VT, Res);
+ }
+
+ // Use default expansion for SSE1/2 targets without SSE3. With SSE3 we can
+ // use fisttp which will be handled later.
+ if (!Subtarget.hasSSE3())
+ return SDValue();
}
// Promote i16 to i32 if we can use a SSE operation.
if (UseSSEReg && IsSigned)
return Op;
- // Use default expansion for SSE1/2 targets without SSE3. With SSE3 we can use
- // fisttp.
- if (!IsSigned && UseSSEReg && !Subtarget.hasSSE3())
- return SDValue();
-
// Fall back to X87.
if (SDValue V = FP_TO_INTHelper(Op, DAG, IsSigned))
return V;
{ ISD::UINT_TO_FP, MVT::v8f64, MVT::v8i64, 5 },
{ ISD::UINT_TO_FP, MVT::f64, MVT::i64, 1 },
+ { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 1 },
+ { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 1 },
{ ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 },
{ ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
{ ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 3 },
{ ISD::UINT_TO_FP, MVT::f64, MVT::i64, 6 },
+ { ISD::FP_TO_UINT, MVT::i64, MVT::f32, 4 },
+ { ISD::FP_TO_UINT, MVT::i64, MVT::f64, 4 },
{ ISD::ZERO_EXTEND, MVT::v4i16, MVT::v4i8, 1 },
{ ISD::SIGN_EXTEND, MVT::v4i16, MVT::v4i8, 6 },