#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_RCAR
+#define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000
+#define CONFIG_SYS_RCAR_I2C0_SPEED 400000
+#define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000
+#define CONFIG_SYS_RCAR_I2C1_SPEED 400000
+#define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000
+#define CONFIG_SYS_RCAR_I2C2_SPEED 400000
+#define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000
+#define CONFIG_SYS_RCAR_I2C3_SPEED 400000
+#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4
+
/* Board Clock */
#define CONFIG_BASE_CLK_FREQ 20000000u
#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */
#define CONFIG_PLL1_CLK_FREQ (CONFIG_BASE_CLK_FREQ * 156 / 2)
#define CONFIG_PLL1_DIV2_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 2)
#define CONFIG_MP_CLK_FREQ (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
+#define CONFIG_HP_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 12)
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_MP_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV 4