ARM: shmobile: r8a7791: Add EHCI MSTP clock
authorMagnus Damm <damm@opensource.se>
Mon, 7 Apr 2014 06:04:21 +0000 (15:04 +0900)
committerSimon Horman <horms@verge.net.au>
Fri, 5 Dec 2014 00:23:23 +0000 (09:23 +0900)
Add support for EHCI clock gating via the MSTP703 bit on r8a7791.

Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 6225b99aa620d6e260228a30cc5d24cde60cb1e7)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm/boot/dts/r8a7791.dtsi
include/dt-bindings/clock/r8a7791-clock.h

index aa1cba9..5234605 100644 (file)
                mstp7_clks: mstp7_clks@e615014c {
                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
-                       clocks = <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
+                       clocks = <&mp_clk>,  <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
                                 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
                                 <&zx_clk>, <&zx_clk>, <&zx_clk>;
                        #clock-cells = <1>;
                        renesas,clock-indices = <
-                               R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
+                               R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
                                R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
                                R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
                                R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
                                R8A7791_CLK_LVDS0
                        >;
                        clock-output-names =
-                               "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
+                               "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
                                "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
                };
                mstp8_clks: mstp8_clks@e6150990 {
index 729dc5f..29b0f33 100644 (file)
@@ -63,6 +63,7 @@
 #define R8A7791_CLK_PWM                        23
 
 /* MSTP7 */
+#define R8A7791_CLK_EHCI               3
 #define R8A7791_CLK_HSUSB              4
 #define R8A7791_CLK_HSCIF2             13
 #define R8A7791_CLK_SCIF5              14