REG64(SP_CS_TEX_SAMP, reg_dump_gpuaddr64),
{NULL},
+}, reg_a7xx[] = {
+ REG64(SP_VS_OBJ_START, reg_disasm_gpuaddr64),
+ REG64(SP_HS_OBJ_START, reg_disasm_gpuaddr64),
+ REG64(SP_DS_OBJ_START, reg_disasm_gpuaddr64),
+ REG64(SP_GS_OBJ_START, reg_disasm_gpuaddr64),
+ REG64(SP_FS_OBJ_START, reg_disasm_gpuaddr64),
+ REG64(SP_CS_OBJ_START, reg_disasm_gpuaddr64),
+
+ {NULL},
}, *type0_reg;
static struct rnn *rnn;
type0_reg = reg_a6xx;
init_rnn("a6xx");
break;
+ case 700 ... 799:
+ type0_reg = reg_a7xx;
+ init_rnn("a7xx");
+ break;
default:
- errx(-1, "unsupported gpu");
+ errx(-1, "unsupported gpu: %u", options->gpu_id);
}
}
static uint32_t bin_x1, bin_x2, bin_y1, bin_y2;
static unsigned mode;
static const char *render_mode;
+static const char *thread;
static enum {
MODE_BINNING = 0x1,
MODE_GMEM = 0x2,
print_mode(int level)
{
if ((options->gpu_id >= 500) && !quiet(2)) {
- printf("%smode: %s\n", levels[level], render_mode);
+ printf("%smode: %s", levels[level], render_mode);
+ if (thread)
+ printf(":%s", thread);
+ printf("\n");
printf("%sskip_ib2: g=%d, l=%d\n", levels[level], skip_ib2_enable_global,
skip_ib2_enable_local);
}
bin_y1, bin_x2, bin_y2, num_indices);
if (options->gpu_id >= 500)
printf("%s:", render_mode);
+ if (thread)
+ printf("%s:", thread);
printf("\t%08"PRIx64, r.value);
if (r.value != lastvals[regbase]) {
printf("!");
dump_domain(texsamp, 4, level + 2, "A5XX_TEX_SAMP");
dump_hex(texsamp, 4, level + 1);
texsamp += 4;
- } else if ((600 <= options->gpu_id) && (options->gpu_id < 700)) {
+ } else if ((600 <= options->gpu_id) && (options->gpu_id < 800)) {
dump_domain(texsamp, 4, level + 2, "A6XX_TEX_SAMP");
dump_hex(texsamp, 4, level + 1);
texsamp += src == STATE_SRC_BINDLESS ? 16 : 4;
}
dump_hex(texconst, 12, level + 1);
texconst += 12;
- } else if ((600 <= options->gpu_id) && (options->gpu_id < 700)) {
+ } else if ((600 <= options->gpu_id) && (options->gpu_id < 800)) {
dump_domain(texconst, 16, level + 2, "A6XX_TEX_CONST");
if (options->dump_textures) {
uint64_t addr =
dump_domain(ssboconst, 4, level + 2, "A4XX_SSBO_0");
} else if (500 <= options->gpu_id && options->gpu_id < 600) {
dump_domain(ssboconst, 4, level + 2, "A5XX_SSBO_0");
- } else if (600 <= options->gpu_id && options->gpu_id < 700) {
+ } else if (600 <= options->gpu_id && options->gpu_id < 800) {
sz = 16;
dump_domain(ssboconst, 16, level + 2, "A6XX_TEX_CONST");
}
for (uint32_t i = 0; i < loopcount; i++) {
ibs[ib].base = ibaddr;
ibs[ib].size = ibsize;
- printf("%sbin %u\n", levels[level], i);
+ printl(3, "%sbin %u\n", levels[level], i);
dump_commands(ptr, ibsize, level);
ibaddr += ibsize;
ptr += ibsize;
static void
cp_set_marker(uint32_t *dwords, uint32_t sizedwords, int level)
{
- render_mode = rnn_enumname(rnn, "a6xx_marker", dwords[0] & 0xf);
+ uint32_t val = dwords[0] & 0xf;
+ const char *mode = rnn_enumname(rnn, "a6xx_marker", val);
+
+ if (!mode) {
+ static char buf[8];
+ sprintf(buf, "0x%x", val);
+ render_mode = buf;
+ return;
+ }
+
+ render_mode = mode;
if (!strcmp(render_mode, "RM6_BINNING")) {
enable_mask = MODE_BINNING;
}
static void
+cp_set_thread_control(uint32_t *dwords, uint32_t sizedwords, int level)
+{
+ uint32_t val = dwords[0] & 0x3;
+ thread = rnn_enumname(rnn, "cp_thread", val);
+}
+
+static void
cp_set_render_mode(uint32_t *dwords, uint32_t sizedwords, int level)
{
uint64_t addr;
summary = saved_summary;
}
+/* Looks similar to CP_CONTEXT_REG_BUNCH, but not quite the same...
+ * discarding first two dwords??
+ *
+ * CP_CONTEXT_REG_BUNCH:
+ * 0221: 9c1ff606 (rep)(xmov3)mov $usraddr, $data
+ * ; mov $data, $data
+ * ; mov $usraddr, $data
+ * ; mov $data, $data
+ * 0222: d8000000 waitin
+ * 0223: 981f0806 mov $01, $data
+ *
+ * CP_UNK5D:
+ * 0224: 981f0006 mov $00, $data
+ * 0225: 981f0006 mov $00, $data
+ * 0226: 9c1ff206 (rep)(xmov1)mov $usraddr, $data
+ * ; mov $data, $data
+ * 0227: d8000000 waitin
+ * 0228: 981f0806 mov $01, $data
+ *
+ */
+static void
+cp_context_reg_bunch2(uint32_t *dwords, uint32_t sizedwords, int level)
+{
+ dwords += 2;
+ sizedwords -= 2;
+ cp_context_reg_bunch(dwords, sizedwords, level);
+}
+
static void
cp_reg_write(uint32_t *dwords, uint32_t sizedwords, int level)
{
CP(SET_CTXSWITCH_IB, cp_set_ctxswitch_ib),
CP(START_BIN, cp_start_bin),
+
+ /* for a7xx */
+ CP(THREAD_CONTROL, cp_set_thread_control),
+ CP(CONTEXT_REG_BUNCH2, cp_context_reg_bunch2),
};
static void
}
static void
-init(struct rnn *rnn, char *file, char *domain)
+init(struct rnn *rnn, char *file, char *domain, char *variant)
{
/* prepare rnn stuff for lookup */
rnn_parsefile(rnn->db, file);
if (!rnn->dom[0] && rnn->dom[1]) {
fprintf(stderr, "Could not find domain %s in %s\n", domain, file);
}
- rnn->variant = domain;
+ rnn->variant = variant;
- rnndec_varadd(rnn->vc, "chip", domain);
+ rnndec_varadd(rnn->vc, "chip", variant);
if (rnn->vc != rnn->vc_nocolor)
- rnndec_varadd(rnn->vc_nocolor, "chip", domain);
+ rnndec_varadd(rnn->vc_nocolor, "chip", variant);
if (rnn->db->estatus)
errx(rnn->db->estatus, "failed to parse register database");
}
void
rnn_load_file(struct rnn *rnn, char *file, char *domain)
{
- init(rnn, file, domain);
+ init(rnn, file, domain, domain);
}
void
rnn_load(struct rnn *rnn, const char *gpuname)
{
if (strstr(gpuname, "a2")) {
- init(rnn, "adreno/a2xx.xml", "A2XX");
+ init(rnn, "adreno/a2xx.xml", "A2XX", "A2XX");
} else if (strstr(gpuname, "a3")) {
- init(rnn, "adreno/a3xx.xml", "A3XX");
+ init(rnn, "adreno/a3xx.xml", "A3XX", "A3XX");
} else if (strstr(gpuname, "a4")) {
- init(rnn, "adreno/a4xx.xml", "A4XX");
+ init(rnn, "adreno/a4xx.xml", "A4XX", "A4XX");
} else if (strstr(gpuname, "a5")) {
- init(rnn, "adreno/a5xx.xml", "A5XX");
+ init(rnn, "adreno/a5xx.xml", "A5XX", "A5XX");
} else if (strstr(gpuname, "a6")) {
- init(rnn, "adreno/a6xx.xml", "A6XX");
+ init(rnn, "adreno/a6xx.xml", "A6XX", "A6XX");
+ } else if (strstr(gpuname, "a7")) {
+ init(rnn, "adreno/a6xx.xml", "A6XX", "A7XX");
}
}