arm64: dts: qcom: sc7280: fix codec reset line polarity for CRD 1.0/2.0

The driver for the codec, when resetting the chip, first drives the line
low, and then high. This means that the line is active low. Change the
annotation in the DTS accordingly.

Fixes: f8b4eb64f200 ("arm64: dts: qcom: sc7280: Add wcd9385 codec node for CRD 1.0/2.0 and IDP boards")
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221027074652.1044235-5-dmitry.torokhov@gmail.com

diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 4884647..1ac7c09 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -34,7 +34,7 @@
                pinctrl-0 = <&wcd_reset_n>;
                pinctrl-1 = <&wcd_reset_n_sleep>;
 
-               reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>;
+               reset-gpios = <&tlmm 83 GPIO_ACTIVE_LOW>;
 
                qcom,rx-device = <&wcd_rx>;
                qcom,tx-device = <&wcd_tx>;