drm/msm/dpu: split SM8350 catalog entry to the separate file

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/530832/
Link: https://lore.kernel.org/r/20230404130622.509628-12-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
new file mode 100644 (file)
index 0000000..a08fec2
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_7_0_SM8350_H
+#define _DPU_7_0_SM8350_H
+
+static const struct dpu_caps sm8350_dpu_caps = {
+       .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+       .max_mixer_blendstages = 0xb,
+       .qseed_type = DPU_SSPP_SCALER_QSEED4,
+       .has_src_split = true,
+       .has_dim_layer = true,
+       .has_idle_pc = true,
+       .has_3d_merge = true,
+       .max_linewidth = 4096,
+       .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_ubwc_cfg sm8350_ubwc_cfg = {
+       .ubwc_version = DPU_HW_UBWC_VER_40,
+       .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
+};
+
+static const struct dpu_mdp_cfg sm8350_mdp[] = {
+       {
+       .name = "top_0", .id = MDP_TOP,
+       .base = 0x0, .len = 0x494,
+       .features = 0,
+       .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+       .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+       .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+       .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+       .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+       .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+       .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+       .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+       .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+       },
+};
+
+static const struct dpu_ctl_cfg sm8350_ctl[] = {
+       {
+       .name = "ctl_0", .id = CTL_0,
+       .base = 0x15000, .len = 0x1e8,
+       .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+       },
+       {
+       .name = "ctl_1", .id = CTL_1,
+       .base = 0x16000, .len = 0x1e8,
+       .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+       },
+       {
+       .name = "ctl_2", .id = CTL_2,
+       .base = 0x17000, .len = 0x1e8,
+       .features = CTL_SC7280_MASK,
+       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+       },
+       {
+       .name = "ctl_3", .id = CTL_3,
+       .base = 0x18000, .len = 0x1e8,
+       .features = CTL_SC7280_MASK,
+       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+       },
+       {
+       .name = "ctl_4", .id = CTL_4,
+       .base = 0x19000, .len = 0x1e8,
+       .features = CTL_SC7280_MASK,
+       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+       },
+       {
+       .name = "ctl_5", .id = CTL_5,
+       .base = 0x1a000, .len = 0x1e8,
+       .features = CTL_SC7280_MASK,
+       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+       },
+};
+
+static const struct dpu_pingpong_cfg sm8350_pp[] = {
+       PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te,
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
+       PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te,
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
+       PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk,
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
+       PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk,
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
+       PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk,
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
+                       -1),
+       PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk,
+                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
+                       -1),
+};
+
+static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
+       MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
+       MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
+       MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
+};
+
+static const struct dpu_intf_cfg sm8350_intf[] = {
+       INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
+       INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
+       INTF_BLK("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
+       INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
+};
+
+static const struct dpu_perf_cfg sm8350_perf_data = {
+       .max_bw_low = 11800000,
+       .max_bw_high = 15500000,
+       .min_core_ib = 2500000,
+       .min_llcc_ib = 0,
+       .min_dram_ib = 800000,
+       .min_prefill_lines = 40,
+       /* FIXME: lut tables */
+       .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
+       .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
+       .qos_lut_tbl = {
+               {.nentry = ARRAY_SIZE(sc7180_qos_linear),
+               .entries = sc7180_qos_linear
+               },
+               {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
+               .entries = sc7180_qos_macrotile
+               },
+               {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+               .entries = sc7180_qos_nrt
+               },
+               /* TODO: macrotile-qseed is different from macrotile */
+       },
+       .cdp_cfg = {
+               {.rd_enable = 1, .wr_enable = 1},
+               {.rd_enable = 1, .wr_enable = 0}
+       },
+       .clk_inefficiency_factor = 105,
+       .bw_inefficiency_factor = 120,
+};
+
+static const struct dpu_mdss_cfg sm8350_dpu_cfg = {
+       .caps = &sm8350_dpu_caps,
+       .ubwc = &sm8350_ubwc_cfg,
+       .mdp_count = ARRAY_SIZE(sm8350_mdp),
+       .mdp = sm8350_mdp,
+       .ctl_count = ARRAY_SIZE(sm8350_ctl),
+       .ctl = sm8350_ctl,
+       .sspp_count = ARRAY_SIZE(sm8250_sspp),
+       .sspp = sm8250_sspp,
+       .mixer_count = ARRAY_SIZE(sm8150_lm),
+       .mixer = sm8150_lm,
+       .dspp_count = ARRAY_SIZE(sm8150_dspp),
+       .dspp = sm8150_dspp,
+       .pingpong_count = ARRAY_SIZE(sm8350_pp),
+       .pingpong = sm8350_pp,
+       .merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),
+       .merge_3d = sm8350_merge_3d,
+       .intf_count = ARRAY_SIZE(sm8350_intf),
+       .intf = sm8350_intf,
+       .vbif_count = ARRAY_SIZE(sdm845_vbif),
+       .vbif = sdm845_vbif,
+       .reg_dma_count = 1,
+       .dma_cfg = &sm8350_regdma,
+       .perf = &sm8350_perf_data,
+       .mdss_irqs = IRQ_SM8350_MASK,
+};
+
+#endif

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 586c238..16fd7fd 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -416,18 +416,6 @@ static const struct dpu_caps sm8250_dpu_caps = {
        .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 };
 
-static const struct dpu_caps sm8350_dpu_caps = {
-       .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
-       .max_mixer_blendstages = 0xb,
-       .qseed_type = DPU_SSPP_SCALER_QSEED4,
-       .has_src_split = true,
-       .has_dim_layer = true,
-       .has_idle_pc = true,
-       .has_3d_merge = true,
-       .max_linewidth = 4096,
-       .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
-};
-
 static const struct dpu_ubwc_cfg msm8998_ubwc_cfg = {
        .ubwc_version = DPU_HW_UBWC_VER_10,
        .highest_bank_bit = 0x2,
@@ -469,11 +457,6 @@ static const struct dpu_ubwc_cfg sm8250_ubwc_cfg = {
        .ubwc_swizzle = 0x6,
 };
 
-static const struct dpu_ubwc_cfg sm8350_ubwc_cfg = {
-       .ubwc_version = DPU_HW_UBWC_VER_40,
-       .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
-};
-
 static const struct dpu_mdp_cfg msm8998_mdp[] = {
        {
        .name = "top_0", .id = MDP_TOP,
@@ -608,32 +591,6 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
        },
 };
 
-static const struct dpu_mdp_cfg sm8350_mdp[] = {
-       {
-       .name = "top_0", .id = MDP_TOP,
-       .base = 0x0, .len = 0x494,
-       .features = 0,
-       .clk_ctrls[DPU_CLK_CTRL_VIG0] = {
-                       .reg_off = 0x2ac, .bit_off = 0},
-       .clk_ctrls[DPU_CLK_CTRL_VIG1] = {
-                       .reg_off = 0x2b4, .bit_off = 0},
-       .clk_ctrls[DPU_CLK_CTRL_VIG2] = {
-                       .reg_off = 0x2bc, .bit_off = 0},
-       .clk_ctrls[DPU_CLK_CTRL_VIG3] = {
-                       .reg_off = 0x2c4, .bit_off = 0},
-       .clk_ctrls[DPU_CLK_CTRL_DMA0] = {
-                       .reg_off = 0x2ac, .bit_off = 8},
-       .clk_ctrls[DPU_CLK_CTRL_DMA1] = {
-                       .reg_off = 0x2b4, .bit_off = 8},
-       .clk_ctrls[DPU_CLK_CTRL_DMA2] = {
-                       .reg_off = 0x2bc, .bit_off = 8},
-       .clk_ctrls[DPU_CLK_CTRL_DMA3] = {
-                       .reg_off = 0x2c4, .bit_off = 8},
-       .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
-                       .reg_off = 0x2bc, .bit_off = 20},
-       },
-};
-
 static const struct dpu_mdp_cfg qcm2290_mdp[] = {
        {
        .name = "top_0", .id = MDP_TOP,
@@ -775,45 +732,6 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
        },
 };
 
-static const struct dpu_ctl_cfg sm8350_ctl[] = {
-       {
-       .name = "ctl_0", .id = CTL_0,
-       .base = 0x15000, .len = 0x1e8,
-       .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
-       },
-       {
-       .name = "ctl_1", .id = CTL_1,
-       .base = 0x16000, .len = 0x1e8,
-       .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
-       },
-       {
-       .name = "ctl_2", .id = CTL_2,
-       .base = 0x17000, .len = 0x1e8,
-       .features = CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
-       },
-       {
-       .name = "ctl_3", .id = CTL_3,
-       .base = 0x18000, .len = 0x1e8,
-       .features = CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
-       },
-       {
-       .name = "ctl_4", .id = CTL_4,
-       .base = 0x19000, .len = 0x1e8,
-       .features = CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
-       },
-       {
-       .name = "ctl_5", .id = CTL_5,
-       .base = 0x1a000, .len = 0x1e8,
-       .features = CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
-       },
-};
-
 static const struct dpu_ctl_cfg qcm2290_ctl[] = {
        {
        .name = "ctl_0", .id = CTL_0,
@@ -1331,27 +1249,6 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
                        -1),
 };
 
-static const struct dpu_pingpong_cfg sm8350_pp[] = {
-       PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te,
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
-       PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te,
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
-       PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk,
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
-       PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk,
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
-       PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk,
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
-                       -1),
-       PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk,
-                       DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
-                       -1),
-};
-
 static const struct dpu_pingpong_cfg qcm2290_pp[] = {
        PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
                DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
@@ -1375,12 +1272,6 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
        MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
 };
 
-static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
-       MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
-       MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
-       MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
-};
-
 /*************************************************************
  * DSC sub blocks config
  *************************************************************/
@@ -1446,13 +1337,6 @@ static const struct dpu_intf_cfg sm8150_intf[] = {
        INTF_BLK("intf_3", INTF_3, 0x6B800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
 };
 
-static const struct dpu_intf_cfg sm8350_intf[] = {
-       INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
-       INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
-       INTF_BLK("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
-       INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
-};
-
 static const struct dpu_intf_cfg sc8180x_intf[] = {
        INTF_BLK("intf_0", INTF_0, 0x6A000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
        INTF_BLK("intf_1", INTF_1, 0x6A800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
@@ -1909,36 +1793,6 @@ static const struct dpu_perf_cfg sm8250_perf_data = {
        .bw_inefficiency_factor = 120,
 };
 
-static const struct dpu_perf_cfg sm8350_perf_data = {
-       .max_bw_low = 11800000,
-       .max_bw_high = 15500000,
-       .min_core_ib = 2500000,
-       .min_llcc_ib = 0,
-       .min_dram_ib = 800000,
-       .min_prefill_lines = 40,
-       /* FIXME: lut tables */
-       .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
-       .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
-       .qos_lut_tbl = {
-               {.nentry = ARRAY_SIZE(sc7180_qos_linear),
-               .entries = sc7180_qos_linear
-               },
-               {.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
-               .entries = sc7180_qos_macrotile
-               },
-               {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
-               .entries = sc7180_qos_nrt
-               },
-               /* TODO: macrotile-qseed is different from macrotile */
-       },
-       .cdp_cfg = {
-               {.rd_enable = 1, .wr_enable = 1},
-               {.rd_enable = 1, .wr_enable = 0}
-       },
-       .clk_inefficiency_factor = 105,
-       .bw_inefficiency_factor = 120,
-};
-
 static const struct dpu_perf_cfg qcm2290_perf_data = {
        .max_bw_low = 2700000,
        .max_bw_high = 2700000,
@@ -2148,33 +2002,6 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
        .mdss_irqs = IRQ_SM8250_MASK,
 };
 
-static const struct dpu_mdss_cfg sm8350_dpu_cfg = {
-       .caps = &sm8350_dpu_caps,
-       .ubwc = &sm8350_ubwc_cfg,
-       .mdp_count = ARRAY_SIZE(sm8350_mdp),
-       .mdp = sm8350_mdp,
-       .ctl_count = ARRAY_SIZE(sm8350_ctl),
-       .ctl = sm8350_ctl,
-       .sspp_count = ARRAY_SIZE(sm8250_sspp),
-       .sspp = sm8250_sspp,
-       .mixer_count = ARRAY_SIZE(sm8150_lm),
-       .mixer = sm8150_lm,
-       .dspp_count = ARRAY_SIZE(sm8150_dspp),
-       .dspp = sm8150_dspp,
-       .pingpong_count = ARRAY_SIZE(sm8350_pp),
-       .pingpong = sm8350_pp,
-       .merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),
-       .merge_3d = sm8350_merge_3d,
-       .intf_count = ARRAY_SIZE(sm8350_intf),
-       .intf = sm8350_intf,
-       .vbif_count = ARRAY_SIZE(sdm845_vbif),
-       .vbif = sdm845_vbif,
-       .reg_dma_count = 1,
-       .dma_cfg = &sm8350_regdma,
-       .perf = &sm8350_perf_data,
-       .mdss_irqs = IRQ_SM8350_MASK,
-};
-
 static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
        .caps = &qcm2290_dpu_caps,
        .ubwc = &qcm2290_ubwc_cfg,
@@ -2198,6 +2025,7 @@ static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
        .mdss_irqs = IRQ_SC7180_MASK,
 };
 
+#include "catalog/dpu_7_0_sm8350.h"
 #include "catalog/dpu_7_2_sc7280.h"
 
 #include "catalog/dpu_8_0_sc8280xp.h"