drm/amd/display; Fix kernel doc warnings
authorHarry Wentland <harry.wentland@amd.com>
Wed, 18 Sep 2019 15:42:59 +0000 (11:42 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 3 Oct 2019 14:11:00 +0000 (09:11 -0500)
We had a couple of missing definitions and formatting errors.

v2: Fix 'notifying' type

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

index 088d19d..b18deb2 100644 (file)
@@ -267,6 +267,13 @@ static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
               dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
 }
 
+/**
+ * dm_pflip_high_irq() - Handle pageflip interrupt
+ * @interrupt_params: ignored
+ *
+ * Handles the pageflip interrupt by notifying all interested parties
+ * that the pageflip has been completed.
+ */
 static void dm_pflip_high_irq(void *interrupt_params)
 {
        struct amdgpu_crtc *amdgpu_crtc;
@@ -411,6 +418,13 @@ static void dm_vupdate_high_irq(void *interrupt_params)
        }
 }
 
+/**
+ * dm_crtc_high_irq() - Handles CRTC interrupt
+ * @interrupt_params: ignored
+ *
+ * Handles the CRTC/VSYNC interrupt by notfying DRM's VBLANK
+ * event handler.
+ */
 static void dm_crtc_high_irq(void *interrupt_params)
 {
        struct common_irq_params *irq_params = interrupt_params;
index b6620f1..77c5166 100644 (file)
@@ -108,6 +108,12 @@ struct amdgpu_dm_backlight_caps {
  * @display_indexes_num: Max number of display streams supported
  * @irq_handler_list_table_lock: Synchronizes access to IRQ tables
  * @backlight_dev: Backlight control device
+ * @backlight_link: Link on which to control backlight
+ * @backlight_caps: Capabilities of the backlight device
+ * @freesync_module: Module handling freesync calculations
+ * @fw_dmcu: Reference to DMCU firmware
+ * @dmcu_fw_version: Version of the DMCU firmware
+ * @soc_bounding_box: SOC bounding box values provided by gpu_info FW
  * @cached_state: Caches device atomic state for suspend/resume
  * @compressor: Frame buffer compression buffer. See &struct dm_comressor_info
  */
@@ -128,7 +134,7 @@ struct amdgpu_display_manager {
        u16 display_indexes_num;
 
        /**
-        * @atomic_obj
+        * @atomic_obj:
         *
         * In combination with &dm_atomic_state it helps manage
         * global atomic state that doesn't map cleanly into existing
@@ -237,6 +243,8 @@ struct amdgpu_display_manager {
        uint32_t dmcu_fw_version;
 #ifdef CONFIG_DRM_AMD_DC_DCN2_0
        /**
+        * @soc_bounding_box:
+        *
         * gpu_info FW provided soc bounding box struct or 0 if not
         * available in FW
         */