[RISCV] Add explicit i64 to isel patterns to reduce RISCVGenDAGISel.inc size.

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index ec06a132c1f4d6d1df03626cac4aa416f1a4ff58..6ce39999b1a08605f87a36c67642b1c48f5f5e05 100644 (file)
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1179,8 +1179,8 @@ def : InstAlias<".insn_s $opcode, $funct3, $rs2, ${imm12}(${rs1})",
 
 class PatGpr<SDPatternOperator OpNode, RVInst Inst>
     : Pat<(OpNode GPR:$rs1), (Inst GPR:$rs1)>;
-class PatGprGpr<SDPatternOperator OpNode, RVInst Inst>
-    : Pat<(OpNode GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>;
+class PatGprGpr<SDPatternOperator OpNode, RVInst Inst, ValueType vt = XLenVT>
+    : Pat<(vt (OpNode GPR:$rs1, GPR:$rs2)), (Inst GPR:$rs1, GPR:$rs2)>;
 
 class PatGprImm<SDPatternOperator OpNode, RVInst Inst, ImmLeaf ImmType>
     : Pat<(XLenVT (OpNode (XLenVT GPR:$rs1), ImmType:$imm)),

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
index 5227acc1e504d45417217fc0edf08780584df470..2ec7aa5e87eb4d404142115518de2264e98ce3a5 100644 (file)
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td
@@ -127,17 +127,17 @@ let Predicates = [HasStdExtA] in {
 
 /// AMOs
 
-multiclass AMOPat<string AtomicOp, string BaseInst> {
+multiclass AMOPat<string AtomicOp, string BaseInst, ValueType vt = XLenVT> {
   def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_monotonic"),
-                  !cast<RVInst>(BaseInst)>;
+                  !cast<RVInst>(BaseInst), vt>;
   def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_acquire"),
-                  !cast<RVInst>(BaseInst#"_AQ")>;
+                  !cast<RVInst>(BaseInst#"_AQ"), vt>;
   def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_release"),
-                  !cast<RVInst>(BaseInst#"_RL")>;
+                  !cast<RVInst>(BaseInst#"_RL"), vt>;
   def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_acq_rel"),
-                  !cast<RVInst>(BaseInst#"_AQ_RL")>;
+                  !cast<RVInst>(BaseInst#"_AQ_RL"), vt>;
   def : PatGprGpr<!cast<PatFrag>(AtomicOp#"_seq_cst"),
-                  !cast<RVInst>(BaseInst#"_AQ_RL")>;
+                  !cast<RVInst>(BaseInst#"_AQ_RL"), vt>;
 }
 
 defm : AMOPat<"atomic_swap_32", "AMOSWAP_W">;
@@ -273,16 +273,17 @@ class PseudoCmpXchg
 
 // Ordering constants must be kept in sync with the AtomicOrdering enum in
 // AtomicOrdering.h.
-multiclass PseudoCmpXchgPat<string Op, Pseudo CmpXchgInst> {
-  def : Pat<(!cast<PatFrag>(Op#"_monotonic") GPR:$addr, GPR:$cmp, GPR:$new),
+multiclass PseudoCmpXchgPat<string Op, Pseudo CmpXchgInst,
+                            ValueType vt = XLenVT> {
+  def : Pat<(vt (!cast<PatFrag>(Op#"_monotonic") GPR:$addr, GPR:$cmp, GPR:$new)),
             (CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 2)>;
-  def : Pat<(!cast<PatFrag>(Op#"_acquire") GPR:$addr, GPR:$cmp, GPR:$new),
+  def : Pat<(vt (!cast<PatFrag>(Op#"_acquire") GPR:$addr, GPR:$cmp, GPR:$new)),
             (CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 4)>;
-  def : Pat<(!cast<PatFrag>(Op#"_release") GPR:$addr, GPR:$cmp, GPR:$new),
+  def : Pat<(vt (!cast<PatFrag>(Op#"_release") GPR:$addr, GPR:$cmp, GPR:$new)),
             (CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 5)>;
-  def : Pat<(!cast<PatFrag>(Op#"_acq_rel") GPR:$addr, GPR:$cmp, GPR:$new),
+  def : Pat<(vt (!cast<PatFrag>(Op#"_acq_rel") GPR:$addr, GPR:$cmp, GPR:$new)),
             (CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 6)>;
-  def : Pat<(!cast<PatFrag>(Op#"_seq_cst") GPR:$addr, GPR:$cmp, GPR:$new),
+  def : Pat<(vt (!cast<PatFrag>(Op#"_seq_cst") GPR:$addr, GPR:$cmp, GPR:$new)),
             (CmpXchgInst GPR:$addr, GPR:$cmp, GPR:$new, 7)>;
 }
 
@@ -309,15 +310,15 @@ def : Pat<(int_riscv_masked_cmpxchg_i32
 
 let Predicates = [HasStdExtA, IsRV64] in {
 
-defm : AMOPat<"atomic_swap_64", "AMOSWAP_D">;
-defm : AMOPat<"atomic_load_add_64", "AMOADD_D">;
-defm : AMOPat<"atomic_load_and_64", "AMOAND_D">;
-defm : AMOPat<"atomic_load_or_64", "AMOOR_D">;
-defm : AMOPat<"atomic_load_xor_64", "AMOXOR_D">;
-defm : AMOPat<"atomic_load_max_64", "AMOMAX_D">;
-defm : AMOPat<"atomic_load_min_64", "AMOMIN_D">;
-defm : AMOPat<"atomic_load_umax_64", "AMOMAXU_D">;
-defm : AMOPat<"atomic_load_umin_64", "AMOMINU_D">;
+defm : AMOPat<"atomic_swap_64", "AMOSWAP_D", i64>;
+defm : AMOPat<"atomic_load_add_64", "AMOADD_D", i64>;
+defm : AMOPat<"atomic_load_and_64", "AMOAND_D", i64>;
+defm : AMOPat<"atomic_load_or_64", "AMOOR_D", i64>;
+defm : AMOPat<"atomic_load_xor_64", "AMOXOR_D", i64>;
+defm : AMOPat<"atomic_load_max_64", "AMOMAX_D", i64>;
+defm : AMOPat<"atomic_load_min_64", "AMOMIN_D", i64>;
+defm : AMOPat<"atomic_load_umax_64", "AMOMAXU_D", i64>;
+defm : AMOPat<"atomic_load_umin_64", "AMOMINU_D", i64>;
 
 /// 64-bit AMOs
 
@@ -369,7 +370,7 @@ def : PseudoMaskedAMOPat<int_riscv_masked_atomicrmw_umin_i64,
 /// 64-bit compare and exchange
 
 def PseudoCmpXchg64 : PseudoCmpXchg;
-defm : PseudoCmpXchgPat<"atomic_cmp_swap_64", PseudoCmpXchg64>;
+defm : PseudoCmpXchgPat<"atomic_cmp_swap_64", PseudoCmpXchg64, i64>;
 
 def : Pat<(int_riscv_masked_cmpxchg_i64
             GPR:$addr, GPR:$cmpval, GPR:$newval, GPR:$mask, timm:$ordering),