(match_operand:QHI 2 "register_operand" "r")))]
"ok_for_simple_arith_logic_operands (operands, <MODE>mode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 0)
(plus:QHI (match_dup 1) (match_dup 2)))
(clobber (reg:CC R_FLAGS))])]
(match_operand:SI 2 "add_operand" " L,r,J")))]
"ok_for_simple_arith_logic_operands (operands, SImode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 0)
(plus:SI (match_dup 1) (match_dup 2)))
(clobber (reg:CC R_FLAGS))])]
(match_operand:DI 2 "add_operand" " L,J, r")))]
"ok_for_simple_arith_logic_operands (operands, DImode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(const_int 0)]
{
visium_split_double_add (PLUS, operands[0], operands[1], operands[2]);
(match_operand:QHI 2 "register_operand" "r")))]
"ok_for_simple_arith_logic_operands (operands, <MODE>mode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 0)
(minus:QHI (match_dup 1) (match_dup 2)))
(clobber (reg:CC R_FLAGS))])]
(match_operand:SI 2 "add_operand" " L,r, J")))]
"ok_for_simple_arith_logic_operands (operands, SImode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 0)
(minus:SI (match_dup 1) (match_dup 2)))
(clobber (reg:CC R_FLAGS))])]
(match_operand:DI 2 "add_operand" " L,J, r")))]
"ok_for_simple_arith_logic_operands (operands, DImode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(const_int 0)]
{
visium_split_double_add (MINUS, operands[0], operands[1], operands[2]);
(neg:I (match_operand:I 1 "register_operand" "r")))]
"ok_for_simple_arith_logic_operands (operands, <MODE>mode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 0) (neg:I (match_dup 1)))
(clobber (reg:CC R_FLAGS))])]
""
(neg:DI (match_operand:DI 1 "register_operand" "r")))]
"ok_for_simple_arith_logic_operands (operands, DImode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(const_int 0)]
{
visium_split_double_add (MINUS, operands[0], const0_rtx, operands[1]);
(match_operand:I 2 "register_operand" "r")))]
"ok_for_simple_arith_logic_operands (operands, <MODE>mode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 0)
(and:I (match_dup 1) (match_dup 2)))
(clobber (reg:CC R_FLAGS))])]
(match_operand:I 2 "register_operand" "r")))]
"ok_for_simple_arith_logic_operands (operands, <MODE>mode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 0)
(ior:I (match_dup 1) (match_dup 2)))
(clobber (reg:CC R_FLAGS))])]
(match_operand:I 2 "register_operand" "r")))]
"ok_for_simple_arith_logic_operands (operands, <MODE>mode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 0)
(xor:I (match_dup 1) (match_dup 2)))
(clobber (reg:CC R_FLAGS))])]
(not:I (match_operand:I 1 "reg_or_0_operand" "rO")))]
"ok_for_simple_arith_logic_operands (operands, <MODE>mode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 0) (not:I (match_dup 1)))
(clobber (reg:CC R_FLAGS))])]
""
(match_operand:QI 2 "reg_or_shift_operand" "r,K")))]
"ok_for_simple_arith_logic_operands (operands, <MODE>mode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 0)
(ashift:I (match_dup 1) (match_dup 2)))
(clobber (reg:CC R_FLAGS))])]
(match_operand:QI 2 "reg_or_shift_operand" "r,K")))]
"ok_for_simple_arith_logic_operands (operands, <MODE>mode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 0)
(ashiftrt:I (match_dup 1) (match_dup 2)))
(clobber (reg:CC R_FLAGS))])]
(match_operand:QI 2 "reg_or_shift_operand" "r,K")))]
"ok_for_simple_arith_logic_operands (operands, <MODE>mode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 0)
(lshiftrt:I (match_dup 1) (match_dup 2)))
(clobber (reg:CC R_FLAGS))])]
(truncate:QI (match_operand:HI 1 "register_operand" "r")))]
"ok_for_simple_arith_logic_operands (operands, QImode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 0) (truncate:QI (match_dup 1)))
(clobber (reg:CC R_FLAGS))])]
""
(truncate:HI (match_operand:SI 1 "register_operand" "r")))]
"ok_for_simple_arith_logic_operands (operands, HImode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 0) (truncate:HI (match_dup 1)))
(clobber (reg:CC R_FLAGS))])]
""
(truncate:SI (match_operand:DI 1 "register_operand" "r")))]
"ok_for_simple_arith_logic_operands (operands, SImode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 0) (truncate:SI (match_dup 1)))
(clobber (reg:CC R_FLAGS))])]
""
(sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
"ok_for_simple_arith_logic_operands (operands, HImode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 0) (sign_extend:HI (match_dup 1)))
(clobber (reg:CC R_FLAGS))])]
""
(sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
"ok_for_simple_arith_logic_operands (operands, SImode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 0) (sign_extend:SI (match_dup 1)))
(clobber (reg:CC R_FLAGS))])]
""
(sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
"ok_for_simple_arith_logic_operands (operands, SImode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_operand:SI 0 "register_operand" "")
(sign_extend:SI (match_operand:HI 1 "register_operand" "")))
(clobber (reg:CC R_FLAGS))])]
(sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
"ok_for_simple_arith_logic_operands (operands, DImode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 3) (match_dup 1))
(clobber (reg:CC R_FLAGS))])
(parallel [(set (match_dup 2)
(zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
"ok_for_simple_arith_logic_operands (operands, HImode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 0)
(ashift:HI (match_dup 2) (const_int 8)))
(clobber (reg:CC R_FLAGS))])
(zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
"ok_for_simple_arith_logic_operands (operands, SImode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 0)
(ashift:SI (match_dup 2) (const_int 24)))
(clobber (reg:CC R_FLAGS))])
(zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
"ok_for_simple_arith_logic_operands (operands, DImode)"
"#"
- "reload_completed"
+ "&& reload_completed"
[(parallel [(set (match_dup 3) (match_dup 1))
(clobber (reg:CC R_FLAGS))])
(set (match_dup 2) (const_int 0))]