unsigned int *num_states);
int (*get_dpm_clock_table)(void *handle,
struct dpm_clocks *clock_table);
+ int (*get_smu_prv_buf_details)(void *handle, void **addr, size_t *size);
};
struct metrics_table_header {
return 0;
}
+static int pp_get_prv_buffer_details(void *handle, void **addr, size_t *size)
+{
+ struct pp_hwmgr *hwmgr = handle;
+ struct amdgpu_device *adev = hwmgr->adev;
+
+ if (!addr || !size)
+ return -EINVAL;
+
+ *addr = NULL;
+ *size = 0;
+ mutex_lock(&hwmgr->smu_lock);
+ if (adev->pm.smu_prv_buffer) {
+ amdgpu_bo_kmap(adev->pm.smu_prv_buffer, addr);
+ *size = adev->pm.smu_prv_buffer_size;
+ }
+ mutex_unlock(&hwmgr->smu_lock);
+
+ return 0;
+}
+
static const struct amd_pm_funcs pp_dpm_funcs = {
.load_firmware = pp_dpm_load_fw,
.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
.set_xgmi_pstate = pp_set_xgmi_pstate,
.get_gpu_metrics = pp_get_gpu_metrics,
.gfx_state_change_set = pp_gfx_state_change_set,
+ .get_smu_prv_buf_details = pp_get_prv_buffer_details,
};
return ret;
}
+static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size)
+{
+ struct smu_context *smu = handle;
+ struct smu_table_context *smu_table = &smu->smu_table;
+ struct smu_table *memory_pool = &smu_table->memory_pool;
+
+ if (!addr || !size)
+ return -EINVAL;
+
+ *addr = NULL;
+ *size = 0;
+ mutex_lock(&smu->mutex);
+ if (memory_pool->bo) {
+ *addr = memory_pool->cpu_addr;
+ *size = memory_pool->size;
+ }
+ mutex_unlock(&smu->mutex);
+
+ return 0;
+}
static const struct amd_pm_funcs swsmu_pm_funcs = {
/* export for sysfs */
.get_max_sustainable_clocks_by_dc = smu_get_max_sustainable_clocks_by_dc,
.load_firmware = smu_load_microcode,
.gfx_state_change_set = smu_gfx_state_change_set,
+ .get_smu_prv_buf_details = smu_get_prv_buffer_details,
};
int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event,