radv: don't use the SPI barrier management bug workaround

Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 5a44efb..89a643a 100644 (file)
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1274,6 +1274,11 @@ calculate_gs_ring_sizes(struct radv_pipeline *pipeline, const struct radv_gs_sta
 static void si_multiwave_lds_size_workaround(struct radv_device *device,
                                             unsigned *lds_size)
 {
+       /* If tessellation is all offchip and on-chip GS isn't used, this
+        * workaround is not needed.
+        */
+       return;
+
        /* SPI barrier management bug:
         *   Make sure we have at least 4k of LDS in use to avoid the bug.
         *   It applies to workgroup sizes of more than one wavefront.