; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
declare i1 @llvm.vector.reduce.or.nxv1i1(<vscale x 1 x i1>)
declare i1 @llvm.vector.reduce.xor.nxv1i1(<vscale x 1 x i1>)
define signext i1 @vreduce_xor_nxv1i1(<vscale x 1 x i1> %v) {
+; RV32-LABEL: vreduce_xor_nxv1i1:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; RV32-NEXT: vcpop.m a0, v0
+; RV32-NEXT: slli a0, a0, 31
+; RV32-NEXT: srai a0, a0, 31
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vreduce_xor_nxv1i1:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; RV64-NEXT: vcpop.m a0, v0
+; RV64-NEXT: slli a0, a0, 63
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: ret
%red = call i1 @llvm.vector.reduce.xor.nxv1i1(<vscale x 1 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.xor.nxv2i1(<vscale x 2 x i1>)
define signext i1 @vreduce_xor_nxv2i1(<vscale x 2 x i1> %v) {
+; RV32-LABEL: vreduce_xor_nxv2i1:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; RV32-NEXT: vcpop.m a0, v0
+; RV32-NEXT: slli a0, a0, 31
+; RV32-NEXT: srai a0, a0, 31
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vreduce_xor_nxv2i1:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; RV64-NEXT: vcpop.m a0, v0
+; RV64-NEXT: slli a0, a0, 63
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: ret
%red = call i1 @llvm.vector.reduce.xor.nxv2i1(<vscale x 2 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.xor.nxv4i1(<vscale x 4 x i1>)
define signext i1 @vreduce_xor_nxv4i1(<vscale x 4 x i1> %v) {
+; RV32-LABEL: vreduce_xor_nxv4i1:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; RV32-NEXT: vcpop.m a0, v0
+; RV32-NEXT: slli a0, a0, 31
+; RV32-NEXT: srai a0, a0, 31
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vreduce_xor_nxv4i1:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; RV64-NEXT: vcpop.m a0, v0
+; RV64-NEXT: slli a0, a0, 63
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: ret
%red = call i1 @llvm.vector.reduce.xor.nxv4i1(<vscale x 4 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.xor.nxv8i1(<vscale x 8 x i1>)
define signext i1 @vreduce_xor_nxv8i1(<vscale x 8 x i1> %v) {
+; RV32-LABEL: vreduce_xor_nxv8i1:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; RV32-NEXT: vcpop.m a0, v0
+; RV32-NEXT: slli a0, a0, 31
+; RV32-NEXT: srai a0, a0, 31
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vreduce_xor_nxv8i1:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; RV64-NEXT: vcpop.m a0, v0
+; RV64-NEXT: slli a0, a0, 63
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: ret
%red = call i1 @llvm.vector.reduce.xor.nxv8i1(<vscale x 8 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.xor.nxv16i1(<vscale x 16 x i1>)
define signext i1 @vreduce_xor_nxv16i1(<vscale x 16 x i1> %v) {
+; RV32-LABEL: vreduce_xor_nxv16i1:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; RV32-NEXT: vcpop.m a0, v0
+; RV32-NEXT: slli a0, a0, 31
+; RV32-NEXT: srai a0, a0, 31
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vreduce_xor_nxv16i1:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; RV64-NEXT: vcpop.m a0, v0
+; RV64-NEXT: slli a0, a0, 63
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: ret
%red = call i1 @llvm.vector.reduce.xor.nxv16i1(<vscale x 16 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.xor.nxv32i1(<vscale x 32 x i1>)
define signext i1 @vreduce_xor_nxv32i1(<vscale x 32 x i1> %v) {
+; RV32-LABEL: vreduce_xor_nxv32i1:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; RV32-NEXT: vcpop.m a0, v0
+; RV32-NEXT: slli a0, a0, 31
+; RV32-NEXT: srai a0, a0, 31
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vreduce_xor_nxv32i1:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; RV64-NEXT: vcpop.m a0, v0
+; RV64-NEXT: slli a0, a0, 63
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: ret
%red = call i1 @llvm.vector.reduce.xor.nxv32i1(<vscale x 32 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.xor.nxv64i1(<vscale x 64 x i1>)
define signext i1 @vreduce_xor_nxv64i1(<vscale x 64 x i1> %v) {
+; RV32-LABEL: vreduce_xor_nxv64i1:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; RV32-NEXT: vcpop.m a0, v0
+; RV32-NEXT: slli a0, a0, 31
+; RV32-NEXT: srai a0, a0, 31
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vreduce_xor_nxv64i1:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; RV64-NEXT: vcpop.m a0, v0
+; RV64-NEXT: slli a0, a0, 63
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: ret
%red = call i1 @llvm.vector.reduce.xor.nxv64i1(<vscale x 64 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.add.nxv1i1(<vscale x 1 x i1>)
define signext i1 @vreduce_add_nxv1i1(<vscale x 1 x i1> %v) {
+; RV32-LABEL: vreduce_add_nxv1i1:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; RV32-NEXT: vcpop.m a0, v0
+; RV32-NEXT: slli a0, a0, 31
+; RV32-NEXT: srai a0, a0, 31
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vreduce_add_nxv1i1:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
+; RV64-NEXT: vcpop.m a0, v0
+; RV64-NEXT: slli a0, a0, 63
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: ret
%red = call i1 @llvm.vector.reduce.add.nxv1i1(<vscale x 1 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.add.nxv2i1(<vscale x 2 x i1>)
define signext i1 @vreduce_add_nxv2i1(<vscale x 2 x i1> %v) {
+; RV32-LABEL: vreduce_add_nxv2i1:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; RV32-NEXT: vcpop.m a0, v0
+; RV32-NEXT: slli a0, a0, 31
+; RV32-NEXT: srai a0, a0, 31
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vreduce_add_nxv2i1:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e8, mf4, ta, ma
+; RV64-NEXT: vcpop.m a0, v0
+; RV64-NEXT: slli a0, a0, 63
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: ret
%red = call i1 @llvm.vector.reduce.add.nxv2i1(<vscale x 2 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.add.nxv4i1(<vscale x 4 x i1>)
define signext i1 @vreduce_add_nxv4i1(<vscale x 4 x i1> %v) {
+; RV32-LABEL: vreduce_add_nxv4i1:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; RV32-NEXT: vcpop.m a0, v0
+; RV32-NEXT: slli a0, a0, 31
+; RV32-NEXT: srai a0, a0, 31
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vreduce_add_nxv4i1:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
+; RV64-NEXT: vcpop.m a0, v0
+; RV64-NEXT: slli a0, a0, 63
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: ret
%red = call i1 @llvm.vector.reduce.add.nxv4i1(<vscale x 4 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.add.nxv8i1(<vscale x 8 x i1>)
define signext i1 @vreduce_add_nxv8i1(<vscale x 8 x i1> %v) {
+; RV32-LABEL: vreduce_add_nxv8i1:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; RV32-NEXT: vcpop.m a0, v0
+; RV32-NEXT: slli a0, a0, 31
+; RV32-NEXT: srai a0, a0, 31
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vreduce_add_nxv8i1:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e8, m1, ta, ma
+; RV64-NEXT: vcpop.m a0, v0
+; RV64-NEXT: slli a0, a0, 63
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: ret
%red = call i1 @llvm.vector.reduce.add.nxv8i1(<vscale x 8 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.add.nxv16i1(<vscale x 16 x i1>)
define signext i1 @vreduce_add_nxv16i1(<vscale x 16 x i1> %v) {
+; RV32-LABEL: vreduce_add_nxv16i1:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; RV32-NEXT: vcpop.m a0, v0
+; RV32-NEXT: slli a0, a0, 31
+; RV32-NEXT: srai a0, a0, 31
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vreduce_add_nxv16i1:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e8, m2, ta, ma
+; RV64-NEXT: vcpop.m a0, v0
+; RV64-NEXT: slli a0, a0, 63
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: ret
%red = call i1 @llvm.vector.reduce.add.nxv16i1(<vscale x 16 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.add.nxv32i1(<vscale x 32 x i1>)
define signext i1 @vreduce_add_nxv32i1(<vscale x 32 x i1> %v) {
+; RV32-LABEL: vreduce_add_nxv32i1:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; RV32-NEXT: vcpop.m a0, v0
+; RV32-NEXT: slli a0, a0, 31
+; RV32-NEXT: srai a0, a0, 31
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vreduce_add_nxv32i1:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e8, m4, ta, ma
+; RV64-NEXT: vcpop.m a0, v0
+; RV64-NEXT: slli a0, a0, 63
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: ret
%red = call i1 @llvm.vector.reduce.add.nxv32i1(<vscale x 32 x i1> %v)
ret i1 %red
}
declare i1 @llvm.vector.reduce.add.nxv64i1(<vscale x 64 x i1>)
define signext i1 @vreduce_add_nxv64i1(<vscale x 64 x i1> %v) {
+; RV32-LABEL: vreduce_add_nxv64i1:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; RV32-NEXT: vcpop.m a0, v0
+; RV32-NEXT: slli a0, a0, 31
+; RV32-NEXT: srai a0, a0, 31
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vreduce_add_nxv64i1:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetvli a0, zero, e8, m8, ta, ma
+; RV64-NEXT: vcpop.m a0, v0
+; RV64-NEXT: slli a0, a0, 63
+; RV64-NEXT: srai a0, a0, 63
+; RV64-NEXT: ret
%red = call i1 @llvm.vector.reduce.add.nxv64i1(<vscale x 64 x i1> %v)
ret i1 %red
}