[CodeGen] clean up and add tests for scalar and-of-setcc; NFC

https://bugs.llvm.org/show_bug.cgi?id=32401

llvm-svn: 299034

diff --git a/llvm/test/CodeGen/ARM/and-setcc.ll b/llvm/test/CodeGen/ARM/and-setcc.ll
new file mode 100644 (file)
index 0000000..6dd6a44
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/and-setcc.ll
@@ -0,0 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=arm-eabi -mcpu=cortex-a8 | FileCheck %s
+
+define zeroext i1 @ne_neg1_and_ne_zero(i32 %x) nounwind {
+; CHECK-LABEL: ne_neg1_and_ne_zero:
+; CHECK:       @ BB#0:
+; CHECK-NEXT:    add r1, r0, #1
+; CHECK-NEXT:    mov r0, #0
+; CHECK-NEXT:    cmp r1, #1
+; CHECK-NEXT:    movwhi r0, #1
+; CHECK-NEXT:    bx lr
+  %cmp1 = icmp ne i32 %x, -1
+  %cmp2 = icmp ne i32 %x, 0
+  %and = and i1 %cmp1, %cmp2
+  ret i1 %and
+}
+
+; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401
+
+define zeroext i1 @cmpeq_logical(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
+; CHECK-LABEL: cmpeq_logical:
+; CHECK:       @ BB#0:
+; CHECK-NEXT:    cmp r2, r3
+; CHECK-NEXT:    mov r2, #0
+; CHECK-NEXT:    movweq r2, #1
+; CHECK-NEXT:    mov r12, #0
+; CHECK-NEXT:    cmp r0, r1
+; CHECK-NEXT:    movweq r12, #1
+; CHECK-NEXT:    and r0, r12, r2
+; CHECK-NEXT:    bx lr
+  %cmp1 = icmp eq i32 %a, %b
+  %cmp2 = icmp eq i32 %c, %d
+  %and = and i1 %cmp1, %cmp2
+  ret i1 %and
+}
+

diff --git a/llvm/test/CodeGen/ARM/setcc-sentinals.ll b/llvm/test/CodeGen/ARM/setcc-sentinals.ll
deleted file mode 100644 (file)
index dc45e0e..0000000
--- a/llvm/test/CodeGen/ARM/setcc-sentinals.ll
+++ /dev/null
@@ -1,14 +0,0 @@
-; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -asm-verbose=false %s -o - | FileCheck %s
-
-define zeroext i1 @test0(i32 %x) nounwind {
-; CHECK-LABEL: test0:
-; CHECK: add [[REG:(r[0-9]+)|(lr)]], r0, #1
-; CHECK-NEXT: mov r0, #0
-; CHECK-NEXT: cmp [[REG]], #1
-; CHECK-NEXT: movwhi r0, #1
-; CHECK-NEXT: bx  lr
-  %cmp1 = icmp ne i32 %x, -1
-  %not.cmp = icmp ne i32 %x, 0
-  %.cmp1 = and i1 %cmp1, %not.cmp
-  ret i1 %.cmp1
-}

diff --git a/llvm/test/CodeGen/PowerPC/and-setcc.ll b/llvm/test/CodeGen/PowerPC/and-setcc.ll
new file mode 100644 (file)
index 0000000..f7e2596
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/and-setcc.ll
@@ -0,0 +1,35 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -verify-machineinstrs | FileCheck %s
+
+define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) {
+; CHECK-LABEL: ne_neg1_and_ne_zero:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    addi 3, 3, 1
+; CHECK-NEXT:    li 4, 0
+; CHECK-NEXT:    li 12, 1
+; CHECK-NEXT:    cmpldi 3, 1
+; CHECK-NEXT:    isel 3, 12, 4, 1
+; CHECK-NEXT:    blr
+  %cmp1 = icmp ne i64 %x, -1
+  %cmp2 = icmp ne i64 %x, 0
+  %and = and i1 %cmp1, %cmp2
+  ret i1 %and
+}
+
+; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401
+
+define zeroext i1 @cmpeq_logical(i16 zeroext %a, i16 zeroext %b, i16 zeroext %c, i16 zeroext %d) {
+; CHECK-LABEL: cmpeq_logical:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    cmpw 0, 3, 4
+; CHECK-NEXT:    cmpw 1, 5, 6
+; CHECK-NEXT:    li 3, 1
+; CHECK-NEXT:    crnand 20, 2, 6
+; CHECK-NEXT:    isel 3, 0, 3, 20
+; CHECK-NEXT:    blr
+  %cmp1 = icmp eq i16 %a, %b
+  %cmp2 = icmp eq i16 %c, %d
+  %and = and i1 %cmp1, %cmp2
+  ret i1 %and
+}
+

diff --git a/llvm/test/CodeGen/X86/and-setcc.ll b/llvm/test/CodeGen/X86/and-setcc.ll
new file mode 100644 (file)
index 0000000..080331a
--- /dev/null
+++ b/llvm/test/CodeGen/X86/and-setcc.ll
@@ -0,0 +1,33 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
+
+define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) nounwind {
+; CHECK-LABEL: ne_neg1_and_ne_zero:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    incq %rdi
+; CHECK-NEXT:    cmpq $1, %rdi
+; CHECK-NEXT:    seta %al
+; CHECK-NEXT:    retq
+  %cmp1 = icmp ne i64 %x, -1
+  %cmp2 = icmp ne i64 %x, 0
+  %and = and i1 %cmp1, %cmp2
+  ret i1 %and
+}
+
+; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401
+
+define zeroext i1 @cmpeq_logical(i8 %a, i8 %b, i8 %c, i8 %d) nounwind {
+; CHECK-LABEL: cmpeq_logical:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    cmpb %sil, %dil
+; CHECK-NEXT:    sete %sil
+; CHECK-NEXT:    cmpb %cl, %dl
+; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    andb %sil, %al
+; CHECK-NEXT:    retq
+  %cmp1 = icmp eq i8 %a, %b
+  %cmp2 = icmp eq i8 %c, %d
+  %and = and i1 %cmp1, %cmp2
+  ret i1 %and
+}
+

diff --git a/llvm/test/CodeGen/X86/setcc-sentinals.ll b/llvm/test/CodeGen/X86/setcc-sentinals.ll
deleted file mode 100644 (file)
index d36e678..0000000
--- a/llvm/test/CodeGen/X86/setcc-sentinals.ll
+++ /dev/null
@@ -1,13 +0,0 @@
-; RUN: llc < %s -mcpu=generic -march=x86-64 -asm-verbose=false | FileCheck %s
-
-define zeroext i1 @test0(i64 %x) nounwind {
-; CHECK-LABEL: test0:
-; CHECK-NEXT: incq %[[X:rdi|rcx]]
-; CHECK-NEXT: cmpq $1, %[[X]]
-; CHECK-NEXT: seta %al
-; CHECK-NEXT: ret
-  %cmp1 = icmp ne i64 %x, -1
-  %not.cmp = icmp ne i64 %x, 0
-  %.cmp1 = and i1 %cmp1, %not.cmp
-  ret i1 %.cmp1
-}