agx: Match order for designated initializers
authorAlyssa Rosenzweig <alyssa@rosenzweig.io>
Tue, 12 Apr 2022 22:06:08 +0000 (18:06 -0400)
committerAlyssa Rosenzweig <alyssa@rosenzweig.io>
Mon, 2 May 2022 01:58:29 +0000 (21:58 -0400)
Required to compile our headers with C++, to allow us to use GTest unit tests.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16268>

src/asahi/compiler/agx_compile.h
src/asahi/compiler/agx_compiler.h

index 8df4576..4db9b21 100644 (file)
@@ -197,40 +197,36 @@ agx_compile_shader_nir(nir_shader *nir,
       struct agx_shader_info *out);
 
 static const nir_shader_compiler_options agx_nir_options = {
-   .lower_scmp = true,
+   .lower_fdiv = true,
+   .fuse_ffma16 = true,
+   .fuse_ffma32 = true,
    .lower_flrp16 = true,
    .lower_flrp32 = true,
-   .lower_ffract = true,
+   .lower_fpow = true,
    .lower_fmod = true,
-   .lower_fdiv = true,
+   .lower_ifind_msb = true,
+   .lower_find_lsb = true,
+   .lower_scmp = true,
    .lower_isign = true,
+   .lower_fsign = true,
    .lower_iabs = true,
-   .lower_fpow = true,
-   .lower_find_lsb = true,
-   .lower_ifind_msb = true,
    .lower_fdph = true,
-   .lower_wpos_pntc = true,
-   .lower_fsign = true,
-   .lower_rotate = true,
+   .lower_ffract = true,
    .lower_pack_split = true,
    .lower_insert_byte = true,
    .lower_insert_word = true,
-   .lower_uniforms_to_ubo = true,
    .lower_cs_local_index_to_id = true,
-
-   .lower_doubles_options = nir_lower_dmod,
-   .lower_int64_options = ~(nir_lower_iadd64 | nir_lower_imul_2x32_64),
-
-   .force_indirect_unrolling = (nir_var_shader_in | nir_var_shader_out | nir_var_function_temp),
-
-   .has_fsub = true,
-   .has_isub = true,
    .has_cs_global_id = true,
-
+   .lower_wpos_pntc = true,
    .vectorize_io = true,
-   .fuse_ffma16 = true,
-   .fuse_ffma32 = true,
    .use_interpolated_input_intrinsics = true,
+   .lower_rotate = true,
+   .has_fsub = true,
+   .has_isub = true,
+   .lower_uniforms_to_ubo = true,
+   .force_indirect_unrolling = (nir_var_shader_in | nir_var_shader_out | nir_var_function_temp),
+   .lower_int64_options = (nir_lower_int64_options) ~(nir_lower_iadd64 | nir_lower_imul_2x32_64),
+   .lower_doubles_options = nir_lower_dmod,
 };
 
 #endif
index 3c609b2..e2cd20d 100644 (file)
@@ -98,9 +98,9 @@ static inline agx_index
 agx_get_index(unsigned value, enum agx_size size)
 {
    return (agx_index) {
-      .type = AGX_INDEX_NORMAL,
       .value = value,
-      .size = size
+      .size = size,
+      .type = AGX_INDEX_NORMAL,
    };
 }
 
@@ -108,9 +108,9 @@ static inline agx_index
 agx_immediate(uint16_t imm)
 {
    return (agx_index) {
-      .type = AGX_INDEX_IMMEDIATE,
       .value = imm,
-      .size = AGX_SIZE_32
+      .size = AGX_SIZE_32,
+      .type = AGX_INDEX_IMMEDIATE,
    };
 }
 
@@ -126,9 +126,9 @@ static inline agx_index
 agx_register(uint8_t imm, enum agx_size size)
 {
    return (agx_index) {
-      .type = AGX_INDEX_REGISTER,
       .value = imm,
-      .size = size
+      .size = size,
+      .type = AGX_INDEX_REGISTER,
    };
 }
 
@@ -136,9 +136,9 @@ static inline agx_index
 agx_nir_register(unsigned imm, enum agx_size size)
 {
    return (agx_index) {
-      .type = AGX_INDEX_NIR_REGISTER,
       .value = imm,
-      .size = size
+      .size = size,
+      .type = AGX_INDEX_NIR_REGISTER,
    };
 }
 
@@ -147,9 +147,9 @@ static inline agx_index
 agx_uniform(uint8_t imm, enum agx_size size)
 {
    return (agx_index) {
-      .type = AGX_INDEX_UNIFORM,
       .value = imm,
-      .size = size
+      .size = size,
+      .type = AGX_INDEX_UNIFORM,
    };
 }