f_max = <200000000>;
max_req_size = <0x20000>; /**128KB*/
gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>;
- tx_delay = <8>;
hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>;
card_type = <1>;
/* 1:mmc card(include eMMC),
f_max = <200000000>;
max_req_size = <0x20000>; /**128KB*/
gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>;
- tx_delay = <8>;
hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>;
card_type = <1>;
/* 1:mmc card(include eMMC),
f_max = <200000000>;
max_req_size = <0x20000>; /**128KB*/
gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>;
- tx_delay = <8>;
hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>;
card_type = <1>;
/* 1:mmc card(include eMMC),
f_max = <200000000>;
max_req_size = <0x20000>; /**128KB*/
gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>;
- tx_delay = <8>;
hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>;
card_type = <1>;
/* 1:mmc card(include eMMC),
caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
f_min = <400000>;
f_max = <200000000>;
- tx_delay = <6>;
max_req_size = <0x20000>; /**128KB*/
gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>;
hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>;
caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
f_min = <400000>;
f_max = <200000000>;
- tx_delay = <6>;
max_req_size = <0x20000>; /**128KB*/
gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>;
hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>;
caps2 = "MMC_CAP2_HS200", "MMC_CAP2_HS400";
f_min = <400000>;
f_max = <200000000>;
- tx_delay = <6>;
max_req_size = <0x20000>; /**128KB*/
gpio_dat3 = <&gpio BOOT_3 GPIO_ACTIVE_HIGH>;
hw_reset = <&gpio BOOT_9 GPIO_ACTIVE_HIGH>;
.ds_pin_poll = 0x3c,
.ds_pin_poll_en = 0x4a,
.ds_pin_poll_bit = 11,
+ .sdmmc.init.core_phase = 3,
+ .sdmmc.init.tx_phase = 0,
+ .sdmmc.init.rx_phase = 0,
+ .sdmmc.hs.core_phase = 3,
+ .sdmmc.ddr.core_phase = 2,
+ .sdmmc.hs2.core_phase = 2,
+ .sdmmc.hs4.tx_delay = 6,
+ .sdmmc.sd_hs.core_phase = 2,
+ .sdmmc.sdr104.core_phase = 2,
};
static struct meson_mmc_data mmc_data_axg = {
.chip_type = MMC_CHIP_AXG,
.ds_pin_poll = 0x3e,
.ds_pin_poll_en = 0x4c,
.ds_pin_poll_bit = 13,
+ .sdmmc.init.core_phase = 3,
+ .sdmmc.init.tx_phase = 0,
+ .sdmmc.init.rx_phase = 0,
+ .sdmmc.hs.core_phase = 3,
+ .sdmmc.ddr.core_phase = 2,
+ .sdmmc.hs2.core_phase = 2,
+ .sdmmc.hs4.tx_delay = 8,
+ .sdmmc.sd_hs.core_phase = 2,
+ .sdmmc.sdr104.core_phase = 2,
};
static struct meson_mmc_data mmc_data_gxlx = {
.chip_type = MMC_CHIP_GXLX,
u32 vconf = 0;
struct sd_emmc_config *pconf = (struct sd_emmc_config *)&vconf;
struct amlsd_platform *pdata = host->pdata;
+ struct mmc_phase *init = &(host->data->sdmmc.init);
writel(0, host->base + SD_EMMC_CLOCK_V3);
#ifndef SD_EMMC_CLK_CTRL
vclkc = 0;
pclkc->div = 60; /* 400KHz */
pclkc->src = 0; /* 0: Crystal 24MHz */
- pclkc->core_phase = 3; /* 2: 180 phase */
- pclkc->rx_phase = 0;
- pclkc->tx_phase = 0;
+ pclkc->core_phase = init->core_phase; /* 2: 180 phase */
+ pclkc->rx_phase = init->rx_phase;
+ pclkc->tx_phase = init->tx_phase;
pclkc->always_on = 1; /* Keep clock always on */
writel(vclkc, host->base + SD_EMMC_CLOCK_V3);
pdata->clkc = vclkc;
u32 adjust;
struct sd_emmc_adjust_v3 *gadjust = (struct sd_emmc_adjust_v3 *)&adjust;
u8 clk_div = 0;
+ struct para_e *para = &(host->data->sdmmc);
vctrl = readl(host->base + SD_EMMC_CFG);
if ((timing == MMC_TIMING_MMC_HS400) ||
adjust = readl(host->base + SD_EMMC_ADJUST_V3);
gadjust->ds_enable = 1;
writel(adjust, host->base + SD_EMMC_ADJUST_V3);
- clkc->tx_delay = pdata->tx_delay;
+ clkc->tx_delay = para->hs4.tx_delay;
}
pr_info("%s: try set sd/emmc to HS400 mode\n",
mmc_hostname(host->mmc));
clk_div++;
clkc->div = clk_div / 2;
if (aml_card_type_mmc(pdata))
- clkc->core_phase = 2;
+ clkc->core_phase = para->ddr.core_phase;
pr_info("%s: try set sd/emmc to DDR mode\n",
mmc_hostname(host->mmc));
} else if (timing == MMC_TIMING_MMC_HS) {
if (host->data->chip_type < MMC_CHIP_G12A)
- clkc->core_phase = 3;
+ clkc->core_phase = para->hs.core_phase;
else
clkc->core_phase = 2;
- } else if ((timing == MMC_TIMING_MMC_HS200)
- || ((timing == MMC_TIMING_SD_HS)
- && aml_card_type_non_sdio(pdata))
- || (timing == MMC_TIMING_UHS_SDR104)) {
- clkc->core_phase = 2;
+ } else if (timing == MMC_TIMING_MMC_HS200) {
+ clkc->core_phase = para->hs2.core_phase;
+ } else if ((timing == MMC_TIMING_SD_HS)
+ && aml_card_type_non_sdio(pdata)) {
+ clkc->core_phase = para->sd_hs.core_phase;
+ } else if (timing == MMC_TIMING_UHS_SDR104) {
+ clkc->core_phase = para->sdr104.core_phase;
} else
ctrl->ddr = 0;
MMC_CHIP_G12A = 0x28,
};
+struct mmc_phase {
+ unsigned int core_phase;
+ unsigned int tx_phase;
+ unsigned int rx_phase;
+ unsigned int tx_delay;
+};
+
+struct para_e {
+ struct mmc_phase init;
+ struct mmc_phase hs;
+ struct mmc_phase ddr;
+ struct mmc_phase hs2;
+ struct mmc_phase hs4;
+ struct mmc_phase sd_hs;
+ struct mmc_phase sdr104;
+};
+
struct meson_mmc_data {
enum mmc_chip_e chip_type;
unsigned int pinmux_base;
unsigned int ds_pin_poll;
unsigned int ds_pin_poll_en;
unsigned int ds_pin_poll_bit;
+ struct para_e sdmmc;
};
struct amlsd_host;